Shielded gate mosfet and method of manufacturing the same

CN116864395BActive Publication Date: 2026-10-16HUA HONG SEMICON WUXI LTD
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Patent Information

Application Number
CN202310917514.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-07-25
Publication Date
2026-10-16
Estimated Expiration
2043-07-25

AI Technical Summary

Technical Problem

[0006]本申请提供了一种屏蔽栅MOSFET及其制备方法,可以解决源端引出区域中源极和栅极短接造成IGSS漏电超出芯片漏电量设计规格的问题

Benefits of technology

[0045] This application avoids the influence of wet etching of the first gate oxide layer/second gate oxide layer on the main trench and auxiliary trench covering the source lead-out region by forming a patterned first photoresist layer. Furthermore, by forming a patterned second photoresist layer covering the main trench and auxiliary trench covering the source lead-out region, it avoids the influence of wet etching of the first gate oxide layer/second gate oxide layer on the main trench used for source lead-out. This also avoids side-cutting defects on both sides of the top of the first polysilicon layer in the main trench of the source lead-out region, thereby preventing short circuits between the source and gate in the source lead-out region, reducing IGSS leakage current, and improving the electrical performance of the device.

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Abstract

The application provides a shield gate MOSFET and a preparation method thereof. The preparation method comprises the following steps: forming multiple groups of deep grooves in an epitaxial layer; forming a first gate oxide layer; forming a first polysilicon layer; forming a patterned first photoresist layer covering a source terminal leading-out area; removing the first polysilicon layer in the gate terminal leading-out area and the first gate oxide layer on the surface of the epitaxial layer; forming a second gate oxide layer; forming a patterned second photoresist layer covering the source terminal leading-out area; removing part of the second gate oxide layer in the deep groove of the gate terminal leading-out area; and forming a second polysilicon layer. The application forms the first photoresist layer / second photoresist layer covering the main groove and the auxiliary groove of the source terminal leading-out area, avoids the influence of wet etching of the first gate oxide layer / second gate oxide layer on the main groove used for source terminal leading-out in the subsequent process, avoids the side etching of the top side wall of the main groove, thereby avoiding the short connection of the source terminal and the gate terminal, and reducing the IGSS leakage.
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