A CMOS voltage reference source

Abstract

The application discloses a CMOS voltage reference source, comprising a first-stage circuit and a second-stage circuit, the first-stage circuit is used for generating a bias current, the second-stage circuit is coupled to the first-stage circuit, the second-stage circuit is used for outputting a reference voltage, and a gate and a substrate of a PMOS tube in the first-stage circuit are connected with a reference voltage output end. The application sets a transconductance enhancement transistor, enhances the transconductance of the transistor through self-bias of the reference voltage, improves the power supply rejection ratio of the CMOS voltage reference source, designs a full PMOS voltage reference source composed of PMOS tubes, avoids the influence of different types of transistors on the output voltage, sets a working threshold of the PMOS tube, and reduces the power consumption of the CMOS voltage reference source.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more particularly to a CMOS voltage reference source. Background Technology

[0002] Voltage references are fundamental modules in power management chips that generate various internal voltages, enabling continuous operation for voltage management and rapid response. In many emerging energy-constrained systems such as the Internet of Things (IoT), biomedical devices, and self-powered wearable electronics, it is crucial for integrated circuits to maintain extremely low power consumption during typical operation. Low-power voltage references can reduce standby power consumption and extend chip lifespan under limited energy sources, showing broad application prospects in mixed-signal chips such as sensors, analog-to-digital converters (ADCs), and DC-DC converters. Traditional bandgap references, due to their use of bipolar junction transistors (BJTs), have relatively high operating voltages and power consumption, while CMOS voltage references feature low voltage and low power consumption.

[0003] However, mixed-signal chips integrate a large number of analog and digital circuits, and the operation of these circuits can cause fluctuations in the power supply voltage, thus affecting the accuracy of the output voltage of the CMOS voltage reference. Therefore, it is necessary to study a low-power CMOS voltage reference with enhanced power supply rejection ratio. The academic paper "A -40℃ to 140℃ Picowatt CMOS Voltage Reference With 0.25-V Power Supply" proposes a CMOS voltage reference that reduces the impact of using different types of transistors on the output voltage by reducing the transistor size ratio. However, the small-size transistors have very low transconductance, resulting in high impedance to ground and low power supply rejection ratio. Summary of the Invention

[0004] In order to solve at least one of the technical problems mentioned above, the present invention aims to provide a CMOS voltage reference source to improve the power supply rejection ratio of the CMOS voltage reference source.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] The present invention provides a CMOS voltage reference source, including a first-stage circuit and a second-stage circuit. The first-stage circuit is used to generate a bias current, and the second-stage circuit is coupled to the first-stage circuit and used to output a reference voltage. The gate and substrate of a PMOS transistor in the first-stage circuit are connected and connected to the reference voltage output terminal.

[0007] Preferably, the first stage circuit is a pre-bias circuit, including a first PMOS transistor and a second PMOS transistor. The source, gate, and substrate of the first PMOS transistor are connected and connected to a power supply. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate and substrate of the second PMOS transistor are connected and connected to a reference voltage output terminal. The drain of the second PMOS transistor is grounded.

[0008] Preferably, the second-stage circuit is a reference voltage generation circuit, including a third PMOS transistor and a fourth PMOS transistor. The source, gate, and substrate of the third PMOS transistor are connected and connected to the drain of the first PMOS transistor. The source and substrate of the fourth PMOS transistor are connected and connected to the drain of the third PMOS transistor. The gate and drain of the fourth PMOS transistor are connected and grounded.

[0009] Preferably, the first and third PMOS transistors are mid-threshold PMOS transistors, and the second and fourth PMOS transistors are ordinary threshold PMOS transistors.

[0010] Preferably, the second PMOS transistor operates in the subthreshold region.

[0011] Preferably, the current flowing through the PMOS transistor is:

[0012]

[0013] Where μ is the carrier mobility, K is the PMOS transistor size ratio, and C ox V is the gate oxide capacitance, m is the subthreshold slope factor of the PMOS transistor, and V T For thermal voltage, V GS V is the gate-source voltage of the PMOS transistor. TH This is the threshold voltage of the PMOS transistor.

[0014] Preferably, the reference voltage is:

[0015]

[0016] Among them, the first factor is negatively correlated with temperature, and the second factor is positively correlated with temperature.

[0017] Preferably, the transconductance of the second PMOS transistor is:

[0018]

[0019] Among them, g m λ is the transconductance of the PMOS transistor, and λ is the threshold voltage system number.

[0020] Preferably, the power supply rejection ratio obtained from analyzing the small-signal model is:

[0021]

[0022] Among them, g mb For transconductance, r ds This is the on-resistance of the PMOS transistor.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention incorporates a transconductance enhancement transistor, which enhances the transconductance of the transistor through self-biasing of the reference voltage, thereby improving the power supply rejection ratio of the CMOS voltage reference source. The all-PMOS voltage reference source, composed entirely of PMOS transistors, avoids the influence of using different types of transistors on the output voltage. By setting the operating threshold of the PMOS transistors, the power consumption of the CMOS voltage reference source is reduced.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions disclosed in this invention.

[0028] Figure 1 This is a circuit structure diagram of the present invention;

[0029] Figure 2 Reference voltage V REF Temperature characteristic curve;

[0030] Figure 3 This is a circuit diagram of the transconductance enhancement-mode transistor of the present invention;

[0031] Figure 4 This is a circuit diagram of a diode-connected transistor.

[0032] Figure 5 A comparison curve of transconductance enhancement effect;

[0033] Figure 6 This is a circuit diagram using a diode-connected transistor.

[0034] Figure 7 This is a comparison curve of the power supply rejection ratio enhancement effect. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0037] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0038] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of the invention.

[0040] CMOS voltage references are widely used in the integrated circuit field due to their low voltage and low power consumption. However, the inventors discovered that the transconductance of small-sized diode-connected transistors is very small, resulting in a low power supply rejection ratio (PSRR) for the CMOS voltage reference and affecting the accuracy of its output voltage. To address this issue, this invention incorporates transconductance-enhancing transistors, which enhance the transconductance of the transistors through self-biasing of the reference voltage, thereby improving the PSRR of the CMOS voltage reference. Furthermore, the design utilizes an all-PMOS voltage reference composed entirely of PMOS transistors, avoiding the impact of using different types of transistors on the output voltage. Finally, by setting the operating threshold of the PMOS transistors, the power consumption of the CMOS voltage reference is reduced.

[0041] A CMOS voltage reference source, see Figure 1 It includes a first-stage circuit and a second-stage circuit. The first-stage circuit generates a bias current, and the second-stage circuit is coupled to the first-stage circuit and is used to output a reference voltage V. REF In the first-stage circuit, the gate and substrate of a PMOS transistor are connected together and connected to the reference voltage output terminal.

[0042] Specifically, the first-stage circuit is a pre-bias circuit, including a first PMOS transistor M1 and a second PMOS transistor M2. The source, gate, and substrate of the first PMOS transistor M1 are connected and connected to the power supply. The drain of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M2. The gate and substrate of the second PMOS transistor M2 are connected and connected to the reference voltage output terminal. The drain of the second PMOS transistor M2 is grounded. The second-stage circuit is a reference voltage generation circuit, including a third PMOS transistor M3 and a fourth PMOS transistor M4. The source, gate, and substrate of the third PMOS transistor M3 are connected and connected to the drain of the first PMOS transistor M1. The source and substrate of the fourth PMOS transistor M4 are connected and connected to the drain of the third PMOS transistor M3. The gate and drain of the fourth PMOS transistor M4 are connected and grounded.

[0043] The second PMOS transistor M2 of this invention is a transconductance enhancement-mode transistor, which utilizes a reference voltage V REF The gate and substrate of the second PMOS transistor M2 are biased to enhance the transconductance of the second PMOS transistor M2, reduce the impedance to ground of the output node of the first stage circuit, and thus improve the power supply rejection ratio.

[0044] Preferably, the first PMOS transistor M1 and the third PMOS transistor M3 are medium threshold PMOS transistors, and the second PMOS transistor M2 and the fourth PMOS transistor M4 are ordinary threshold PMOS transistors.

[0045] Preferably, the second PMOS transistor M2 operates in the subthreshold region.

[0046] Preferably, the current flowing through the PMOS transistor is:

[0047]

[0048] Where μ is the carrier mobility, K is the PMOS transistor size ratio, and C ox V is the gate oxide capacitance, m is the subthreshold slope factor of the PMOS transistor, and V T For thermal voltage, V GS V is the gate-source voltage of the PMOS transistor. TH This is the threshold voltage of the PMOS transistor.

[0049] The currents flowing through the third PMOS transistor M3 and the fourth PMOS transistor M4 can be obtained from the above formula, which are:

[0050]

[0051]

[0052] Because the current flowing through the third PMOS transistor M3 and the fourth PMOS transistor M4 is equal, the specific reference voltage V can be obtained. REF for:

[0053]

[0054] The first factor is the threshold voltage difference between the third PMOS transistor M3 and the fourth PMOS transistor M4, which is negatively correlated with temperature. The second factor is positively correlated with temperature. (See also...) Figure 2 By adjusting the size ratio of the third PMOS transistor M3 and the fourth PMOS transistor M4, the magnitude of the positive temperature coefficient of the second factor can be changed. This positive temperature coefficient is then superimposed on the first factor, causing the second-stage circuit to output a temperature-independent reference voltage V. REF .

[0055] See Figure 3 The second PMOS transistor M2 of this invention is a transconductance enhancement-type PMOS transistor, and the simplified transistor threshold formula is as follows:

[0056] V TH =V TH0 -λV BS

[0057] Where λ is the threshold voltage system number, V BS This is the transistor substrate-source voltage.

[0058] For transconductance enhancement transistors, V BS Less than 0 and equal to V GS The transconductance of the second PMOS transistor M2 can be obtained as follows:

[0059]

[0060] See Figure 4 For diode-connected transistors, V BS It equals 0. Therefore, the transconductance of a diode-connected transistor can be obtained as:

[0061]

[0062] In summary, it can be seen that the transconductance of the second PMOS transistor M2 is the same as that of a diode-connected transistor. times

[0063]

[0064] See Figure 5 The upper curve represents the transistor with enhanced transconductance, and the lower curve represents the transistor without enhanced transconductance. Under the same conditions, the transconductance of the transistor without enhanced transconductance increases very little with changes in gate-source voltage, while the transconductance of the transistor with enhanced transconductance increases exponentially with changes in gate-source voltage. Numerically, when the gate-source voltage of the transistor is 200mV, the effect of enhanced transconductance is 6.9 times better than that without enhanced transconductance.

[0065] The power supply rejection ratio obtained under the small-signal model is:

[0066]

[0067] Among them, g mb For transconductance, r ds This is the on-resistance of the PMOS transistor.

[0068] See Figure 6 This CMOS voltage reference uses a diode-connected transistor. Analysis of the small-signal model yields the current rejection ratio (PSRR) as follows:

[0069]

[0070] Comparing the two equations, it can be seen that the power supply rejection ratio (PSRR) of the CMOS voltage reference using a transconductance enhancement-mode transistor is better than that of the CMOS voltage reference using a diode-connected transistor.

[0071] See Figure 7At a frequency of 100Hz, the power supply rejection ratio (PSRR) with the transconductance enhancement circuit is -83.76dB, while the PSRR without the transconductance enhancement circuit is -65.90dB. The PSRR with the transconductance enhancement circuit is 18dB higher than that without. It should be noted that the PSRR will increase even more as the gate-source voltage of the second PMOS transistor M2 increases. However, considering low power consumption, the gate-source voltage of the second PMOS transistor M2 is set below the threshold voltage, allowing it to operate in the subthreshold region.

[0072] This invention incorporates a transconductance enhancement transistor, which enhances the transconductance of the transistor through self-biasing of the reference voltage, thereby improving the power supply rejection ratio of the CMOS voltage reference source. The design utilizes an all-PMOS voltage reference source composed entirely of PMOS transistors, avoiding the impact of using different types of transistors on the output voltage. Furthermore, the invention sets the operating threshold of the PMOS transistors to reduce the power consumption of the CMOS voltage reference source.

[0073] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A CMOS voltage reference source, characterized in that, The circuit includes a first-stage circuit and a second-stage circuit. The first-stage circuit generates a bias current, and the second-stage circuit is coupled to the first-stage circuit and outputs a reference voltage. The gate and substrate of a PMOS transistor in the first-stage circuit are connected, and it is also connected to the reference voltage output terminal. The current flowing through the PMOS transistor is: ； in, For carrier mobility, The size ratio of the PMOS transistor. Gate oxide capacitor, This is the subthreshold slope factor of the PMOS transistor. Thermoelectric voltage, This is the gate-source voltage of the PMOS transistor. This is the threshold voltage of the PMOS transistor; The first stage circuit is a pre-bias circuit, including a first PMOS transistor and a second PMOS transistor. The source, gate and substrate of the first PMOS transistor are connected and connected to the power supply. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate and substrate of the second PMOS transistor are connected and connected to the reference voltage output terminal. The drain of the second PMOS transistor is grounded. The second stage circuit is a reference voltage generation circuit, including a third PMOS transistor and a fourth PMOS transistor. The source, gate and substrate of the third PMOS transistor are connected and connected to the drain of the first PMOS transistor. The source and substrate of the fourth PMOS transistor are connected and connected to the drain of the third PMOS transistor. The gate and drain of the fourth PMOS transistor are connected and grounded. The first and third PMOS transistors are medium-threshold PMOS transistors, while the second and fourth PMOS transistors are normal-threshold PMOS transistors.

2. The CMOS voltage reference source according to claim 1, characterized in that, The second PMOS transistor operates in the subthreshold region.

3. The CMOS voltage reference source according to claim 1, characterized in that, The reference voltage is: ； Among them, the first factor is negatively correlated with temperature, and the second factor is positively correlated with temperature.

4. The CMOS voltage reference source according to claim 1, characterized in that, The transconductance of the second PMOS transistor is: ； in, The transconductance of the PMOS transistor. The threshold voltage system number.

5. The CMOS voltage reference source according to claim 4, characterized in that, Analysis of the small-signal model yields the following power supply rejection ratio: ； in, For transconductance, This is the on-resistance of the PMOS transistor.

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