A smart antenna array structure integrating power supply, control, and communication.

Abstract

This invention discloses a smart antenna array structure based on integrated power supply, control, and communication, comprising: a radio frequency (RF) power divider network; the RF power divider network divides the RF signal into multiple paths, feeding each RF signal into a coupler, which further divides the RF signal according to the coupling coefficient; the output of the coupler outputs a first RF signal, which is fed into the antenna link; the coupling end of the coupler outputs a second RF signal, which is fed into a passive on-chip system. In terms of power supply, the antenna utilizes the rectified RF signal to power the low-power antenna link; in terms of control, it uses a communication protocol to network-control the RF unit, completing functions such as beam control and shaping; in terms of communication, it implements a communication protocol and integrates communication sensing.

Description

Technical Field

[0001] This invention belongs to the field of antenna design research, and in particular relates to a smart antenna array structure based on the integration of power supply, control and communication. Background Technology

[0002] Electronically controlled antenna arrays, such as reconfigurable and phased array antenna arrays, are fundamental components of high-frequency communication hardware. These arrays are designed to provide specific communication scenarios and channel characteristics; however, their development and deployment face several challenges. These challenges primarily stem from their anticipated large-scale production, current manufacturing technologies, integration with active RF chains, compact size, dense circuitry, and limitations of post-manufacturing tuning. Consequently, antenna array designers face conflicting design requirements and constraints.

[0003] Among these factors, the high deployment cost and complex network structure are significant reasons affecting large-scale production and deployment. This is mainly because, compared to physically controlled antenna arrays, electronically controlled antenna arrays, while reducing components such as dynamometers, still require large-scale power and control networks. For example, in phased array antenna arrays, the power and control networks required for adjustable RF modules such as phase shifters increase in complexity rapidly with the increase in antenna elements. Therefore, it is necessary to simplify and redeploy these large-scale power and control networks to reduce antenna costs and simplify the antenna structure. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies by providing a smart antenna array structure that integrates power supply, control, and communication.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: a smart antenna array structure based on integrated power supply, control, and communication, comprising: a radio frequency power divider network; the radio frequency power divider network divides the radio frequency signal into multiple paths, feeds each path of the radio frequency signal into a coupler, and the coupler further divides the radio frequency signal according to the coupling coefficient; the output end of the coupler outputs a first radio frequency signal and feeds it into the antenna link; the coupling end of the coupler outputs a second radio frequency signal and feeds it into the passive on-chip system.

[0006] Furthermore, the antenna link includes an adjustable radio frequency module and an antenna connected thereto.

[0007] Furthermore, the RF power divider network, couplers, antenna links, and passive on-chip systems are all connected via coplanar waveguides characterized by straight lines.

[0008] Furthermore, the passive system-on-chip is used to boost and rectify the radio frequency signal to output a DC voltage VDD to power the adjustable radio frequency module; at the same time, the passive system-on-chip analyzes the radio frequency signal and outputs a digital control signal VCTL to control the adjustable radio frequency module.

[0009] Furthermore, the passive system-on-chip uses the same radio frequency communication protocol as the external transponder. While the antenna array communicates with the external transponder, the radio frequency transceiver can also send commands to the passive system-on-chip to control the antenna array.

[0010] Furthermore, the adjustable radio frequency module employs a radio frequency switch or a phase shifter; the adjustable radio frequency module changes the amplitude and phase of the radio frequency signal in the antenna link it is connected to, thereby achieving amplitude gain variation and phase variation.

[0011] Furthermore, the antenna is a patch antenna; the antenna transmits or receives radio frequency signals in the antenna link into free space, and the antenna is controlled by an adjustable radio frequency module to achieve electromagnetic wave beam control and beamforming.

[0012] Furthermore, the passive on-chip system includes:

[0013] The radio frequency (RF) front end is used to receive radio frequency signals and return response signals.

[0014] A charge pump, one end of which is connected to an RF front-end, includes a multi-stage boost circuit for increasing the reference voltage of the RF signal;

[0015] A comparator, connected to the other end of a charge pump, is used to convert the boosted radio frequency signal into a digital signal.

[0016] A voltage rectifier, connected to the output of the comparator, rectifies the boosted radio frequency signal and outputs a first DC voltage VCORE and a second DC voltage VREGL; wherein, the first DC voltage VCORE is used to power the digital processor, and the second DC voltage VREGL is used to power external devices.

[0017] A digital processor is used to process the parsed digital signals and output control signals.

[0018] Furthermore, the charge pump includes a filter circuit and a multi-stage boost circuit;

[0019] The filter circuit consists of an on-chip capacitor and an on-chip inductor;

[0020] The first boost circuit includes a second on-chip capacitor C2; one end of the second on-chip capacitor C2 is connected to the first on-chip inductor, and the other end is connected to the cathode of the first on-chip diode D1 and the anode of the second on-chip diode D2; the cathode of the first on-chip diode D1 is connected to the anode of the second on-chip diode D2, and the cathode of the second on-chip diode D2 is connected to the third on-chip capacitor C3; by continuously switching between the first on-chip diode D1 and the second on-chip diode D2, charge is continuously stacked onto the third on-chip capacitor C3, and energy is stored in the third on-chip capacitor C3;

[0021] The capacitor C3 on the third chip is connected to the positive terminal of the diode D3 on the third chip, and the negative terminal of the diode D3 on the third chip is connected to the capacitor C4 on the fourth chip and the diode D4 on the fourth chip in the second boost circuit. This allows the charge stored in the capacitor C3 on the third chip in the first boost circuit to be transferred to the second boost circuit. And so on, so that the reference voltage of the radio frequency signal continuously increases.

[0022] Furthermore, the comparator includes a first on-chip resistor R1, one end of which is connected to a charge pump, and the other end outputs a boosted RF signal to a voltage rectifier; the other end of the first on-chip resistor R1 is divided into two branches, the first branch passing through a second on-chip resistor R2 connected in parallel and an on-chip capacitor C. N+2 The first branch is input to the negative terminal of voltage comparator P1, and the second branch is input to the positive terminal of voltage comparator P1.

[0023] The output of voltage comparator P1 is used to convert the boosted radio frequency signal into a digital signal.

[0024] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention proposes a smart antenna array structure based on integrated power supply, control, and communication, comprising: a radio frequency power divider network; the radio frequency power divider network divides the radio frequency signal into multiple paths, feeding each path of the radio frequency signal into a coupler, and the coupler further divides the radio frequency signal according to the coupling coefficient; the output of the coupler outputs a first radio frequency signal, which is fed into the antenna link; the coupling end of the coupler outputs a second radio frequency signal, which is fed into the passive on-chip system. In terms of power supply, the rectified radio frequency signal powers the low-power antenna link; in terms of control, a networked control of the radio frequency unit is used using a communication protocol to complete functions such as beam control and beamforming; in terms of communication, a communication protocol and integrated communication sensing are implemented. This antenna array solves the pain points of complex network structures and high deployment costs associated with traditional antenna arrays, requiring only the design of the overall radio frequency communication network, eliminating the need for additional power supply and control networks. Secondly, the overall structure of the antenna array is universal and versatile within the existing radio frequency communication protocol framework. For different radio frequency communication protocols, the designer can select appropriate specific implementation methods according to the present invention, so that the communication protocol of the radio frequency unit inside the antenna array is the same as the communication protocol used by the external transponder. Users can easily control the antenna array and realize many integrated communication and sensing applications. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a block diagram of the overall design structure of the smart antenna array provided in the embodiments of the present invention;

[0027] Figure 2 This is a block diagram of the internal structure of the passive on-chip system designed in this invention;

[0028] Figure 3 This is a circuit schematic diagram of the smart antenna array provided in an embodiment of the present invention. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms “a,” “the,” and “the” used in this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this invention to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of this invention, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0032] The present invention will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0033] like Figure 1 As shown, the present invention provides a smart antenna array structure based on integrated power supply, control, and communication, comprising: a radio frequency power divider network, which divides the radio frequency signal into multiple paths, feeds each path of the radio frequency signal into a coupler, and the coupler further divides the radio frequency signal according to the coupling coefficient; the output end of the coupler outputs a first radio frequency signal and feeds it into the antenna link; the coupling end of the coupler outputs a second radio frequency signal and feeds it into the passive on-chip system.

[0034] Specifically, the RF signal is input to an RF power divider network, which feeds the signal into multiple paths, allowing subsequent antenna links to work collaboratively. The divided RF signal is then fed into a coupler, which further divides the signal based on its coupling coefficient. Most of the power from the output branch of the coupler at its output (OUT) is fed into the antenna links; a small portion of the power from the output branch at its coupling (COUPLE) is fed into the on-chip system. This design meets the low-power requirements of the on-chip system while keeping the antenna links largely unaffected. Under this RF power divider design, the antenna links can still maintain long-distance communication with external transponders.

[0035] It should be noted that the coupler distributes power, with a smaller portion of the RF signal allocated to the passive on-chip, while the majority of the RF signal is still fed into the antenna link. This is primarily because the passive on-chip is low-power; the RF power splitting design described above ensures that the original antenna link is almost unaffected, while successfully establishing communication between the passive on-chip and the RF transceiver. The transceiver can then power and control the antenna link through the passive on-chip.

[0036] Furthermore, the RF power divider network, couplers, antenna links, and passive system-on-chip are all connected via coplanar waveguides characterized by straight lines. In this example, the impedance matching of the coplanar waveguides can be designed according to the frequency band operated by the selected RF communication protocol. By adjusting the width and distance of the coplanar waveguides to ground, the coplanar waveguides can meet a characteristic impedance of 50 ohms on the selected material board.

[0037] The passive system-on-chip (SoC) boosts and rectifies the radio frequency (RF) signal to output a stable DC voltage VDD, which powers the adjustable RF module. Simultaneously, it analyzes the received RF signal and outputs a digital control signal VCTL to control the adjustable RF module. Since the passive SoC and the external transponder use the same RF communication protocol, the RF transceiver can communicate with the external transponder using the antenna array while simultaneously sending commands to the passive SoC to control the antenna array.

[0038] The antenna link includes an adjustable RF module and an antenna connected to it. The adjustable RF module includes, but is not limited to, RF switches and phase shifters. RF switches such as the Skyworks SKY13286-359LF can be selected, and phase shifters such as the Mini-Circuits SPHSA-152+ can be selected. The adjustable RF module changes the amplitude and phase of the RF signal in its antenna link, resulting in α. i Amplitude gain change and Phase change.

[0039] The antenna can be a patch antenna. The antenna transmits or receives radio frequency signals in the link into free space. By controlling the adjustable radio frequency module, the antenna can be used to achieve electromagnetic wave beam control and beamforming.

[0040] like Figure 2 As shown, the passive system-on-chip has complete functions for communicating with an RF transceiver and outputting DC voltage and control signals to external devices. The passive system-on-chip includes:

[0041] The radio frequency (RF) front end is used to receive radio frequency signals and return response signals.

[0042] A charge pump, one end of which is connected to an RF front-end, includes a multi-stage boost circuit for increasing the reference voltage of the RF signal;

[0043] A comparator, connected to the other end of a charge pump, is used to convert the boosted radio frequency signal into a digital signal.

[0044] A voltage rectifier, connected to the output of the comparator, rectifies the boosted radio frequency signal and outputs a first DC voltage VCORE and a second DC voltage VREGL; wherein, the first DC voltage VCORE is used to power the digital processor, and the second DC voltage VREGL is used to power external devices.

[0045] A digital processor is used to process the parsed digital signals and output control signals.

[0046] Furthermore, the charge pump includes a filter circuit and a multi-stage boost circuit;

[0047] The filtering circuit consists of an on-chip capacitor and an on-chip inductor, and is used to filter out noise signals.

[0048] The multi-stage boost circuit consists of N on-chip capacitors C2, C3, ..., C N+1 and N on-chip diodes D1, D2, ..., D N The composition is illustrated in this example using the first boost circuit as an example;

[0049] The first boost circuit includes a second on-chip capacitor C2; one end of the second on-chip capacitor C2 is connected to the first on-chip inductor, and the other end is connected to the cathode of the first on-chip diode D1 and the anode of the second on-chip diode D2; the cathode of the first on-chip diode D1 is connected to the anode of the second on-chip diode D2, and the cathode of the second on-chip diode D2 is connected to the third on-chip capacitor C3; under the action of the radio frequency signal, the first on-chip diode D1 and the second on-chip diode D2 are continuously switched, and the charge is continuously stacked onto the third on-chip capacitor C3, where energy is stored.

[0050] The capacitor C3 on the third chip is connected to the positive terminal of the diode D3 on the third chip, and the negative terminal of the diode D3 on the third chip is connected to the capacitor C4 on the fourth chip and the diode D4 on the fourth chip in the second boost circuit. This allows the charge stored on the capacitor C3 on the third chip in the first boost circuit to be transferred to the second boost circuit. And so on, so that the reference voltage of the radio frequency signal is continuously increased, achieving the effect of voltage multiplication.

[0051] Furthermore, the comparator includes a first on-chip resistor R1, one end of which is connected to a charge pump, and the other end outputs a boosted RF signal to a voltage rectifier; the other end of the first on-chip resistor R1 is divided into two branches, the first branch passing through a second on-chip resistor R2 connected in parallel and an on-chip capacitor C. N+2 The first branch is input to the negative terminal of voltage comparator P1, and the second branch is input to the positive terminal of voltage comparator P1; the output of voltage comparator P1 is used to convert the boosted RF signal into a digital signal.

[0052] Furthermore, the digital processor processes the parsed digital signal and outputs control signals on five GPIO ports (GPIO0, ..., GPIO5).

[0053] It should be noted that the passive system-on-chip (SoC) receives radio frequency (RF) signals and returns response signals via an RF front-end. A charge pump boosts the reference voltage of the RF signal, and a rectifier rectifies the boosted signal, ultimately outputting a stable DC voltage. Therefore, this invention can directly utilize the passive SoC as a stable DC voltage source to power the low-power RF unit in the antenna link. Thus, this invention eliminates the need for an additional power supply network. The digital processor module in the passive SoC processes the digital signal parsed from the RF signal and sends control commands to the RF unit via the control signal output port of the passive SoC. Since the passive SoC uses an integrated communication protocol with the external transponder, the passive SoC enables direct control of the RF unit using an RF transceiver, eliminating the need for an additional control network and facilitating antenna array control, subsequent beamforming, and beamforming.

[0054] like Figure 3 As shown, the present invention provides a circuit implementation of the proposed integrated antenna array structure. Figure 3 The circuit schematic for only one antenna branch is shown; the structures of the other antenna array branches are similar. A1 represents the RF signal input terminal for this branch. The RF signal first passes through coupler X1, is fed into the on-chip system link at the coupler's COUPLED port, and is fed into the antenna link at the coupler's OUTPUT port. The on-chip system link first includes an RF balun transformer. After the balun transformer, a matching circuit containing inductors L1 and L2 connects to the on-chip SoC. The adjustable RF module U11 for the antenna link uses an RF switch, and after the RF switch, the link connects to the patch antenna port RF9.

[0055] Example 1

[0056] This embodiment constructs an antenna array within a commercial RFID system, operating under the EPC C1G2 communication protocol. An Impinj R700 reader / writer is selected as the RF transceiver. This embodiment is implemented on a double-layer printed circuit board, using patch antennas to form the overall antenna array. The printed circuit board comprises two copper foil layers, a top layer and a bottom layer, with an F4B substrate between them. Since the selected RF transceiver operates in the UHF band, this embodiment employs a coplanar waveguide impedance matching design for the UHF band. A one-to-four power divider network is designed, resulting in a total of four on-chip systems and four patch antennas in the system. Users send commands to the on-chip systems via the R700 reader / writer. Each on-chip system is distinguished and individually controlled using a unique identifier (EPC) under the EPC C1G2 protocol. The on-chip systems communicate with the reader / writer via backscattered signals. In response to the reader's commands, the on-chip systems send control signals to the RF switches and phase shifters, thereby achieving beamforming and beam control. External transponders (i.e., tags in the RFID system) also use the EPCC1G2 protocol for communication. Users can use this embodiment to communicate normally with the transponders and control the antenna array through the integrated communication protocol to realize many integrated communication and sensing applications.

[0057] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only.

[0058] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A smart antenna array structure integrating power supply, control, and communication, characterized in that, include: One radio frequency power divider network; The radio frequency power divider network divides the radio frequency signal into multiple paths, feeds each radio frequency signal into a coupler, and the coupler further divides the radio frequency signal according to the coupling coefficient; the output of the coupler outputs a first radio frequency signal, which is fed into the antenna link; the coupling end of the coupler outputs a second radio frequency signal, which is fed into the passive on-chip system. The RF power divider network, coupler, antenna link, and passive system-on-chip are all connected via coplanar waveguides. The passive system-on-chip is used to boost and rectify the RF signal, outputting a DC voltage VDD to power the adjustable RF module. Simultaneously, the passive system-on-chip analyzes the RF signal and outputs a digital control signal VCTL to control the adjustable RF module.

2. The intelligent antenna array structure based on the integration of power supply, control, and communication as described in claim 1, characterized in that, The antenna link includes an adjustable radio frequency module and an antenna connected thereto.

3. The intelligent antenna array structure based on integrated power supply, control, and communication as described in claim 2, characterized in that, The passive on-chip system uses the same radio frequency communication protocol as the external transponder. While the antenna array is communicating with the external transponder, the radio frequency transceiver can also send commands to the passive on-chip system to control the antenna array.

4. The intelligent antenna array structure based on integrated power supply, control, and communication as described in claim 2, characterized in that, The adjustable radio frequency module employs a radio frequency switch or a phase shifter; the adjustable radio frequency module changes the amplitude and phase of the radio frequency signal in the antenna link it is connected to, thereby achieving amplitude gain variation and phase variation.

5. A smart antenna array structure based on integrated power supply, control, and communication as described in claim 2, characterized in that, The antenna is a patch antenna; the antenna transmits or receives radio frequency signals in the antenna link into free space, and the antenna is controlled by an adjustable radio frequency module to achieve electromagnetic wave beam control and beamforming.

6. The intelligent antenna array structure based on the integration of power supply, control, and communication as described in claim 1, characterized in that, The passive system-on-chip includes: a radio frequency (RF) front-end for receiving RF signals and returning response signals; a charge pump, one end of which is connected to the RF front-end and includes a multi-stage boost circuit for increasing the reference voltage of the RF signal; a comparator, the other end of which is connected to the charge pump for converting the boosted RF signal into a digital signal; a voltage rectifier, connected to the output of the comparator, for rectifying the boosted RF signal and outputting a first DC voltage VCORE and a second DC voltage VREGL; wherein the first DC voltage VCORE is used to power the digital processor, and the second DC voltage VREGL is used to power external devices; and a digital processor for processing the converted digital signal and outputting control signals.

7. A smart antenna array structure based on integrated power supply, control, and communication as described in claim 6, characterized in that, The charge pump includes a filter circuit and a multi-stage boost circuit. The filter circuit consists of a first on-chip capacitor and a first on-chip inductor. The first boost circuit includes a second on-chip capacitor C2. One end of the second on-chip capacitor C2 is connected to the first on-chip inductor, and the other end is connected to the cathode of the first on-chip diode D1 and the anode of the second on-chip diode D2. The cathode of the first on-chip diode D1 is connected to the anode of the second on-chip diode D2, and the cathode of the second on-chip diode D2 is connected to a third on-chip capacitor C3. By continuously switching between the first on-chip diode D1 and the second on-chip diode D2, charge is continuously stacked onto the third on-chip capacitor C3, where energy is stored. The third on-chip capacitor C3 is connected to the anode of the third on-chip diode D3, and the cathode of the third on-chip diode D3 is connected to the fourth on-chip capacitor C4 and the fourth on-chip diode D4 in the second boost circuit, so that the charge stored on the third on-chip capacitor C3 in the first boost circuit is transferred to the second boost circuit. This process continues, causing the reference voltage of the radio frequency signal to continuously increase.

8. A smart antenna array structure based on integrated power supply, control, and communication as described in claim 6, characterized in that, The comparator comprises a first on-chip resistor R1, one end of which is connected with the charge pump and the other end outputs the boosted radio frequency signal to the voltage rectifier; the other end of the first on-chip resistor R1 is divided into two branches, the first branch passes through the parallel connection of a second on-chip resistor R2 and an on-chip capacitor C N+2 The negative electrode of the voltage comparator P1 is input with the first branch and the positive electrode of the voltage comparator P1 is input with the second branch; the output end of the voltage comparator P1 is used for analyzing the boosted radio frequency signal into a digital signal.

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