Quantum measurement and control system extension high-precision trigger distribution device and method

Abstract

The application discloses a quantum measurement and control system extension high-precision trigger distribution device and method, relates to the field of trigger distribution devices, and comprises a trigger delay unit and an FPGA unit. The output end of the FPGA unit is connected with the input end of the trigger delay unit. The trigger delay unit comprises a single-end trigger output circuit with 10 channels and a differential trigger output circuit with 48 channels. The single-end trigger output circuit receives signals sent by the FPGA, and performs signal delay through a delay adjustment chip. The differential trigger output circuit performs signal delay through an Odelay module of the HPBANK of the FPGA. The application has the advantages that the single-end delay output with 10 channels and the differential trigger output with 48 channels are realized through the multi-channel single-end and differential individually adjustable delay, and a synchronous time sequence generator with the precision as low as 10ps is supported, which can realize one-way external single-end trigger input and six-way external LVDS differential input.

Description

Technical Field

[0001] This invention relates to the field of triggering and distributing devices, specifically to a high-precision triggering and distributing device and method for quantum measurement and control systems. Background Technology

[0002] With the diversification of demands for electronic products and equipment in society, the independent operation of single functional modules is often insufficient to meet high usage requirements. Instead, various modules with different functions work collaboratively to achieve the required functions. Therefore, maintaining the timing synchronization of each module can enable the equipment to achieve higher performance. The quantum measurement and control system's extended high-precision trigger distribution device is a synchronization device that can generate multi-channel synchronization signals to maintain the consistency and synchronization of the timing of each device.

[0003] Timing generators are used to delay external trigger signals as needed, or to generate multiple timing pulse signals themselves. Depending on the delay accuracy and application requirements, they can be divided into various types such as microsecond, nanosecond, and picosecond timing generators, and are widely used in fields such as lasers, nuclear fusion, radar, biomedical engineering, high-speed imaging, mass spectrometry instruments, and spectrometers.

[0004] In the quantum realm, controllers for multi-qubit quantum computing are crucial. Triggering devices provide low-latency, real-time communication chains specifically designed for quantum computing, enabling the routine implementation of rapid, automated qubit calibration. They have wide applications in quantum computing, quantum simulation (neutral atom traps), quantum error correction, and active qubit reset.

[0005] The existing technical solutions in the market are:

[0006] Option 1: The Zurich Instruments PQSC has 18 ZSync interfaces for connecting Zurich Instruments' SHFSG or HDAWG and SHFQA, used for qubit control and readout respectively. The UHFQAZSync interface provides a bidirectional data transfer interface, which can send qubit readout results to the PQSC for centralized processing, or send trigger signals to control lower-level instruments to make synchronous responses.

[0007] Option 2: Dedicated pulse generator equipment, such as the DG645. The DG645 eight-channel digital delay pulse generator uses high-precision circuitry to generate TTL amplitude pulses and digitally controls their delay time for output. It provides four independent pulse outputs, with up to eight delay outputs optional.

[0008] Regarding the drawbacks of the existing solutions mentioned above: Zurich Instruments PQSC suffers from low delay accuracy and limited channels. Dedicated pulse generators such as the DG645 are expensive, difficult to integrate, and also have limited channels. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and, in response to the above problems, to propose a quantum measurement and control system extended high-precision triggering and distribution device and method, so as to achieve independent and adjustable multi-channel delay, small size, easy integration, and high-precision delay adjustment.

[0010] The quantum measurement and control system includes an extended high-precision trigger distribution device, comprising a trigger delay unit and an FPGA unit. The output of the FPGA unit is connected to the input of the trigger delay unit.

[0011] The trigger delay unit includes a 10-channel single-ended trigger output circuit and a 48-channel differential trigger output circuit.

[0012] The single-ended trigger output circuit receives a signal from the FPGA and delays the signal via a delay adjustment chip; the differential trigger output circuit delays the signal via the ODELAY module of the FPGA's HPBANK.

[0013] The FPGA unit includes one external host computer control network communication port, one serial communication port, one external single-ended trigger input, six external LVDS differential inputs, and one external clock signal input. Specifically, in terms of hardware, for the ten 3.3V standard trigger output signals, each channel is generated by the FPGA (1.8V standard), passes through a delay adjustment circuit, a differential-to-single-ended circuit, and a level conversion circuit, before outputting a 3.3V standard trigger output signal. For the 48 LVDS level differential trigger output signals, the FPGA outputs differential signals from a 1.8V bank. In terms of software, the host computer sends commands to the control board via network port or USB serial port, and the control board then controls the FPGA to output differential signals, which pass through a delay adjustment circuit, a differential-to-single-ended circuit, and a level conversion circuit, or are output directly. Therefore, this board has ten independent trigger output signals and 48 pairs of independent differential signals. For single-ended output signals, the signal is generated by the FPGA and passes through the delay adjustment chip NB6L295. The incremental resolution of the digital selectable delay of this chip is usually 11 ps, which realizes the signal delay function. For differential output, the signal is output by the ODELAY module of the FPGA HPBANK (delay step is 78ps), which realizes the signal delay function.

[0014] Furthermore, the differential trigger output circuit is connected to an RJ45 connector, the input of which is connected to 48 differential trigger outputs, and the output of which is connected to 5 external LVDS differential inputs; the single-ended trigger output circuit is connected to an SMA connector, and the input of which is connected to a single-delay output through level conversion.

[0015] Furthermore, the FPGA unit is connected to the host computer via an external host computer control network port or serial port. The host computer sends instructions to the FPGA unit through the network port or serial port. The FPGA unit outputs a differential signal according to the instructions. After passing through a delay adjustment chip and a differential-to-single-ended circuit, the signal is output by a level conversion circuit or directly.

[0016] Furthermore, the signal delay of the single-ended trigger output circuit is: a logic integer cycle delay of 10ns + an NB6L295 parameter delay of 11ps; the signal delay of the differential trigger output circuit is: a logic integer cycle delay of 10ns + an ODELAY parameter delay of 78ps.

[0017] Furthermore, the delay adjustment chip is NB6L295MNG. The delay adjustment chip is controlled by SPI to send different delay parameters. The output of the delay adjustment chip includes two channels, and the two outputs are respectively connected to two comparators. The delay adjustment chip is connected to the BUFFER through the two comparators. The signal of the BUFFER is output through the SMA connector.

[0018] Furthermore, the comparator is model LMV7219M5, the comparator is powered by 3.3V, and the comparator converts the LVPECL signal into a 0-3.3V pulse signal.

[0019] Furthermore, the BUFFER model is SN74AVC2T245RSWR, and a transistor circuit is connected to the enable pin of the BUFFER.

[0020] A method for extending high-precision triggering and distribution in a quantum measurement and control system, based on the aforementioned device for extending high-precision triggering and distribution in a quantum measurement and control system, includes the following steps:

[0021] S1. The host computer sends commands to the control board via the network port or serial port, and the control board controls the FPGA unit to output differential signals;

[0022] S2. The host computer sends the delay adjustment parameters to the control board. For the 10 trigger output signals with a standard 3.3V level, the signals are output through the FPGA unit. The signals are delayed by the delay adjustment chip according to the delay adjustment parameters, and a single-ended trigger output signal with a standard 3.3V level is output.

[0023] S3. The host computer sends the delay adjustment parameters to the control board. For the 48-channel LVDS level differential trigger output signals, the signal delay is performed by the HPBANK ODELAY module of the FPGA unit, and the differential trigger output signal is output.

[0024] The signal delay of the single-ended trigger output circuit is: 10ns logic cycle delay + 11ps NB6L295 parameter delay; the signal delay of the differential trigger output circuit is: 10ns logic cycle delay + 78ps ODELAY parameter delay.

[0025] Furthermore, the delay adjustment chip is controlled by SPI to send different delay parameters. The output of the delay adjustment chip includes two channels, which are respectively connected to two comparators. The delay adjustment chip is connected to the BUFFER through the two comparators, and the signal of the BUFFER is output through the SMA connector.

[0026] The beneficial effects of this invention are:

[0027] This invention provides a synchronous timing generator with adjustable single-ended and differential delays via multiple channels, featuring 10 channels of single-ended delay output and 48 channels of differential trigger output. It also supports one external single-ended trigger input and six external LVDS differential inputs with a precision as low as 10 ps. Attached Figure Description

[0028] Figure 1 A system structure block diagram of the quantum measurement and control system extended high-precision triggering and distribution device provided in the embodiments of the present invention;

[0029] Figure 2 The FPGA-side delay circuit implementation diagram of the quantum measurement and control system extended high-precision trigger distribution device provided in the embodiment of the present invention is shown.

[0030] Figure 3 A schematic diagram of the NB6L295 connection circuit for the quantum measurement and control system extended high-precision triggering and distribution device provided in this embodiment of the invention;

[0031] Figure 4 The comparator and BUFFER output circuit of the quantum measurement and control system extended high-precision triggering and distribution device provided in the embodiments of the present invention;

[0032] Figure 5 The implementation diagram of the BANK33 delay circuit on the FPGA side of the quantum measurement and control system extended high-precision trigger distribution device provided in the embodiment of the present invention;

[0033] Figure 6 The implementation diagram of the BANK34 delay circuit on the FPGA side of the quantum measurement and control system extended high-precision trigger distribution device provided in the embodiment of the present invention;

[0034] Figure 7 The diagram shows the implementation of the BANK35 delay circuit on the FPGA side of the quantum measurement and control system's extended high-precision triggering and distribution device, as provided in the embodiments of the present invention. Detailed Implementation

[0035] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention; that is, the described embodiments are only a part of the embodiments of the invention, and not all of them. The components of the embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention. It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0038] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0040] like Figure 1 As shown, the quantum measurement and control system extends a high-precision trigger distribution device, including a trigger delay unit and an FPGA unit. The output of the FPGA unit is connected to the input of the trigger delay unit, wherein:

[0041] The trigger delay unit includes a 10-channel single-ended trigger output circuit and a 48-channel differential trigger output circuit.

[0042] The single-ended trigger output circuit receives a signal from the FPGA and delays the signal via a delay adjustment chip; the differential trigger output circuit delays the signal via the ODELAY module of the FPGA's HPBANK.

[0043] The FPGA unit includes one external host computer control network port input, one external single-ended trigger input, six external LVDS differential inputs, and one external clock signal input. Specifically, the trigger chassis has 10 trigger output signals with a 3.3V standard level and 48 differential trigger output signals with LVDS level. On the hardware side, for the 10 trigger output signals with a 3.3V standard level, each channel is generated by the FPGA (1.8V standard level), passes through a delay adjustment circuit, a differential-to-single-ended circuit, and a level conversion circuit, and then outputs a 3.3V standard trigger output signal. For the 48 differential trigger output signals with LVDS level, the FPGA outputs differential signals from a 1.8V bank. On the software side, the host computer sends commands to the control board via the network port or USB serial port, and the control board then controls the FPGA to output differential signals, which pass through a delay adjustment circuit, a differential-to-single-ended circuit, and a level conversion circuit, or are output directly. Therefore, this board has 10 independent trigger output signals and 48 pairs of independent differential signals. For single-ended output signals, the signal is generated by the FPGA and passes through the delay adjustment chip NB6L295. The incremental resolution of the digital selectable delay of this chip is usually 11 ps, which realizes the signal delay function. For differential output, the signal is output by the ODELAY module of the FPGA HPBANK (delay step is 78ps), which realizes the signal delay function.

[0044] Furthermore, the differential trigger output circuit is connected to an RJ45 connector, the input of which is connected to 48 differential trigger outputs, and the output of which is connected to 5 external LVDS differential inputs; the single-ended trigger output circuit is connected to an SMA connector, and the input of which is connected to a single-delay output through level conversion.

[0045] Furthermore, the FPGA unit is connected to the host computer via an external host computer control network port or serial port. The host computer sends instructions to the FPGA unit through the network port or serial port. The FPGA unit outputs a differential signal according to the instructions. After passing through a delay adjustment chip and a differential-to-single-ended circuit, the signal is output by a level conversion circuit or directly.

[0046] Furthermore, the signal delay of the single-ended trigger output circuit is: a logic integer cycle delay of 10ns + an NB6L295 parameter delay of 11ps; the signal delay of the differential trigger output circuit is: a logic integer cycle delay of 10ns + an ODELAY parameter delay of 78ps.

[0047] Furthermore, as a preferred embodiment, a detailed delay circuit design for single-ended triggering is proposed. Specifically, it uses the HR bank of the XC7Z045FFG900, and the schematic diagram is as follows. Figure 2 As shown. The delay chip used is the NB6L295MNG, which is controlled via SPI to send different delay parameters. The incremental resolution of the digitally selectable delay of this chip is typically 11 ps. The principle is as follows. Figure 3 As shown in the diagram. The comparator selected is LMV7219M5, which provides a 3.3V power supply and converts the LVPECL signal into a 0-3.3V pulse signal. The buffer selected is SN74AVC2T245RSWR, which can provide interface protection. A transistor circuit is added to the enable pin of this chip to prevent the timing generator from generating power-on and power-off overshoot. Finally, the signal is output as an SMA signal. The schematic diagram is shown below. Figure 4 As shown.

[0048] Furthermore, as a preferred embodiment of this practice, a detailed delay circuit design scheme for differential triggering is proposed, specifically, as follows: Figure 5 , 6 7. BANK33, 34, and 35 of the Z7045 are HPBANKs that support outputting ODELAY delay. Differential triggering outputs from these three BANKs can achieve delay adjustment.

[0049] Furthermore, the delay adjustment chip is NB6L295MNG. The delay adjustment chip is controlled by SPI to send different delay parameters. The output of the delay adjustment chip includes two channels, and the two outputs are respectively connected to two comparators. The delay adjustment chip is connected to the BUFFER through the two comparators. The signal of the BUFFER is output through the SMA connector.

[0050] Furthermore, the comparator is model LMV7219M5, the comparator is powered by 3.3V, and the comparator converts the LVPECL signal into a 0-3.3V pulse signal.

[0051] Furthermore, the BUFFER model is SN74AVC2T245RSWR, and a transistor circuit is connected to the enable pin of the BUFFER.

[0052] A method for extending high-precision triggering and distribution in a quantum measurement and control system, based on the aforementioned device for extending high-precision triggering and distribution in a quantum measurement and control system, includes the following steps:

[0053] S1. The host computer sends commands to the control board via Ethernet or serial port, and the control board controls the FPGA unit to output differential signals; specifically, the host computer sends commands to the control board via Ethernet connection. These commands may include configuration and settings for the FPGA unit to generate the required differential signals. The control board acts as an intermediary, converting the received commands into appropriate control signals to control the FPGA unit.

[0054] An FPGA (Field-Programmable Gate Array) is a reconfigurable digital circuit that can be programmed to perform various tasks. In this case, it is set to generate the required differential signals based on instructions received from a control board. Differential signals typically consist of two complementary signals, one of which is the inverse of the other. Such signals are commonly used for high-speed data transmission and interference immunity.

[0055] S2. The host computer sends the delay adjustment parameters to the control board. For the 10 trigger output signals with a standard 3.3V level, the signals are output through the FPGA unit. The signals are delayed by the delay adjustment chip according to the delay adjustment parameters, and a single-ended trigger output signal with a standard 3.3V level is output.

[0056] S3. The host computer sends delay adjustment parameters to the control board. For the 48-channel LVDS level differential trigger output signals, the ODELAY module of the HPBANK in the FPGA unit performs signal delay and outputs differential trigger output signals. Specifically, in this step, the host computer sends the delay adjustment parameters to the control board again. However, this time the control board processes the 48-channel LVDS (low-voltage differential signal) differential trigger output signals.

[0057] The FPGA unit is equipped with an HPBANK, or high-performance module. Within this HPBANK is an ODELAY (output delay) module. The ODELAY module is specifically designed to introduce delay into the output signals. When the control board receives delay adjustment parameters from the host computer, it configures the ODELAY module for each of the 48 LVDS signals. The ODELAY module introduces a specific delay amount based on the provided parameters, thereby achieving precise control over signal timing. After adjustment by the ODELAY module, the FPGA outputs 48 differential trigger signals. These signals are used in applications requiring precise synchronization and timing control, typically in high-speed data transmission and communication systems. The LVDS signal standard was chosen because of its high immunity to interference and its ability to maintain signal integrity while transmitting data over relatively long distances.

[0058] The signal delay of the single-ended trigger output circuit is: a logic integer cycle delay of 10ns + an NB6L295 parameter delay of 11ps; the signal delay of the differential trigger output circuit is: a logic integer cycle delay of 10ns + an ODELAY parameter delay of 78ps. Specifically, the delay processes are as follows:

[0059] The delay principle and flow of a single-ended trigger output circuit:

[0060] The host computer sends instructions and parameters to the delay adjustment chip via the SPI interface to set the required delay amount;

[0061] The delay adjustment chip implements a delay based on received parameters using internal logic circuitry. This may include a counter, delay lines, or other delay units. The delay-adjusted signal exits from the chip's output. One output connects to a comparator to monitor the delay amount, and another output connects to another comparator to monitor the delay amount. The outputs of the two comparators are then connected to two buffers. Each buffer is an amplifier used to enhance the signal's amplitude and quality, ensuring no distortion during transmission. The signal processed by the buffers is then output via an SMA connector. This SMA connector can be connected to other circuits or devices for further signal processing or use.

[0062] The delay principle of the differential trigger output circuit is as follows: The host computer sends commands and parameters to the delay adjustment chip via the SPI interface to set the required delay amount. The delay adjustment chip adjusts the delay amount of the ODELAY module inside the FPGA based on the received parameters. The ODELAY module typically consists of a series of delay units used to implement minute signal delays. The differential signal passes through the FPGA's HPBANK, is processed by the ODELAY module, and the required delay is introduced. The delayed differential signal exits from the FPGA's output. The positive terminal of the differential signal is connected to a comparator to monitor the signal delay amount; the negative terminal of the differential signal is connected to another comparator to monitor the signal delay amount; the output signals of the two comparators are connected to two buffers to amplify and restore the signal strength; the signal processed by the buffers is output through an SMA connector. This SMA connector can be connected to other circuits or devices for further signal processing or use.

[0063] Furthermore, the delay adjustment chip is controlled via SPI to send different delay parameters. The chip has two outputs, each connected to a comparator. These comparators are connected to a buffer, and the buffer's signal is output via an SMA connector. Specifically, the delay adjustment chip is a special integrated circuit whose main function is to adjust the delay of the output signal based on the received SPI control signal. SPI (Serial Peripheral Interface) is a serial peripheral interface protocol that allows a microcontroller or host computer to communicate with external devices. Through the SPI interface, the host computer can send instructions and parameters to the delay adjustment chip to adjust the output signal delay. The host computer sends delay parameters to the delay adjustment chip via the SPI interface. These parameters may include digital values ​​specifying the desired delay amount. Each delay parameter corresponds to a specific delay amount; by adjusting these parameters, different signal delays can be achieved in the delay adjustment chip. The delay adjustment chip's output includes two signals, i.e., differential signal pairs. Each signal is connected to a comparator. A comparator is a circuit used to compare the difference between an input signal and a reference voltage. They are used to monitor the delay of the output signal and compare it to a reference voltage. The outputs of two comparators are connected to two buffers. A buffer is a circuit used to amplify and reconstruct a signal. It can eliminate amplitude loss during signal transmission and ensure signal quality. Since the signal output from the delay adjustment chip may experience some signal attenuation, connecting a buffer strengthens and restores the signal strength. Through an SMA (Sub-Miniature Version A) connector, the amplified signal from the buffer can be output to other circuits or devices. An SMA connector is a commonly used high-frequency signal connector, typically used to connect RF and microwave circuits. Through an SMA connector, the signal output from the delay adjustment chip can be easily connected to the input of other systems for signal transmission and processing.

[0064] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A high-precision triggering and distribution device for a quantum measurement and control system, comprising a trigger delay unit and an FPGA unit, wherein the output of the FPGA unit is connected to the input of the trigger delay unit, characterized in that: The trigger delay unit includes a 10-channel single-ended trigger output circuit and a 48-channel differential trigger output circuit. The single-ended trigger output circuit receives a signal from the FPGA and delays the signal via a delay adjustment chip; the differential trigger output circuit delays the signal via the ODELAY module of the FPGA's HP BANK. The FPGA unit includes one external host computer control network port communication, one serial port communication, one external single-ended trigger input, six external LVDS differential inputs, and one external clock signal input. The delay adjustment chip is NB6L295MNG. The delay adjustment chip is controlled by SPI and sends different delay parameters. The output of the delay adjustment chip includes two channels. The two outputs are respectively connected to two comparators. The delay adjustment chip is connected to BUFFER through the two comparators. The signal of BUFFER is output through SMA connector. The comparator is an LMV7219M5, which is powered by 3.3V and converts the LVPECL signal into a 0-3.3V pulse signal. The BUFFER is model SN74AVC2T245RSWR, and a transistor circuit is connected to the enable pin of the BUFFER.

2. The quantum measurement and control system extended high-precision triggering and distribution device as described in claim 1, characterized in that, The differential trigger output circuit is connected to an RJ45 connector, the input of which is connected to 48 differential trigger outputs, and the output of which is connected to 5 external LVDS differential inputs; the single-ended trigger output circuit is connected to an SMA connector, and the input of which is connected to a single delay output through level conversion.

3. The quantum measurement and control system extended high-precision triggering and distribution device as described in claim 1, characterized in that, The FPGA unit is connected to the host computer via an external host computer control network port or serial port. The host computer sends instructions to the FPGA unit through the network port or serial port. The FPGA unit outputs a differential signal according to the instructions. After passing through a delay adjustment chip and a differential to single-ended circuit, the signal is output by a level conversion circuit or directly.

4. The quantum measurement and control system extended high-precision triggering and distribution device as described in claim 1, characterized in that, The signal delay of the single-ended trigger output circuit is: 10ns logic integer cycle delay + 11ps NB6L295 parameter delay; the signal delay of the differential trigger output circuit is: 10ns logic integer cycle delay + 78ps ODELAY parameter delay.

5. A method for extending high-precision triggering and distribution in a quantum measurement and control system, based on the device for extending high-precision triggering and distribution in a quantum measurement and control system as described in any one of claims 1-4, characterized in that, Includes the following steps: S1. The host computer sends commands to the control board via the network port or serial port, and the control board controls the FPGA unit to output differential signals; S2. The host computer sends the delay adjustment parameters to the control board. For the 10 trigger output signals with a standard 3.3V level, the signals are output through the FPGA unit. The signals are delayed by the delay adjustment chip according to the delay adjustment parameters, and a single-ended trigger output signal with a standard 3.3V level is output. S3. The host computer sends the delay adjustment parameters to the control board. For the 48-channel LVDS level differential trigger output signals, the signal delay is performed by the HP BANK ODELAY module of the FPGA unit, and the differential trigger output signal is output. The signal delay of the single-ended trigger output circuit is: 10ns logic cycle delay + 11ps NB6L295 parameter delay; the signal delay of the differential trigger output circuit is: 10ns logic cycle delay + 78ps ODELAY parameter delay.

6. The quantum measurement and control system extended high-precision triggering and distribution method as described in claim 5, characterized in that, The delay adjustment chip is controlled by SPI to send different delay parameters. The output of the delay adjustment chip includes two channels, which are respectively connected to two comparators. The delay adjustment chip is connected to the BUFFER through the two comparators, and the signal of the BUFFER is output through the SMA connector.

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