Insulated gate bipolar transistor and method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises a substrate, a collector region located on one side of the substrate, at least one doped region located on the side of the substrate away from the collector region, each doped region being in contact with the substrate, and a plurality of doped regions being arranged at intervals, a drift region located on the side of the doped region away from the collector region, the drift region having a third surface away from the doped region, the doping concentration of the doped region being higher than that of the drift region, and at least one super junction penetrating into the drift region along the third surface, and part of the drift region being located between the doped region and the super junction, wherein the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type. By arranging the doped region below the super junction, the current tailing phenomenon in the transistor off process is improved, the off energy loss of the transistor is effectively reduced, and the reliability of the device is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically, to an insulated gate bipolar transistor and a method for manufacturing the same. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field-effect transistor (MOS). It combines the advantages of the high input impedance of a MOSFET and the low on-state voltage drop of a GTR, resulting in low drive power and low saturation voltage drop. It is very suitable for applications in converter systems with DC voltages of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives.

[0003] When an IGBT is turned on, both the emitter and collector regions inject a large number of holes into the drift region, increasing the device's conductivity and reducing conduction losses. However, when the IGBT is turned off, the large number of injected holes prevents the carriers from being eliminated quickly, resulting in a current tail phenomenon and causing significant turn-off energy loss. Summary of the Invention

[0004] The main objective of this invention is to provide an insulated gate bipolar transistor and its fabrication method to solve the problem of high turn-off energy loss in the prior art of IGBTs.

[0005] To achieve the above objectives, according to one aspect of the present invention, an insulated gate bipolar transistor is provided, comprising: a substrate; a collector region located on one side of the substrate, the collector region having opposing first and second surfaces; at least one doped region located on the side of the substrate away from the collector region, each doped region being in contact with the substrate, and a plurality of doped regions being spaced apart; a drift region located on the side of the doped region away from the collector region, the drift region having a third surface away from the doped region, the doping concentration of the doped region being higher than the doping concentration of the drift region; at least one superjunction extending along the third surface into the drift region, a portion of the drift region being located between the doped region and the superjunction, wherein the drift region and the doped region are of a first doping type, and the superjunction and the collector region are of a second doping type.

[0006] Furthermore, the doping concentration of the doped region increases along a first direction, which is the direction from the third surface to the first surface.

[0007] Furthermore, the doped region is located at least partially between the superjunction and the collector region.

[0008] Furthermore, the projection of the doped region onto the first surface coincides with the first surface.

[0009] Furthermore, the superknot extends along the first direction.

[0010] Furthermore, it also includes a second doped region, which is located between the collector region and the doped region, and the second doped region is of a second doping type.

[0011] According to another aspect of the present invention, a method for fabricating an insulated gate bipolar transistor is provided, comprising the following steps: providing a substrate; forming at least one doped region on one side of the substrate; forming a drift region on the side of the doped region away from the substrate, the drift region having a third surface away from the doped region, and the doping concentration of the doped region being higher than the doping concentration of the drift region; forming at least one superjunction in the drift region, the superjunction extending through the third surface into the drift region, a portion of the drift region being located between the doped region and the superjunction; forming a collector region on the side of the substrate away from the drift region, the collector region having opposing first and second surfaces, the doped region being in contact with the substrate, wherein the drift region and the doped region are of a first doping type, and the superjunction and the collector region are of a second doping type.

[0012] Furthermore, the step of forming the doped region includes: forming the doped region on one side of the substrate using a vapor phase epitaxy process.

[0013] Furthermore, the steps for forming a superjunction include: setting a patterned mask on the third surface of the drift region, forming a superjunction in the drift region based on the patterned mask; or forming a patterned mask layer on the third surface of the drift region, forming a superjunction based on the patterned mask layer, and removing the patterned mask layer.

[0014] Furthermore, it also includes: growing an epitaxial layer on the third surface; forming an emitter region in the epitaxial layer, wherein the emitter region has the same doping type as the collector region.

[0015] This invention provides an insulated-gate bipolar transistor (IGBT) comprising a substrate, a collector region, at least one doped region, a drift region, and at least one superjunction. The collector region is located on one side of the substrate and has opposing first and second surfaces. At least one doped region is located on the side of the substrate away from the collector region, each doped region is in contact with the substrate, and multiple doped regions are spaced apart. The drift region is located on the side of the doped region away from the collector region and has a third surface away from the doped region. The doping concentration of the drift region is higher than that of the doped region. The superjunction extends along the third surface into the drift region, with a portion of the drift region located between the doped region and the superjunction. The drift region and the doped region represent a first doping type, while the superjunction and the collector region represent a second doping type. By placing the doped region below the superjunction, the forward conduction voltage of the transistor can be reduced. Furthermore, by placing the doped region in contact with the substrate and on the side of the substrate away from the collector region, the number of holes flowing from the collector region into the drift region is reduced, thereby reducing the minority carrier storage in the drift region, improving current tailing, and ultimately reducing the turn-off energy loss of the IGBT device. Attached Figure Description

[0016] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0017] Figure 1 A schematic diagram of an embodiment of an insulated gate bipolar transistor according to an embodiment of the present invention is shown;

[0018] Figure 2 The diagram shows a cross-sectional view of the substrate after forming the doped region and the drift region in a method for forming an insulated gate bipolar transistor according to an embodiment of the present invention.

[0019] Figure 3 It shows in Figure 2 A schematic cross-sectional view of the substrate after a deep groove is formed in the drift zone;

[0020] Figure 4 It shows in Figure 3 A schematic cross-sectional view of the substrate after a superjunction is formed in the drift region;

[0021] Figure 5 It shows in Figure 4 A schematic cross-sectional view of the substrate after the epitaxial layer is formed on the third surface of the drift region;

[0022] Figure 6 It shows in Figure 5 The diagram shows a cross-sectional view of the substrate after the gate trench is formed in the epitaxial layer.

[0023] Figure 7 It shows in Figure 6 A schematic cross-sectional view of the substrate after the gate oxide layer and gate are formed in the gate trench shown;

[0024] Figure 8 It shows in Figure 7 The diagram shows a cross-sectional view of the substrate after a doped well is formed in the epitaxial layer.

[0025] Figure 9 It shows in Figure 8 The diagram shows a cross-sectional view of the substrate after the emission region is formed in the epitaxial layer.

[0026] Figure 10 It shows in Figure 9 The diagram shows a cross-sectional view of the substrate after the dielectric layer and emitter metal are formed on the side of the epitaxial layer away from the drift region;

[0027] Figure 11 It shows in Figure 10 The diagram shows a cross-sectional view of the substrate after a collector region is formed on the side of the substrate away from the drift region.

[0028] Figure 12 It shows in Figure 11 The diagram shows a cross-sectional view of the substrate after the collector metal is formed on the side of the collector region away from the drift region.

[0029] The above figures include the following reference numerals:

[0030] 1. Substrate; 2. Drift region; 3. Superjunction; 4. Epitaxial layer; 5. Gate oxide layer; 6. Gate; 7. Doped well; 8. Emitter region; 9. Dielectric layer; 10. Emitter metal; 11. Collector region; 12. Collector metal; 13. Doped region; 101. Patterned mask layer; 102. Deep trench; 104. Gate trench. Detailed Implementation

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] As mentioned in the background section, when an IGBT is turned on, the collector region injects a large number of holes into the drift region to increase the device's conductivity and reduce conduction losses. Conversely, when the device is turned off, the large number of holes injected into the drift region cannot be eliminated quickly, resulting in current tailing and causing significant turn-off energy loss in the IGBT.

[0035] To solve the aforementioned technical problems, the inventors of this application have proposed an insulated-gate bipolar transistor, such as... Figure 1 As shown, the device includes a substrate 1, a collector region 11, at least one doped region 13, a drift region 2, and at least one superjunction 3. The collector region 11 is located on one side of the substrate 1 and has opposing first and second surfaces. The doped region 13 is located on the side of the substrate 1 away from the collector region 11 and is in contact with the substrate 1. Multiple doped regions 13 are spaced apart. The drift region 2 is located on the side of the doped region 13 away from the collector region 11 and has a third surface away from the doped region 13. The doping concentration of the doped region 13 is higher than that of the drift region 2. The superjunction 3 extends through the third surface into the drift region 2. A portion of the drift region 2 is located between the doped region 13 and the superjunction 3. The drift region 2 and the doped region 13 are of the first doping type, and the superjunction 3 and the collector region 11 are of the second doping type.

[0036] In the transistor described above, by adding a substrate 1 that is in contact with the collector region 11 to the first surface of the collector region 11, and adding a doped region 13 to the side of the substrate 1 away from the collector region 11, the holes that enter the drift region 2 through the collector region 11 during the device turn-on process can be blocked, thereby reducing the number of holes entering the drift region 2, and thus reducing the minority carrier storage in the hole drift region 2, shortening the duration of the tail current in the device, thereby improving the current tailing phenomenon during the transistor turn-off process, and effectively reducing the turn-off energy loss of the transistor.

[0037] In some optional embodiments, the doping concentration of the doped region 13 is higher than that of the drift region 2. More optionally, the doping concentration of the doped region 13 is one to four orders of magnitude higher than that of the drift region 2. For example, the doping concentration of the doped region 13 is 1 × 10⁻⁶. 20 / cm 3 At that time, the doping concentration of the aforementioned drift region 2 was 1×10⁻⁶. 16 / cm 3 Up to 1×10 19 / cm 3 .

[0038] In some optional embodiments, the doping concentration of the doped region 13 increases along a first direction, wherein the first direction is the direction from the third surface to the first surface, that is, the concentration of the doped region 13 decreases gradually along the direction away from the collector region 11. For example, the average doping concentration of the doped region 13 is 1 × 10⁻⁶. 16 / cm 3 At that time, the doping concentration of the doped region 13 near the collector region 11 is higher than 1×10⁻⁶. 16 / cm 3 The doping concentration of the doped region 13 on the side furthest from the collector region 11 is less than 1×10⁻⁶. 16 / cm 3 By setting the doping concentration gradient of the doped region 13, some holes can be blocked from entering the drift region 2 on the side closer to the collector region 11, thus avoiding the storage of a large number of hole carriers in the drift region 2 and causing current tailing during transistor turn-off. On the other hand, setting the doping concentration on the side farther from the collector region 11 to be relatively low allows holes to enter the drift region 2 from the collector region 11 through the doped region 13, which can improve the transistor's conduction efficiency and reduce the transistor's conduction loss.

[0039] The doped region 13 is at least partially located between the superjunction 3 and the collector region 11. In some optional embodiments, the projection of the doped region 13 onto the first surface of the collector region 11 coincides with the first surface. That is, the doped region 13 can be a continuous doped region that completely covers the first surface of the collector region 11, and the width of the doped region 13 in the vertical first direction is the same as the width of the first surface of the collector region 11. The arrangement of completely coinciding with the first surface of the collector region 11 can block holes entering the drift region 2 from the collector region 11 over a large area, which helps to reduce the number of carriers present in the transistor drift region 2, thereby reducing the tail current and shortening the tail current time, thus improving the current tailing phenomenon during transistor turn-off and effectively reducing transistor turn-off energy loss.

[0040] In some optional embodiments, the doped regions 13 are multiple doped regions spaced apart on the substrate 1. Since the doped regions 13 are highly doped, they can reduce the resistivity of the transistor when the transistor is in the conducting state, thereby reducing the conduction loss of the transistor. Correspondingly, the forward conduction voltage of the transistor will increase. By spaced apart, the forward conduction voltage of the transistor can be reduced, thereby improving the reliability of the transistor device.

[0041] In some alternative implementations, the superjunction extends along a first direction, thereby simultaneously reducing the drain-source on-state resistance, gate capacitance, output charge, and die size of the device, resulting in lower conduction losses.

[0042] In some alternative embodiments, an insulated gate bipolar transistor further includes a second doped region formed by implanting a second doping type into the substrate 1, and the second doped region is located between the collector region and the doped region. The doping concentration of the second doped region is less than the doping concentration of the collector region 11. For example, when the doping concentration of the second doped region is 1 × 10⁻⁶, the doping concentration of the second doped region is 1 × 10⁻⁶. 17 / cm 3 At that time, the doping concentration of the aforementioned collector region 11 can be 1×10⁻⁶. 18 / cm 3 Or 1×10 19 / cm 3 Both the second doped region and the collector region 11 mentioned above are of the second doping type. By forming a second doping type between the collector region and the doped region, the conduction loss of the device can be reduced, thereby improving the reliability of the device.

[0043] In some optional embodiments, the thickness of the doped region 13 can be adjusted according to actual needs. For example, the thickness of the doped region 13 can be 1.5 μm to 3 μm. Since the doping concentration of this doped region is heavily doped, and heavy doping can reduce the conductivity of the device, in this embodiment, by controlling the thickness of the doped region to be 1.5 μm to 3 μm, the conductivity of the device can be guaranteed and the conduction loss of the device can be reduced.

[0044] In some optional embodiments, a portion of the drift region 2 in the transistor is located between the doped region 13 and the superjunction 3. Optionally, the spacing between the doped region 13 and the superjunction 3 is 3 μm to 4 μm. By setting the thickness of the doped region 13 and the spacing between the doped region 13 and the superjunction 3, it is possible to adapt to the transistor requirements of different parameters in different scenarios, thereby improving the matching performance of the transistor device.

[0045] According to another aspect of the present invention, a method for fabricating an insulated gate bipolar transistor is provided. The method includes: providing a substrate; forming at least one doped region on one side of the substrate; forming a drift region on the side of the doped region away from the substrate, the drift region having a third surface away from the doped region, and the doping concentration of the doped region being higher than that of the drift region; forming at least one superjunction in the drift region, the superjunction extending through the third surface into the drift region, a portion of the drift region being located between the doped region and the superjunction; forming a collector region on the side of the substrate away from the drift region, the collector region having opposing first and second surfaces; the doped region being in contact with the substrate; wherein the drift region and the doped region are of a first doping type, and the superjunction and the collector region are of a second doping type.

[0046] First, such as Figure 2 As shown, in some alternative embodiments, a doped region 13 is formed on one side of the substrate 1 using a vapor phase epitaxy process.

[0047] In some alternative embodiments, the substrate 1 is a silicon substrate. Further alternatively, the substrate 1 may be a first doping type or a second doping type. By epitaxially growing different structures on silicon substrates with different doping types, the transistor device can meet various functional requirements.

[0048] The doped region 13 can be generated by vapor phase epitaxy, liquid phase epitaxy, or solid phase epitaxy. Optionally, vapor phase epitaxy is used to react or pyrolyze a highly volatile silicon source with hydrogen at high temperature to deposit a silicon crystal layer on the substrate 1. The silicon source commonly used can be SiH4, SiHCl3, or SiCl4. Vapor phase epitaxy can improve the perfection and high integration of silicon materials, reduce leakage current in memory cells, and thus improve the reliability of the corresponding devices.

[0049] In some optional embodiments, the doping type of the doped region 13 includes phosphorus and arsenic. Further optionally, in order to obtain silicon layers with different electrical properties, dopants can typically be added during the formation of the doped region 13 using the aforementioned vapor phase epitaxy process. That is, different doped layers can be formed using vapor phase doping. For example, dopants such as PCl3, PH3, SbCl3, and AsCl3 can be added during the epitaxial process to form an N-type doped layer, while P-type dopants such as BCl3, BBr3, and B2H6 can be added to the epitaxial growth process to form a P-type doped layer. Furthermore, the amount of dopants used to form the doped layers can be controlled to form doped layers with different resistivities, thereby improving device compatibility.

[0050] In some optional embodiments, the doped region 13 is a plurality of doped regions 13 spaced apart on the substrate 1. Further optionally, the doped region 13 may also be a single doped region 13 in contact with the substrate 1. The doped region 13 can be formed at any position on the substrate 1, and the doped region 13 can be etched to form doped regions 13 of different sizes according to the requirements of matching different devices.

[0051] In some feasible embodiments, the doped region 13 is an off-the-shelf doped sheet, which is formed by bonding the doped sheet to the substrate 1 to form the desired doped region 13 in the corresponding device.

[0052] In some alternative implementations, such as Figure 2 As shown, after forming the doped region 13, an epitaxial growth process is used to form a drift region 2 on the side of the doped region 13 away from the substrate 1. This drift region 2 has a third surface away from the doped region 13. Optionally, chemical vapor deposition or physical vapor deposition can be used to form the drift region 2 via ion implantation. After forming the drift region 2, a deep trench 102 is formed in the drift region 2. This deep trench 102 extends along the direction from the third surface towards the substrate 1. Figure 3 As shown.

[0053] In some alternative embodiments, a patterned mask layer 101 is formed on the third surface of the drift region 2, that is, a hard mask layer is formed on the third surface of the drift region 2, and then a layer of photoresist is deposited on the hard mask layer. Patterning is achieved through exposure and development processes, and then etching is performed to form a pattern in the drift region 2. Figure 3 The deep trench 102 shown is then removed by removing the remaining mask layer. Alternatively, the deep trench 102 is formed by providing a patterned mask layer 101 on the third surface of the drift region 2 and forming the deep trench 102 by etching. Alternatively, a photoresist layer with an opening of a specific size can be formed on the third surface, and the drift region 2 is then etched in the opening of the photoresist layer to form the deep trench 102.

[0054] In some alternative implementations, such as Figure 4 As shown, a superjunction 3 is formed by filling the deep trench 102 with polycrystalline silicon of different doping types than that of the drift region 2.

[0055] In some alternative implementations, such as Figure 5 As shown, an epitaxial layer 4 is formed on the third surface of the drift region 2 by epitaxial growth. The doping type of the epitaxial layer 4 is the same as that of the drift region 2. The doping can be added as a dopant during the epitaxial growth process to form the epitaxial layer 4. Alternatively, the epitaxial layer 4 can be formed by ion implantation after the epitaxial growth of a silicon layer of a certain thickness.

[0056] In some alternative implementations, such as Figure 6 As shown, a hard mask layer and photoresist are deposited on the side of the epitaxial layer 4 away from the drift region 2, and a pattern is formed by photolithography. Then, at least one gate trench 104 is formed by etching. After that, the remaining mask layer is removed. The gate trench 104 can be a plurality of gate trenches 104 spaced apart. Further optionally, a patterned mask layer 101 can be formed on the side of the epitaxial layer 4 away from the drift region 2, and then the gate trench 104 can be formed by etching the epitaxial layer 4. Further optionally, the gate trench 104 can be formed by etching the epitaxial layer 4 using a dry etching method or a wet etching method by depositing a photoresist layer with a specific photoresist opening.

[0057] In some alternative implementations, such as Figure 7 As shown, a gate oxide layer 5 is formed on the inner wall and bottom of the gate trench 104 using chemical vapor deposition or physical vapor deposition. Then, silicon dioxide is grown in the gate trench 104 outside the gate oxide layer 5 to form the gate 6.

[0058] In some alternative implementations, such as Figure 8 As shown, a doped well 7 is formed on the side of the epitaxial layer 4 away from the drift region 2 by ion implantation. The doped well 7 has the opposite doping type to the epitaxial layer 4, that is, the doped well 7 can be obtained by transforming at least a portion of the epitaxial layer 4.

[0059] In some alternative implementations, such as Figure 9 As shown, at least one emitter region 8 is formed on the side of the doped well 7 away from the epitaxial layer 4. The emitter region 8 is disposed around the end of the gate 6 away from the drift region 2. Further optionally, at least one or more emitter regions 8 are formed in the doped well 7 by means of ion implantation and high temperature diffusion, which are spaced around the gate 6. The emitter regions 8 are of the same doping type as the collector region 11.

[0060] In some alternative implementations, such as Figure 10 As shown, at least one dielectric layer 9 is formed on the side of the doped well 7 away from the drift region 2 by setting a mask and performing chemical vapor deposition or physical vapor deposition. The dielectric layer 9 corresponds one-to-one with the gate 6 and completely covers the surface of the gate 6 away from the drift region 2. Then, an emitter metal 10 is formed on the side of the doped well 7 away from the drift region 2. Further optionally, the emitter metal 10 can be formed by evaporation, atomic layer deposition or magnetron sputtering.

[0061] In some alternative implementations, such as Figure 11 As shown, a collector region 11 is formed on the side of the substrate 1 away from the doped region 13 by ion implantation. The collector region 11 has the same doping type as the substrate 1.

[0062] In some alternative implementations, such as Figure 12 As shown, a collector metal 12 is formed on the side of the collector region 11 away from the substrate 1 using methods such as vapor deposition, atomic layer deposition, or magnetron sputtering.

[0063] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0064] This application involves placing a doped region on the side of the substrate away from the collector region. This prevents holes from entering the drift region from the collector region from being blocked by the doped region along their path into the drift region. Since the doping type of this doped region is opposite to that of the collector region, some holes exiting the collector region recombine with ions in the doped region when they reach the drift region. This reduces the number of ions entering the drift region from the collector region, thereby reducing the amount of stored charge in the transistor. This reduces the tail current of the transistor, improves the current tailing phenomenon during transistor turn-off, effectively reduces the turn-off energy loss of the transistor, and greatly improves the reliability of the device.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An insulated-gate bipolar transistor, characterized in that, include: Base; A current collector region is located on one side of the substrate, the current collector region having opposing first and second surfaces; At least one doped region is located on the side of the substrate away from the collector region, each doped region is in contact with the substrate, and the plurality of doped regions are spaced apart; A drift region is located on the side of the doped region away from the collector region, the drift region has a third surface away from the doped region, and the doping concentration of the doped region is higher than that of the drift region; At least one superjunction extends along a third surface into the drift region, a portion of which is located between the doped region and the superjunction, wherein the drift region and the doped region are of a first doping type, and the superjunction and the collector region are of a second doping type.

2. The insulated gate bipolar transistor according to claim 1, characterized in that, The doping concentration of the doped region increases along a first direction, where the first direction is the direction from the third surface to the first surface.

3. The insulated-gate bipolar transistor according to claim 1, characterized in that, The doped region is located at least partially between the superjunction and the collector region.

4. The insulated-gate bipolar transistor according to any one of claims 1 to 3, characterized in that, The projection of the doped region onto the first surface coincides with the first surface.

5. The insulated-gate bipolar transistor according to any one of claims 1 to 3, characterized in that, The superjunction extends along a first direction.

6. The insulated-gate bipolar transistor according to any one of claims 1 to 3, characterized in that, Also includes: The second doped region is located between the current collector region and the doped region, and the second doped region is of a second doping type.

7. A method for fabricating an insulated gate bipolar transistor according to any one of claims 1 to 6, characterized in that, Includes the following steps: Provide a base; At least one doped region is formed on one side of the substrate; A drift region is formed on the side of the doped region away from the substrate, the drift region having a third surface away from the doped region, and the doping concentration of the doped region being higher than that of the drift region; At least one superjunction is formed in the drift region, the superjunction extending through the third surface into the drift region, and a portion of the drift region is located between the doped region and the superjunction; A collector region is formed on the side of the substrate away from the drift region. The collector region has opposing first and second surfaces. The doped region is in contact with the substrate. The drift region and the doped region are of a first doping type, and the superjunction and the collector region are of a second doping type.

8. The method for fabricating an insulated-gate bipolar transistor according to claim 7, characterized in that, The steps for forming the doped region include: The doped region is formed on one side of the substrate using a vapor phase epitaxy process.

9. The method for fabricating an insulated-gate bipolar transistor according to claim 7, characterized in that, The steps for forming the superjunction include: A patterned mask is disposed on the third surface of the drift region, and the superjunction is formed in the drift region based on the patterned mask; or A patterned mask layer is formed on the third surface of the drift region, a superjunction is formed based on the patterned mask layer, and the patterned mask layer is removed.

10. The method for fabricating an insulated-gate bipolar transistor according to claim 9, characterized in that, Also includes: An epitaxial layer is grown on the third surface; An emitter region is formed in the epitaxial layer, and the emitter region has the same doping type as the collector region.

Images