Fault memory locating method, system, device, computer device and storage medium

Abstract

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

Description

Technical Field

[0001] This invention relates to the field of server technology, and specifically to a method, system, device, computer equipment, and storage medium for locating faulty memory. Background Technology

[0002] To meet the ever-increasing performance requirements of servers, high-performance CPUs (Central Processing Units) are used in servers. High-performance CPUs require a large amount of memory, therefore, the probability of memory failure in servers is relatively high.

[0003] Memory failures can take many forms, among which a PMIC (Power Management Integrated Circuit) malfunction is one that can shut down a server, rendering it unusable. Current methods for identifying PMIC-failed memory cannot directly pinpoint the location of the faulty memory. Furthermore, because a PMIC failure causes server shutdown, it's difficult to obtain sufficient information to accurately locate the faulty memory. The server's inability to independently locate and recover the faulty PMIC memory leads to lengthy troubleshooting times, posing a significant challenge to server maintenance.

[0004] Therefore, existing technologies have the problem of not being able to obtain abnormal information that can accurately locate faulty memory, and thus cannot locate faulty PMIC memory. Summary of the Invention

[0005] In view of this, the present invention provides a method, system, device, computer equipment and storage medium for locating faulty memory, so as to solve the problem in the prior art that it is difficult to obtain abnormal information that can accurately locate faulty memory and that PMIC faulty memory cannot be located.

[0006] In a first aspect, the present invention provides a method for locating faulty memory, the method comprising:

[0007] Upon receiving a memory fault signal while the server is powered off, the write protection state of the power management chip register is released.

[0008] Based on memory fault signals, candidate faulty memory can be identified;

[0009] Write a disable command to the power management chip register of the candidate faulty memory. The disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state.

[0010] With the server powered on, obtain log information about candidate faulty memory.

[0011] Based on the log information, the target faulty memory and its slot information are determined from the candidate faulty memory.

[0012] The faulty memory location method provided in this embodiment, when a memory fault signal is received and the server is powered off, releases the write protection state of the power management chip register, facilitating the writing of a disable command to the candidate faulty memory. Based on the memory fault signal, a candidate faulty memory is identified, and a disable command is written to the power management chip register of the candidate faulty memory to prevent the candidate faulty memory from affecting server startup. When the server is powered on, the log information of the candidate faulty memory is obtained, and based on the log information, the target faulty memory and slot information are determined, enabling direct location of the specific memory slot where the target faulty memory exists. This solves the problem of difficulty in obtaining abnormal information sufficient for accurate faulty memory location and the inability to locate PMIC faulty memory.

[0013] In one optional implementation, the target faulty memory and its slot information are determined from the candidate faulty memory based on log information, including:

[0014] Determine if the log information contains a first-type memory error message;

[0015] If a first-type memory error message exists, the candidate faulty memory corresponding to the first-type memory error message is identified as the target faulty memory, and the slot information of the target faulty memory is determined based on the log information.

[0016] In this embodiment, the candidate faulty memory corresponding to the first type of memory error information in the log information is identified as the target faulty memory, and the slot information of the target faulty memory is determined. The method is simple and efficient, and can directly locate the specific memory slot, making it convenient for maintenance personnel to replace the target faulty memory.

[0017] In an optional implementation, after determining the slot information of the target faulty memory based on log information, the method further includes:

[0018] Treat the candidate faulty memory corresponding to the second type of memory error information in the log information as normal memory;

[0019] The candidate faulty memory corresponding to the third type of memory error information in the log information is taken as the faulty memory to be analyzed. The faulty memory to be analyzed is the candidate faulty memory other than the target faulty memory and normal memory.

[0020] In this embodiment, the candidate faulty memory corresponding to the second type of memory error information in the log information is regarded as normal memory, and the candidate faulty memory corresponding to the third type of memory error information is regarded as faulty memory to be analyzed. This enables the present invention to identify multiple types of faulty memory and expands the application scope of the present invention.

[0021] In one optional implementation, de-writing the power management chip registers includes:

[0022] Control the target motherboard to power down via AC;

[0023] After a preset time, the target motherboard is powered on via AC, thus releasing the write-protected state of the power management chip register.

[0024] In this embodiment, the target motherboard is controlled to power down via AC. After a preset time, the target motherboard is controlled to power up via AC, thereby clearing the write protection state of the power management chip register. This facilitates the subsequent writing of a disable command to the power management chip register of the candidate faulty memory, preventing the candidate faulty memory from affecting the normal startup of the server.

[0025] In a second aspect, the present invention provides a fault memory location system, the system comprising: a complex programmable device, a baseboard management controller, a platform path controller, and a central processing unit;

[0026] Complex programmable devices are used to receive memory fault signals and determine whether the server is in a powered-off state;

[0027] The complex programmable device is connected to the baseboard management controller and is used to transmit memory fault signals to the baseboard management controller;

[0028] The baseboard management controller is used to remove the write protection state of the power management chip register and to identify candidate faulty memory based on the memory fault signal.

[0029] The baseboard management controller is connected to the platform path controller and is used to send a first message to the platform path controller, which then forwards it to the central processing unit. The first message is used to identify candidate faulty memory.

[0030] The central processing unit is connected to the memory and is used to write a disable command to the power management chip register of the candidate faulty memory. The candidate faulty memory is contained in the memory, and the disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state.

[0031] The baseboard management controller controls the server to DC power on, putting the server into the power-on state, acquiring the log information of the candidate faulty memory, and determining the target faulty memory and the slot information of the target faulty memory from the candidate faulty memory based on the log information.

[0032] The faulty memory location system provided in this embodiment utilizes the baseboard management controller to remove the write-protection state of the power management chip register, facilitating the writing of disable commands to candidate faulty memory. Based on memory fault signals, the baseboard management controller identifies candidate faulty memory and uses the central processing unit to write disable commands to the power management chip register of the candidate faulty memory, preventing the candidate faulty memory from affecting server boot-up. When the server is booted, the baseboard management controller obtains log information of the candidate faulty memory and, based on the log information, determines the target faulty memory and slot information, directly locating the specific memory slot where the target faulty memory exists. This solves the problem of difficulty in obtaining anomaly information sufficient for accurate faulty memory location and the inability to locate faulty PMIC memory.

[0033] In one alternative implementation, the baseboard management controller is connected to the central processing unit via a first link;

[0034] The baseboard management controller is used to determine whether there are first-type memory error messages in the log information;

[0035] If a first type of memory error message is present in the log information, the baseboard management controller is used to determine the candidate fault memory corresponding to the first type of memory error message as the target fault memory, obtain relevant information of the power management chip register in the target fault memory from the central processing unit through the first link, determine the slot information of the target fault memory according to the log information, and generate alarm information according to the relevant information and slot information.

[0036] The baseboard management controller is used to determine whether there are second-type memory error messages in the log information;

[0037] If a second type of memory error message is present in the log information, the baseboard management controller will treat the candidate faulty memory corresponding to the second type of memory error message as normal memory.

[0038] The baseboard management controller is used to determine whether there are third-type memory error messages in the log information;

[0039] In the event that a third type of memory error message exists in the log information, the baseboard management controller uses the candidate fault memory corresponding to the third type of memory error message in the log information as the fault memory to be analyzed. The fault memory to be analyzed is the candidate fault memory other than the target fault memory and normal memory.

[0040] In this embodiment, the baseboard management controller identifies the candidate faulty memory corresponding to the first type of memory error information in the log information as the target faulty memory, and determines the slot information of the target faulty memory. This method is simple and efficient, directly locating the specific memory slot, facilitating replacement of the target faulty memory by maintenance personnel. The baseboard management controller treats the candidate faulty memory corresponding to the second type of memory error information in the log information as normal memory, and the candidate faulty memory corresponding to the third type of memory error information as the faulty memory to be analyzed. This allows the invention to identify multiple types of faulty memory, expanding its application scope.

[0041] In one alternative implementation, the complex programmable device is connected to the substrate management controller via a second link, and the substrate management controller is connected to the platform path controller via a second link.

[0042] The complex programmable device transmits the memory fault signal to the baseboard management controller via a second link;

[0043] The baseboard management controller sends the first message to the platform path controller via the second link.

[0044] In this embodiment, the complex programmable device transmits a memory fault signal to the baseboard management controller via a second link, enabling the baseboard management controller to identify candidate faulty memories. The baseboard management controller then sends a first message to the platform path controller via the second link, allowing the platform path controller to determine which memories are candidate faulty memories, facilitating subsequent notification to the central processing unit.

[0045] In one alternative implementation, the central processing unit is connected to the memory via a third link;

[0046] The central processing unit writes a disable command to the power management chip register of the candidate faulty memory via the third link.

[0047] In this embodiment, the central processing unit writes a disable command to the power management chip register of the candidate faulty memory through a third link to prevent the candidate faulty memory from affecting the server boot-up.

[0048] Thirdly, the present invention provides a faulty memory location device, the device comprising:

[0049] The deactivation module is used to deactivate the write protection state of the power management chip register when a memory fault signal is received and the server is powered off.

[0050] The first determining module is used to determine candidate faulty memory based on memory fault signals;

[0051] The write module is used to write a disable command to the power management chip register of the candidate faulty memory. The disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state.

[0052] The acquisition module is used to acquire log information of candidate faulty memory when the server enters the boot state;

[0053] The second determination module is used to determine the target faulty memory and the slot information of the target faulty memory from the candidate faulty memory based on the log information.

[0054] Fourthly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the fault memory location method of the first aspect or any corresponding embodiment described above.

[0055] Fifthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the fault memory location method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0056] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram illustrating the relationship between the power management chip's abnormal alarm signal and memory according to an embodiment of the present invention;

[0058] Figure 2 This is a flowchart illustrating a fault memory location method according to an embodiment of the present invention;

[0059] Figure 3 This is a schematic diagram of the structure of a fault memory location system according to an embodiment of the present invention;

[0060] Figure 4 This is a schematic flowchart of a method for determining, locating, and alerting on abnormal PMIC memory according to an embodiment of the present invention.

[0061] Figure 5 This is a structural block diagram of a fault memory location device according to an embodiment of the present invention;

[0062] Figure 6This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Each channel of the Central Processing Unit (CPU) can connect to multiple memory modules. Taking a channel that can connect two memory modules as an example, the four memory modules in each pair of channels share a single power management chip (PMIC) fault alarm signal. Figure 1 As shown, channel A of CPU0 connects to the first memory of CPU0 channel A and the second memory of CPU0 channel A, and channel B of CPU0 connects to the first memory of CPU0 channel B and the second memory of CPU0 channel B. These four memory modules share a single power management chip (PWRGD_FAIL_CPU0_AB) alarm signal, which is sent to the Complex Programmable Logic Device (CPLD). If all four memory modules are functioning correctly, the PMIC alarm signal is high. If any of the four memory modules has a PMIC malfunction, that faulty memory will pull the PMIC alarm signal low. Because the four memory modules share a single PMIC alarm signal, it is impossible to distinguish which memory module has the PMIC malfunction.

[0065] Based on the above, this invention provides a method for locating faulty memory. Without affecting the original functions of the motherboard, the CPLD (Content Management Controller) actively notifies the BMC (Baseboard Management Controller) when it detects a low-level abnormal alarm signal from the power management chip. Simultaneously, the CPLD works with the BMC to identify the faulty memory with a PMIC (Power Management Controller) malfunction and provides the corresponding slot information. This solves the problem of not being able to directly locate the faulty memory slot, thus hindering troubleshooting and server room maintenance.

[0066] According to an embodiment of the present invention, a method for locating faulty memory is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a server device with data processing capabilities. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0067] This embodiment provides a method for locating faulty memory, which can be used in the aforementioned server equipment. Figure 2 This is a flowchart of a fault memory location method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0068] Step S201: When a memory fault signal is received and the server is in a powered-off state, the write protection state of the power management chip register is released.

[0069] Specifically, during normal operation, the BIOS (Basic Input Output System) sends an enable command to the DIMM (Dual-Inline-Memory-Modules), the memory powers on and operates normally, and the BIOS sets the power management chip registers (PMIC registers) of all DIMMs to write-protected mode.

[0070] When the CPLD detects a low level in the power management chip's fault alarm signal (PWRGD_FAIL, or simply PWR_FAIL signal), the server will shut down. Simultaneously, because the DIMM's PMIC register is write-protected, the PMIC fault causing the PWR_FAIL signal to go low cannot be cleared, preventing the server from booting up. Therefore, it is necessary to clear the write protection state of the power management chip's register.

[0071] Taking an example where each CPU channel can connect to two memory modules, after the server is powered on via DC, if the server has two CPUs, under normal server conditions, the two CPUs will have eight memory PWR_FAIL signals, all of which will be high-level. This invention refers to the low-level PWR_FAIL signal as a memory fault signal. After the CPLD receives the memory fault signal in real time, it waits 5 seconds to confirm that the CPLD's timing has reached state S5. This S5 state is a power timing state, specifically a power supply connected to an AC (Alternating Current) power supply with STBY (standby) mode. The S5 state indicates that the server is in a powered-off state.

[0072] The CPLD confirms a PMIC (Power Management Interface) error in the memory and forwards the issue to the BMC (Browser Control Center). The BMC then executes subsequent debug logic, which includes: After receiving the memory PMIC error report from the CPLD, the BMC finds that the memory's PMIC status register is write-protected. After the motherboard restarts, the memory PMIC error status cannot be corrected, leading to a recurrence of the memory PMIC error and the shutdown to S5. Therefore, the BMC will remove the write protection from the power management chip register.

[0073] It should be noted that the CPLD-using part of the above debug logic is a simple read process, with minimal CPLD requirements and will not significantly impact the selection and use of existing chips. Furthermore, this invention designs a debug firmware (FW). Under normal conditions, the debug FW will not affect the normal operation of the BMC firmware (FW); once a memory PMIC anomaly occurs, the relevant debug FW will be given the highest priority to quickly locate and resolve the anomaly.

[0074] Step S202: Based on the memory fault signal, determine the candidate faulty memory.

[0075] Specifically, taking the example that each channel of the CPU can connect to two memory modules, the memory fault signal is a low-level PWR_FAIL signal, and four memory modules share one PWR_FAIL signal.

[0076] Receiving a memory fault signal indicates that at least one of the four memory locations sharing the corresponding PWR_FAIL signal has a PMIC (Physical Memory Interface) anomaly, which is the target fault memory. Therefore, the four memory locations sharing the PWR_FAIL signal are considered as candidate fault memories, and at least one of the four candidate fault memories is the target fault memory.

[0077] Step S203: Write a disable command to the power management chip register of the candidate faulty memory. The disable command is used to prevent power-on of the candidate faulty memory when the server enters the power-on state.

[0078] Specifically, taking the example of each CPU channel connecting two memory modules, since a memory fault signal indicates that at least one of the four candidate faulty memory modules is the target faulty memory, the BMC sends the information of the candidate faulty memory modules to the Platform Controller Hub (PCH). The PCH then notifies the CPU, which in turn writes a disable command to the power management chip register of all candidate faulty memory modules. When the server DC is powered on and enters the boot state, the candidate faulty memory modules with the disable command written on will not be powered on, thus preventing the anomaly from occurring.

[0079] Step S204: With the server powered on, obtain log information of the candidate faulty memory.

[0080] Specifically, the server system is powered on by DC, the server enters the power-on state, and the BMC obtains and checks the received PMIC Disable log information.

[0081] Step S205: Based on the log information, determine the target fault memory and the slot information of the target fault memory from the candidate fault memory.

[0082] Specifically, by analyzing the obtained log information, the target faulty memory is identified from the candidate faulty memory, and the slot information of the target faulty memory is determined. Alarm information can also be generated to inform server maintenance personnel which memory needs to be replaced.

[0083] The faulty memory location method provided in this embodiment, when a memory fault signal is received and the server is powered off, releases the write protection state of the power management chip register, facilitating the writing of a disable command to the candidate faulty memory. Based on the memory fault signal, a candidate faulty memory is identified, and a disable command is written to the power management chip register of the candidate faulty memory to prevent the candidate faulty memory from affecting server startup. When the server is powered on, the log information of the candidate faulty memory is obtained, and based on the log information, the target faulty memory and slot information are determined, enabling direct location of the specific memory slot where the target faulty memory exists. This solves the problem of difficulty in obtaining abnormal information sufficient for accurate faulty memory location and the inability to locate PMIC faulty memory.

[0084] In some optional implementations, the target faulty memory and its slot information are determined from the candidate faulty memory based on log information, including:

[0085] Determine if the log information contains a first-type memory error message;

[0086] If a first-type memory error message exists, the candidate faulty memory corresponding to the first-type memory error message is identified as the target faulty memory, and the slot information of the target faulty memory is determined based on the log information.

[0087] Specifically, the BMC checks if it has received PMIC Disable log information and determines whether there is a Type 1 memory error message in the log information. Type 1 memory error messages include, for example, 0X46 / 0X05 related information.

[0088] If a Type 1 memory error message appears in the log information, the candidate faulty memory corresponding to the Type 1 memory error message is the target faulty memory with a PMIC anomaly. The BMC ultimately collects all log information and determines the slot information of the target faulty memory based on the log information so that maintenance personnel can replace the target faulty memory and R&D personnel can further investigate the problem.

[0089] In this embodiment, the candidate faulty memory corresponding to the first type of memory error information in the log information is identified as the target faulty memory, and the slot information of the target faulty memory is determined. The method is simple and efficient, and can directly locate the specific memory slot, making it convenient for maintenance personnel to replace the target faulty memory.

[0090] In some optional implementations, after determining the slot information of the target faulty memory based on log information, the method further includes:

[0091] Treat the candidate faulty memory corresponding to the second type of memory error information in the log information as normal memory;

[0092] The candidate faulty memory corresponding to the third type of memory error information in the log information is taken as the faulty memory to be analyzed. The faulty memory to be analyzed is the candidate faulty memory other than the target faulty memory and normal memory.

[0093] Specifically, if a second type of memory error message appears in the log information, such as a memory error message starting with 0X0A, then the candidate faulty memory corresponding to the second type of memory error message is normal memory.

[0094] This invention refers to memory error messages of types other than the first and second types as third-type memory error messages. If a third-type memory error message appears in the log information, the candidate faulty memory corresponding to the third-type memory error message is taken as the faulty memory to be analyzed. The faulty memory to be analyzed needs to rely on the CPU memory-related register information collected by the BMC through JTAG (Joint Test Action Group, standard test access port and boundary scan structure) for further debugging. At the same time, the BMC's JTAG can collect the memory PMIC FW version to confirm whether the memory fault signal is caused by the use of an old version of the FW.

[0095] In this embodiment, the candidate faulty memory corresponding to the second type of memory error information in the log information is regarded as normal memory, and the candidate faulty memory corresponding to the third type of memory error information is regarded as faulty memory to be analyzed. This enables the present invention to identify multiple types of faulty memory and expands the application scope of the present invention.

[0096] In some alternative implementations, the write-protection state of the power management chip registers is unlocked, including:

[0097] Control the target motherboard to power down via AC;

[0098] After a preset time, the target motherboard is powered on via AC, thus releasing the write-protected state of the power management chip register.

[0099] Specifically, the write protection state of the power management chip (PMIC) register can be released using an AC cycle, which includes AC power-down and AC power-off.

[0100] The target motherboard is a server motherboard. The BMC controls the corresponding power chip to perform an AC power-down operation on the target motherboard via commands. To ensure the normal power-on sequence, after a preset time, the BMC controls the corresponding power chip to perform an AC power-on operation on the target motherboard via commands, completing the AC cycle. At this time, the write protection state of the power management chip register has been released. The preset time is, for example, 10 seconds.

[0101] In this embodiment, the target motherboard is controlled to power down via AC. After a preset time, the target motherboard is controlled to power up via AC, thereby clearing the write protection state of the power management chip register. This facilitates the subsequent writing of a disable command to the power management chip register of the candidate faulty memory, preventing the candidate faulty memory from affecting the normal startup of the server.

[0102] This embodiment provides a fault memory location system that can be deployed in the aforementioned server device. The system includes: a complex programmable device, a baseboard management controller, a platform path controller, and a central processing unit.

[0103] Complex programmable devices are used to receive memory fault signals and determine whether the server is in a powered-off state;

[0104] The complex programmable device is connected to the baseboard management controller and is used to transmit memory fault signals to the baseboard management controller;

[0105] The baseboard management controller is used to remove the write protection state of the power management chip register and to identify candidate faulty memory based on the memory fault signal.

[0106] The baseboard management controller is connected to the platform path controller and is used to send a first message to the platform path controller, which then forwards it to the central processing unit. The first message is used to identify candidate faulty memory.

[0107] The central processing unit is connected to the memory and is used to write a disable command to the power management chip register of the candidate faulty memory. The candidate faulty memory is contained in the memory, and the disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state.

[0108] The baseboard management controller controls the server to DC power on, putting the server into the power-on state, acquiring the log information of the candidate faulty memory, and determining the target faulty memory and the slot information of the target faulty memory from the candidate faulty memory based on the log information.

[0109] Specifically, in combination Figure 3 This embodiment describes a faulty memory location system comprising: a Complex Programmable Device (CPLD), a Baseboard Management Controller (BMC), a Platform Path Controller (PCH), and a Central Processing Unit (CPU). Multiple CPUs can be used, such as CPU 0 and CPU 1. The power management chip fault alarm signal (PWRGD_FAIL, or simply PWR_FAIL signal) is used, taking an example of one CPU connected to 16 memory modules, with four memory modules sharing one PWR_FAIL signal: The power management chip fault alarm signal is named PWRGD_FAIL_CPUx_AB-GH, indicating the PWR_FAIL signals connecting motherboard CPU0 and CPU1 to the memory. The two CPUs have eight PWR_FAIL signals connected to the CPLD, which can monitor for PWR_FAIL signal triggering (normally high level). For example, the power management chip fault alarm signal used by memory CPU0_CHA_DIMM1 connected to channel A of CPU0 can be named PWRGD_FAIL_CPU0_A-GH.

[0110] After the CPLD receives a memory fault signal in real time, it waits for 5 seconds to confirm that the CPLD timing has reached the S5 state. This S5 state is a power timing state, which means that the power supply connected to the Alternating Current (AC) power supply has STBY (standby) status. The S5 state indicates that the server is in a power-off state.

[0111] The CPLD is connected to the BMC. The CPLD confirms that there is a PMIC abnormality in the memory and transmits the problem to the BMC, that is, it transmits the memory fault signal to the baseboard management controller.

[0112] The BMC is used to unlock the write-protected state of the power management chip registers. Taking an example where each CPU channel can connect to two memory modules, the memory fault signal is a low-level PWR_FAIL signal, and four memory modules share one PWR_FAIL signal. Receiving a memory fault signal indicates that at least one of the four memory modules sharing the corresponding PWR_FAIL signal has a PMIC malfunction, which is the target faulty memory. Therefore, the BMC considers the four memory modules sharing the PWR_FAIL signal as candidate faulty memory modules.

[0113] The BMC is connected to the PCH. The BMC sends a first message to the PCH, which includes information about which memory modules are candidate failures. The PCH then transmits this first message to the CPU via the BIOS software, informing the CPU which memory modules are candidate failures.

[0114] The CPU is connected to the memory, and the CPU writes a disable command to the power management chip register of all candidate faulty memory.

[0115] The BMC powers on the server system via DC, putting the server into power-on mode. The BMC then retrieves and examines previously received PMIC Disable log information. By analyzing the retrieved log information, the BMC identifies the target faulty memory from the candidate faulty memory lists and determines the slot information of the target faulty memory.

[0116] It should be noted that the connection method between the server motherboard BMC and key components such as CPLD and PCH, the debugging process and logic of the motherboard CPLD obtaining the memory PWR_FAIL signal status and cooperating with the BMC to parse and resolve memory PMIC abnormal alarms can help solve the existing problems of not being able to directly locate such bugs and the problem of not being able to directly maintain similar anomalies in the data center.

[0117] The faulty memory location system provided in this embodiment utilizes the baseboard management controller to remove the write-protection state of the power management chip register, facilitating the writing of disable commands to candidate faulty memory. Based on memory fault signals, the baseboard management controller identifies candidate faulty memory and uses the central processing unit to write disable commands to the power management chip register of the candidate faulty memory, preventing the candidate faulty memory from affecting server boot-up. When the server is booted, the baseboard management controller obtains log information of the candidate faulty memory and, based on the log information, determines the target faulty memory and slot information, directly locating the specific memory slot where the target faulty memory exists. This solves the problem of difficulty in obtaining anomaly information sufficient for accurate faulty memory location and the inability to locate faulty PMIC memory.

[0118] In some alternative implementations, the baseboard management controller is connected to the central processing unit via a first link;

[0119] The baseboard management controller is used to determine whether there are first-type memory error messages in the log information;

[0120] If a first type of memory error message is present in the log information, the baseboard management controller is used to determine the candidate fault memory corresponding to the first type of memory error message as the target fault memory, obtain relevant information of the power management chip register in the target fault memory from the central processing unit through the first link, determine the slot information of the target fault memory according to the log information, and generate alarm information according to the relevant information and slot information.

[0121] The baseboard management controller is used to determine whether there are second-type memory error messages in the log information;

[0122] If a second type of memory error message is present in the log information, the baseboard management controller will treat the candidate faulty memory corresponding to the second type of memory error message as normal memory.

[0123] The baseboard management controller is used to determine whether there are third-type memory error messages in the log information;

[0124] In the event that a third type of memory error message exists in the log information, the baseboard management controller uses the candidate fault memory corresponding to the third type of memory error message in the log information as the fault memory to be analyzed. The fault memory to be analyzed is the candidate fault memory other than the target fault memory and normal memory.

[0125] Specifically, the Baseboard Management Controller (BMC) checks if it has received PMIC Disable log information and determines whether there is a Type 1 memory error message in the log information. For example, Type 1 memory error messages include information related to 0X46 / 0X05.

[0126] If a Type 1 memory error message appears in the log information, the candidate faulty memory corresponding to the Type 1 memory error message is the target faulty memory with a PMIC anomaly. The BMC obtains relevant exception register information from the CPU via the first link, namely the power management chip register information in the target faulty memory. Based on the log information, it determines the slot information of the target faulty memory, generates alarm information based on the relevant information and slot information, and reports the alarm information to the BMC so that maintenance personnel can replace the target faulty memory and R&D personnel can further investigate the problem. The BMC records all collected log information. The first link, for example, is JTAG (Joint Test Action Group, standard test access port and boundary scan structure). The JTAG bus is a dedicated bus for debugging and connecting the CPU and PCH. The BMC can obtain and parse the values ​​of the memory PMIC register and the CPU memory controller register through the JTAG bus.

[0127] BMC determines whether there are second-type memory error messages in the log information, such as memory error messages starting with 0x0A. If second-type memory error messages appear in the log information, then the candidate faulty memory corresponding to the second-type memory error message is normal memory.

[0128] This invention refers to memory error messages of types other than the first and second types as third-type memory error messages. The BMC (Browser Control Center) determines whether second-type memory error messages exist in the log information. If third-type memory error messages appear in the log information, the candidate faulty memory corresponding to the third-type memory error message is designated as the faulty memory to be analyzed. The faulty memory to be analyzed requires further debugging based on CPU memory-related register information collected by the BMC via JTAG. Simultaneously, the BMC's JTAG can collect the memory PMIC (Power Management Interface) firmware version to confirm whether the memory fault signal is caused by using an older firmware version.

[0129] In this embodiment, the baseboard management controller identifies the candidate faulty memory corresponding to the first type of memory error information in the log information as the target faulty memory, and determines the slot information of the target faulty memory. This method is simple and efficient, directly locating the specific memory slot, facilitating replacement of the target faulty memory by maintenance personnel. The baseboard management controller treats the candidate faulty memory corresponding to the second type of memory error information in the log information as normal memory, and the candidate faulty memory corresponding to the third type of memory error information as the faulty memory to be analyzed. This allows the invention to identify multiple types of faulty memory, expanding its application scope.

[0130] In some alternative implementations, the complex programmable device is connected to the substrate management controller via a second link, and the substrate management controller is connected to the platform path controller via a second link.

[0131] The complex programmable device transmits the memory fault signal to the baseboard management controller via a second link;

[0132] The baseboard management controller sends the first message to the platform path controller via the second link.

[0133] Specifically, such as Figure 3 As shown, the Complex Programmable Device (CPLD) is connected to the Baseboard Management Controller (BMC) via a second link, and the BMC is connected to the Platform Path Controller (PCH) via a second link. The second link can be, for example, I2C (Inter-Integrated Circuit, also known as IIC). This invention names the second link between the CPLD and BMC as I2C_BMC_CPLD, and the second link between the BMC and PCH as I2C_BMC_PCH. I2C_BMC_CPLD: indicates the I2C bus between the motherboard BMC and the CPLD; the BMC can connect via the CPLD.

[0134] It can obtain memory error information and motherboard power-on timing information; I2C_BMC_PCH: indicates the I2C bus between the motherboard BMC and PCH. The BMC can obtain error information of the memory status register in the CPU through the PCH, and at the same time, it can read and write the CPU registers.

[0135] Complex programmable devices (CPLDs) transmit memory fault signals to the baseboard management controller (BMC) via a second link. For example, a CPLD transmits a memory fault signal to the baseboard management controller (BMC) via I2C_BMC_CPLD. The baseboard management controller then sends a first message to the platform path controller (PCH) via the second link. For example, the BMC sends a first message to the PCH via I2C_BMC_PCH.

[0136] In this embodiment, the complex programmable device transmits a memory fault signal to the baseboard management controller via a second link, enabling the baseboard management controller to identify candidate faulty memories. The baseboard management controller then sends a first message to the platform path controller via the second link, allowing the platform path controller to determine which memories are candidate faulty memories, facilitating subsequent notification to the central processing unit.

[0137] In some alternative implementations, the central processing unit is connected to the memory via a third link;

[0138] The central processing unit writes a disable command to the power management chip register of the candidate faulty memory via the third link.

[0139] Specifically, the central processing unit (CPU) and memory are connected via a third link, such as... Figure 3 As shown, CPU0 is connected to the memory via a third link, and CPU1 is connected to the memory via a third link. The third link can be, for example, I3C (Improved Inter-Integrated Circuit, also known as IIIC). The CPU, through the I3C bus connecting the motherboard CPU and memory, can obtain memory error information and read / write to the memory PMIC registers.

[0140] Taking channel A of CPU0 as an example, the third link of channel A of CPU0 is named I3C_CPU0_CHA-H. Channel A of CPU0 is connected to CPU0_CHA_DIMM1 and CPU0_CHA_DIMM2 through I3C_CPU0_CHA-H.

[0141] The central processing unit writes a disable command to the power management chip register of the candidate faulty memory via I3C. For example, CPU0 writes a disable command to the candidate faulty memory CPU0_CHA-B_DIMM1 via I3C_CPU0_CHA-H of channel A.

[0142] In this embodiment, the central processing unit writes a disable command to the power management chip register of the candidate faulty memory through a third link to prevent the candidate faulty memory from affecting the server boot-up.

[0143] This embodiment provides a method for determining, locating, and alerting on abnormal PMIC memory, which solves the same problem and produces the same technical effect as steps S201-S205 described above. Figure 4 As shown, the method flow includes the following steps:

[0144] The CPLD detects a low level in the memory PWR_FAIL signal; the CPLD monitors the server timings to the S5 state (server shutdown state); the CPLD transmits this information to the BMC via I2C; the BMC records this information to the system log and controls the motherboard to power down; 10 seconds later, the BMC controls the motherboard to power on, completing AC... Cycle: The PMIC is unprotected from write protection; the BMC informs the PCH of the possible abnormal location via I2C, and the PCH transmits this information to the CPU via BIOS software; the CPU writes "Disable" to the suspected problematic memory PMIC via I3C, preventing the memory from powering on; the BMC controls the system to perform the power-on process, and the system boots normally, while the abnormal PMIC memory will report an error; all memory errors are checked for 0x46 / 0x05. If so, the saved memory is confirmed to be abnormal PMIC memory, and the BMC collects relevant abnormal register information from the CPU via JTAG; the BMC reports alarm information and records all collected log information; if not, all memory errors are checked for 0x0A. If so, this type of memory error is considered normal memory; otherwise, it is another type of error. Non-PMIC abnormalities do not affect normal boot and require further analysis.

[0145] This embodiment proposes a method for identifying, locating, and alarming abnormal PMIC memory. Without affecting the original functions of the motherboard, the CPLD actively informs the BMC when it detects the memory PWR_FAIL signal going low. Simultaneously, the CPLD cooperates with the BMC to locate and analyze the cause of the memory PMIC failure and provides the corresponding problematic slot information. This improves the accuracy and completeness of locating this type of problem. Furthermore, it can automatically handle this type of fault (bug) and report alarm information. This effectively solves the problem that existing technologies cannot directly locate abnormal memory slots, thus hindering debugging and server room maintenance.

[0146] This embodiment also provides a fault memory location device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0147] This embodiment provides a faulty memory location device, such as... Figure 5 As shown, it includes:

[0148] The release module 501 is used to release the write protection state of the power management chip register when a memory fault signal is received and the server is in a powered-off state.

[0149] The first determining module 502 is used to determine candidate faulty memory based on memory fault signals;

[0150] The write module 503 is used to write a disable command to the power management chip register of the candidate faulty memory. The disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state.

[0151] The acquisition module 504 is used to acquire log information of candidate faulty memory when the server enters the power-on state;

[0152] The second determination module 505 is used to determine the target fault memory and the slot information of the target fault memory from the candidate fault memory based on the log information.

[0153] In some alternative implementations, the second determining module 505 includes:

[0154] The judgment unit is used to determine whether there is a first-type memory error message in the log information;

[0155] The determination unit is used to determine the candidate faulty memory corresponding to the first type of memory error message as the target faulty memory when the first type of memory error message exists, and to determine the slot information of the target faulty memory based on the log information.

[0156] In some alternative implementations, the second determining module 505 includes:

[0157] The first unit is used to treat the candidate faulty memory corresponding to the second type of memory error information in the log information as normal memory.

[0158] The second unit is used to select the candidate faulty memory corresponding to the third type of memory error information in the log information as the faulty memory to be analyzed. The faulty memory to be analyzed is the candidate faulty memory other than the target faulty memory and normal memory.

[0159] In some alternative implementations, the release module 501 includes:

[0160] The first control unit is used to control the target motherboard to power down via AC.

[0161] The second control unit is used to control the target motherboard to power on via AC after a preset time, thereby releasing the write protection state of the power management chip register.

[0162] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0163] In this embodiment, the fault memory location device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0164] This invention also provides a computer device having the above-described features. Figure 5 The faulty memory location device shown.

[0165] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 6 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0166] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0167] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0168] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0169] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0170] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0171] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0172] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for locating faulty memory, characterized in that, The method includes: When a memory fault signal is received and the server is powered off, the write protection state of the power management chip register is released. The power management chip register whose write protection is released is the power management chip register of the memory, which is connected to the central processing unit of the server. The process of releasing the write protection state of the power management chip register includes: controlling the target motherboard to power down via AC; and after a preset time, controlling the target motherboard to power up via AC, thereby releasing the write protection state of the power management chip register. Based on the memory fault signals, candidate faulty memory is identified; Write a disable command to the power management chip register of the candidate faulty memory, wherein the disable command is used to prevent power-on of the candidate faulty memory when the server enters the power-on state; When the server is powered on, obtain the log information of the candidate faulty memory. Based on the log information, the target faulty memory and the slot information of the target faulty memory are determined from the candidate faulty memory.

2. The method according to claim 1, characterized in that, The step of determining the target faulty memory and its slot information from the candidate faulty memory based on the log information includes: Determine whether the log information contains any first-type memory error information; In the presence of the first type of memory error information, the candidate faulty memory corresponding to the first type of memory error information is determined as the target faulty memory, and the slot information of the target faulty memory is determined according to the log information.

3. The method according to claim 2, characterized in that, After determining the slot information of the target faulty memory based on the log information, the method further includes: The candidate faulty memory corresponding to the second type of memory error information in the log information is regarded as normal memory; The candidate faulty memory corresponding to the third type of memory error information in the log information is taken as the faulty memory to be analyzed, wherein the faulty memory to be analyzed is the candidate faulty memory other than the target faulty memory and the normal memory.

4. A faulty memory location system, characterized in that, The system includes: a complex programmable device, a substrate management controller, a platform path controller, and a central processing unit; The complex programmable device is used to receive memory fault signals and determine whether the server is in a shutdown state. The complex programmable device is connected to the baseboard management controller and is used to transmit the memory fault signal to the baseboard management controller; The baseboard management controller is used to remove the write protection state of the power management chip register, and to determine the candidate faulty memory based on the memory fault signal. The power management chip register whose write protection state has been removed is the power management chip register of the memory, and the memory is connected to the channel of the central processing unit. The baseboard management controller removes the write protection state of the power management chip register by: controlling the target motherboard to power down AC; and after a preset time, controlling the target motherboard to power on AC, thereby completing the removal of the write protection state of the power management chip register. The baseboard management controller is connected to the platform path controller and is used to send a first message to the platform path controller, which then forwards it to the central processing unit. The first message is used to determine the candidate faulty memory. The central processing unit is connected to the memory and is used to write a disable command to the power management chip register of the candidate fault memory, wherein the candidate fault memory is contained in the memory, and the disable command is used to prevent the candidate fault memory from being powered on when the server enters the power-on state; The baseboard management controller controls the server to DC power on, enabling the server to enter the power-on state, acquires the log information of the candidate faulty memory, and determines the target faulty memory and the slot information of the target faulty memory from the candidate faulty memory based on the log information.

5. The system according to claim 4, characterized in that, The baseboard management controller is connected to the central processing unit via a first link; The baseboard management controller is used to determine whether there is a first type of memory error information in the log information; If the first type of memory error information exists in the log information, the baseboard management controller is used to determine that the candidate faulty memory corresponding to the first type of memory error information is the target faulty memory, obtain relevant information of the power management chip register in the target faulty memory from the central processing unit through the first link, determine the slot information of the target faulty memory according to the log information, and generate alarm information according to the relevant information and the slot information; The baseboard management controller is used to determine whether there is a second type of memory error information in the log information; If the second type of memory error information exists in the log information, the baseboard management controller is used to treat the candidate faulty memory corresponding to the second type of memory error information as normal memory; The baseboard management controller is used to determine whether there is a third type of memory error information in the log information; If the third type of memory error information exists in the log information, the baseboard management controller is used to select the candidate faulty memory corresponding to the third type of memory error information in the log information as the faulty memory to be analyzed, wherein the faulty memory to be analyzed is the candidate faulty memory other than the target faulty memory and the normal memory.

6. The system according to claim 4, characterized in that, The complex programmable device is connected to the substrate management controller via a second link, and the substrate management controller is connected to the platform path controller via the second link; The complex programmable device transmits the memory fault signal to the baseboard management controller via the second link; The baseboard management controller sends the first message to the platform path controller via the second link.

7. The system according to claim 4, characterized in that, The central processing unit is connected to the memory via a third link; The central processing unit writes the disable command to the power management chip register of the candidate fault memory via the third link.

8. A faulty memory location device, characterized in that, The device includes: The deactivation module is used to deactivate the write protection state of the power management chip register when a memory fault signal is received and the server is in a powered-off state. The power management chip register whose write protection state is deactivated is the power management chip register of the memory, and the memory is connected to the central processing unit of the server. The release module includes: a first control unit for controlling the target motherboard to power down via AC; and a second control unit for controlling the target motherboard to power up via AC after a preset time, thereby releasing the write protection state of the power management chip register. The first determining module is used to determine candidate faulty memory based on the memory fault signal; The write module is used to write a disable command to the power management chip register of the candidate faulty memory, wherein the disable command is used to prevent the candidate faulty memory from being powered on when the server enters the power-on state; The acquisition module is used to acquire log information of the candidate faulty memory when the server enters the power-on state; The second determining module is used to determine the target fault memory and the slot information of the target fault memory from the candidate fault memory based on the log information.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the fault memory location method according to any one of claims 1 to 3.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the fault memory location method according to any one of claims 1 to 3.

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