Back-to-back PMOS anti-reverse circuit and working method

Abstract

This invention's back-to-back PMOS anti-reverse circuit ensures normal power supply within the product under certain key signal operating conditions, preventing secondary power supply malfunctions due to primary power supply instability. The back-to-back PMOS design enables key signal enable or disable states, while the internal low-side drive circuit still meets reverse polarity requirements. Adding a pull-down resistor at the key signal input provides a larger pull-down current, enhancing its anti-interference capability. An RC filter circuit for the key signal is also included to meet the 100ms power-down requirement. This effectively guarantees stable operation under normal control conditions and ensures 0A current under reverse polarity conditions. It is particularly suitable for the automotive electronics industry.

Description

Technical Field

[0001] This invention belongs to the technical field of vehicle engine power management, and particularly relates to a back-to-back PMOS anti-reverse circuit and its working method. Background Technology

[0002] In the power management system of an onboard engine electronic controller, reverse polarity protection is a crucial performance indicator. However, because electronic controllers typically contain low-side drive circuits, passing the reverse polarity test is often difficult. Meanwhile, ensuring the correct output of the power supply voltage within a reasonable range, and guaranteeing the normal operation of the electronic controller, is of great importance to the safety of the entire vehicle.

[0003] The traditional method, "a high-voltage side single-ended reverse connection protection circuit", discloses a reverse connection protection back-to-back PMOS circuit. However, it does not have source and gate protection for both PMOS. When the supply voltage meets the enable voltage of the NMOS in the power-on control circuit, the back-to-back PMOS is turned on. This will cause the secondary power supply chip to have output even when the supply voltage does not meet the normal operating input voltage of the secondary power supply, resulting in abnormal operation of subsequent circuits.

[0004] The traditional method, "voltage converter with reverse polarity protection diode," can effectively protect the switch from damage by introducing a reverse polarity protection diode. However, a Schottky diode must be selected, which has reverse current and reverse polarity protection functions, but it has a large reverse leakage current, high power consumption, and requires heat dissipation.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a back-to-back PMOS reverse polarity protection circuit, which achieves reverse polarity protection and ensures normal operation of the product through power management while possessing strong anti-interference capabilities. The technical solution of this invention has many beneficial effects, as described below:

[0007] A back-to-back PMOS anti-reverse circuit is provided, comprising a back-to-back PMOS circuit, a control circuit for the back-to-back PMOS circuit, and a low-side drive output circuit. The PMOS circuit includes a first PMOS transistor and a second PMOS transistor, with the first PMOS transistor as the left PMOS and the second PMOS transistor as the right PMOS. The sources of the first and second PMOS transistors are connected together. The back-to-back PMOS circuit is used to prevent reverse power supply. The low-side drive output circuit is connected to the output terminal of the back-to-back PMOS circuit, wherein:

[0008] When there is voltage at the input terminal of the first PMOS transistor and the key signal has not reached the normal operating voltage, the input voltage is conducted to the source of the second PMOS transistor through the body diode of the first PMOS transistor. The source and gate voltage values ​​of the second PMOS transistor are equal, and the second PMOS transistor is not turned on, so as to ensure that the product is not powered on when the key signal is not at the normal operating voltage.

[0009] When the power supply is reversed, the transistor in the control circuit is always in the off state. Internally, the low-side drive output circuit controls the internal body diode to conduct, causing the drain of the second PMOS transistor to connect to the input voltage. This voltage, after passing through the internal body diode, connects to the source of the first PMOS transistor. Since the gate voltage and source voltage of the first PMOS transistor are equal, the first PMOS transistor does not conduct. The control circuit uses a key signal enable circuit and selects a matching Zener diode current-limiting resistor R2 to ensure that the Zener diode V2 of the control circuit operates in a regulated state. When the key signal is within a preset voltage range, the control circuit controls the transistor in the control circuit to conduct, and both back-to-back PMOS transistors are in a normal conducting state, thus enabling the product to operate normally.

[0010] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0011] Even with a low-side drive circuit designed internally, reverse polarity protection can still be achieved, ensuring normal operation of the product as long as the primary power supply voltage meets the normal range of the secondary power supply. This invention is simple in design, easy to implement, and can be widely applied in the field of power control for automotive electronic controllers. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 Schematic diagram of a back-to-back PMOS anti-reverse circuit design;

[0014] Figure 2 This is a typical low-side drive circuit inside an onboard controller product. Detailed Implementation

[0015] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0016] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this invention, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0017] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0018] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that aspects can be practiced without these specific details. To enable those skilled in the art to better understand the invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0019] See Figure 1The back-to-back PMOS anti-reverse circuit shown includes a back-to-back PMOS circuit, a control circuit for the back-to-back PMOS circuit, and a low-side drive output circuit. The PMOS circuit includes a first PMOS transistor and a second PMOS transistor, with the first PMOS transistor as the left PMOS and the second PMOS transistor as the right PMOS. The sources of the first and second PMOS transistors are connected together. The back-to-back PMOS circuit is used to prevent reverse power supply. The low-side drive output circuit is connected to the output terminal of the back-to-back PMOS circuit, wherein:

[0020] When there is voltage at the input terminal of the first PMOS transistor and the key signal has not reached the normal operating voltage, the input voltage is conducted to the source of the second PMOS transistor through the body diode of the first PMOS transistor. The source and gate voltage values ​​of the second PMOS transistor are equal, and the second PMOS transistor is not turned on, so as to ensure that the product is not powered on when the key signal is not at the normal operating voltage.

[0021] When the power supply is reversed, the transistor in the control circuit is always in the off state. The internal body diode is turned on by the low-side drive output circuit, which causes the drain of the second PMOS transistor to be connected to the input voltage. After the internal body diode is turned on, it is connected to the source of the first PMOS transistor. Since the gate voltage and source voltage of the first PMOS transistor are equal, the first PMOS transistor does not conduct. This ensures that there is no current loop when the power supply is reversed, thus meeting the reverse polarity requirement.

[0022] The control circuit uses a key signal enable circuit and selects a matching Zener diode current-limiting resistor R2 to ensure that the Zener diode V2 of the control circuit operates in a regulated state. When the key signal is within the preset voltage range, the control circuit controls the transistor in the control circuit to be in the conducting state, and the back-to-back PMOS transistors are all in the normal conducting state, thereby enabling the product to work normally. Specifically:

[0023] The back-to-back PMOS circuit also includes:

[0024] Resistors R4, R6, R7, and Zener diode V4, among which,

[0025] The drain of the first PMOS transistor is connected to the key KEY through the control circuit of the back-to-back PMOS circuit. Resistors R4 and R6 are connected in series between the gate of the first PMOS transistor and the gate of the second PMOS transistor. A Zener diode V4 and a resistor R7 are connected in parallel between the connection of resistors R4 and R6 and the source of the first PMOS transistor and the source of the second PMOS transistor. The cathode of the Zener diode V4 is connected to the source of the first PMOS transistor.

[0026] The drain of the second PMOS transistor is connected to a Zener diode V5, and the anode of the Zener diode V5 is grounded.

[0027] When the battery has a power input, the power is input to the product through the back-to-back circuit switch.

[0028] Using a back-to-back PMOS circuit ensures that when there is voltage at the input terminal, and the key signal is not at the normal operating voltage, although the input voltage can conduct to the source of the right PMOS through the body diode of the left PMOS, the source and gate voltages of the right PMOS are equal, so the right PMOS does not conduct. To ensure that the product is not powered internally when the key signal is not at the normal operating voltage, a back-to-back PMOS reverse protection circuit is used. When the power supply is reversed, the transistor in the control loop remains in the off state. Internally, due to the low-side drive output circuit, the drain of the right PMOS receives the input voltage, which conducts through the internal body diode and then connects to the source of the left PMOS. However, because the gate and source voltages are equal, the left PMOS does not conduct. This ensures that there is no current loop when the product is powered in reverse, meeting the reverse polarity requirement.

[0029] Furthermore, the drain of the first PMOS transistor is connected to a TVS transistor V3 for suppressing surge voltage, and one end of the TVS transistor V3 is grounded.

[0030] When there is voltage at the input terminal, both the left and right PMOS are in the off state when the key signal is not enabled. Although the body diode inside the left PMOS is in the conducting state, the body diode inside the right PMOS is in the off state, so the product is not powered internally.

[0031] When the power supply is reversed, the transistor in the key signal enable circuit is always in the disabled state, and both the left and right PMOS are in the disabled state. Due to the action of the low-side drive circuit inside the product, the internal body diode of the right PMOS is in the conducting state, but the internal body diode of the left PMOS is in the disabled state, there is no current loop, and the current is 0A, so the reverse polarity requirement can be met.

[0032] The control circuit for the back-to-back PMOS circuit includes:

[0033] Resistors R1, R2, and R3; capacitors C1 and C2; TVS diode V1; and NPN transistor U3, wherein:

[0034] The collector of NPN transistor U3 is connected to the input terminal of resistor R5. The output terminal of R5 is connected to the anode of Zener diode V4 and one end of resistor R4, respectively. The emitter is grounded, and the base is connected to the anode of Zener diode V2. The cathode of Zener diode V2 is connected to the input terminal of resistor R3 and the output terminal of resistor R2, respectively. The output terminal of resistor R3 is connected to the emitter of NPN transistor U3.

[0035] The input terminal of resistor R2 is connected to the key. Resistor R1 is connected in parallel to the input terminal of R2, and capacitors C1 and C2 are connected in parallel to the output terminal. One end of the key is connected to one end of TVS diode V1, and the other end of TVS diode V1 is grounded. During the reverse polarity test of the low-side drive output circuit, power flows through the body diode V6 of NPN transistor U3 to the body diode of the second PMOS transistor, blocking the power supply loop through the first PMOS transistor, thus preventing reverse polarity. The battery acts as the power input for the key, connecting internal resistors R8 and R9 to the processor of the external controller to achieve low-side drive output and status feedback.

[0036] Since the key signal is connected to the input terminal of the control circuit through an external power supply and external switch, the required input voltage under the known stable output state of the product's secondary power supply necessitates the selection of a voltage regulator and a current limiting circuit. Simultaneously, the key signal enable circuit uses a pull-down resistor to increase its anti-interference capability, and an RC filter circuit for the key signal is added to meet the 100ms power-down requirement. Preferably, adding a pull-down resistor to the key signal further enhances its input anti-interference capability.

[0037] Furthermore, an RC filter circuit is incorporated at the key signal input terminal to meet the 100ms power-down protection requirement. The key signal enable circuit utilizes a suitable Zener diode and current-limiting resistor to ensure its regulated operation. When the key signal meets a certain voltage range, the key enable circuit controls the transistor to conduct, at which point the back-to-back PMOS transistors are also in a normally conducting state, allowing the product to operate normally. Since the key signal is connected to the control circuit input terminal via an external power supply and external switch, the required input voltage under the known stable output state of the product's secondary power supply necessitates the selection of a Zener diode and current-limiting circuit. Simultaneously, the key signal enable circuit uses pull-down resistors to increase its anti-interference capability, and the RC filter circuit for the key signal ensures it meets the 100ms power-down requirement. The key signal enable circuit ensures normal operation when the key signal meets certain working conditions, at which point both the left and right back-to-back PMOS transistors are in a conducting state, allowing the product to be powered normally internally.

[0038] Please also refer to Figure 1 , Figure 2 ;

[0039] Example 1:

[0040] Combination Figure 1 , Figure 2 ,in Figure 1Based on the circuit described in the patent "A High Voltage Side Single-Ended Reverse Connection Protection Circuit", this invention solves the problem of preventing product malfunction due to a single power supply undervoltage and protects the source and gate of both PMOS transistors, as well as the reverse polarity protection under conditions where the product has a low-side drive circuit.

[0041] The optimized back-to-back PMOS anti-reverse circuit design works by controlling the operating state of the key signal enable circuit to ensure that the primary power supply is within a suitable voltage range before supplying power to the product. The anti-reverse design is achieved through back-to-back PMOS transistors.

[0042] in Figure 1 This is a hardware schematic diagram of a back-to-back PMOS anti-reverse circuit design. Its specific working principle is as follows: The primary power supply is connected to the key signal via a switch in the vehicle. By designing R1, a pull-down resistor of 22.5KΩ is added, resulting in a circuit of approximately 10mA, increasing anti-interference capability. By designing R2 (500Ω resistor) and C1 (22uF capacitor), the key signal passes through the RC circuit to meet the 100ms power-down requirement. Since the secondary power supply chip requires an input voltage greater than 9V to operate normally, there are instances where the input voltage is less than 9V during battery depletion and normal power-on. During these instances, transistor U3 in the key signal control circuit cannot conduct. Selecting Zener diode V2 requires a Zener voltage of 7.5V, a maximum reverse cutoff voltage of 0.6V, and a minimum regulated current of 2mA under normal operating conditions. Therefore, when the Zener diode is operating in regulated mode, its current-limiting resistor R2 is 500Ω, and the current flowing through the Zener diode is 3mA, which meets the design requirement of being greater than the minimum regulated current of 2mA. That is, when the battery and the test signal are connected through an external switch, and the +24V_BATTARY voltage of the battery is greater than 9V, the transistor in the key signal enable circuit is saturated and conducting, and the back-to-back PMOS is in a bidirectional conducting state. Only then does the secondary power supply begin. The product operates normally after the conversion. In the back-to-back PMOS main circuit, R7 is a 100k resistor, which connects the gate and source terminals of the MOSFETs to ensure that when transistor U3 is not conducting, the source and drain voltages of U1 and U2 are the same, and both MOSFETs are in the off state. When transistor U3 is conducting, R5 is a 5.6k resistor to ensure that when the MOSFET is enabled, the source and gate voltage of the MOSFET does not exceed 12V. Zener diode V4 is selected with a Zener voltage of 12V and a minimum Zener current of 2mA to ensure that it operates in a regulated state. TVS diodes are selected for V3 and V4 to suppress surge voltage.

[0043] Figure 2 It is the low-side drive circuit inside the product. When the power supply is reversed, the power supply will go through the body diode and the reverse diode inside U3 to the source of the PMOS transistor U2 on the right. Although it goes through the source of U1 through the body diode inside the product, there is no power supply loop when U1 is not conducting, which can achieve the design requirement of reverse polarity.

[0044] Secondly, a method for operating a back-to-back PMOS anti-reverse circuit is provided. Using the aforementioned back-to-back PMOS anti-reverse circuit, the method is characterized by comprising:

[0045] Step 1: Based on the normal power supply voltage required by the product (e.g., electronic controller), determine the parameters of the Zener diode V2 and the resistance value of the current limiting resistor to ensure that the key signal input voltage can control the transistor to enable / disable.

[0046] Step 2: When the key signal is disabled, the first PMOS transistor and the second PMOS transistor are disabled. The body diode inside the first PMOS transistor is turned on, and when the second PMOS transistor is not turned on, the input power supply does not form a loop.

[0047] When the key signal is enabled, both the first PMOS transistor and the second PMOS transistor are in the on state, and the power supply voltage supplies power to the product through the first PMOS transistor and the second PMOS transistor.

[0048] When the power supply is reversed, the transistor in the control circuit is disabled, the body diode of the second PMOS transistor is turned on, and when the first PMOS transistor is not turned on, the reverse power supply does not form a current loop, thus preventing the circuit from being powered by reverse polarity. 。

[0049] Under certain operating conditions of the key signal, the product can be powered normally internally without causing abnormal operation of the secondary power supply due to unstable primary power output. Through the PMOS back-to-back design, the key signal can be enabled or disabled. The low-side drive circuit designed inside the product can still meet the reverse polarity requirement. The pull-down resistor at the key signal input terminal is added to obtain a larger pull-down current, thereby increasing its anti-interference capability. The RC filter circuit of the key signal is added to meet the 100ms power-down requirement.

[0050] The product provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the invention claims.

Claims

1. A back-to-back PMOS anti-reverse circuit, characterized in that, The circuit includes a back-to-back PMOS circuit, a control circuit for the back-to-back PMOS circuit, and a low-side drive output circuit. The PMOS circuit includes a first PMOS transistor and a second PMOS transistor, with the first PMOS transistor as the left PMOS and the second PMOS transistor as the right PMOS. The sources of the first and second PMOS transistors are connected together. The back-to-back PMOS circuit prevents reverse power supply. The low-side drive output circuit is connected to the output terminal of the back-to-back PMOS circuit. When there is voltage at the input terminal of the first PMOS transistor and the key signal has not reached the normal operating voltage, the input voltage is conducted to the source of the second PMOS transistor through the body diode of the first PMOS transistor. The source and gate voltage values ​​of the second PMOS transistor are equal, and the second PMOS transistor is not turned on, so as to ensure that the product is not powered on when the key signal is not at the normal operating voltage. When the power supply is reversed, the transistor in the control circuit is always in the off state. The internal body diode is turned on by the low-side drive output circuit, which causes the drain of the second PMOS transistor to be connected to the input voltage. After the internal body diode is turned on, it is connected to the source of the first PMOS transistor. Since the gate voltage and source voltage of the first PMOS transistor are equal, the first PMOS transistor is not turned on. The control circuit uses a key signal enable circuit and selects a matching Zener diode current-limiting resistor R2 to ensure that the Zener diode V2 of the control circuit works in a regulated state. When the key signal is within a preset voltage range, the control circuit controls the transistor of the control circuit to be in the conducting state, and the back-to-back PMOS are all in the normal conducting state, thereby enabling the product to work normally. The back-to-back PMOS circuit also includes resistors R4, R6, and R7, and a Zener diode V4. The drain of the first PMOS transistor is connected to a key via the control circuit of the back-to-back PMOS circuit. Resistors R4 and R6 are connected in series between the gates of the first and second PMOS transistors. A Zener diode V4 and resistor R7 are connected in parallel between the connection of resistors R4 and R6 and the sources of the first and second PMOS transistors. The cathode of Zener diode V4 is connected to the source of the first PMOS transistor. A Zener diode V5 is connected to the drain of the second PMOS transistor, and the anode of Zener diode V5 is grounded. When the battery has power input, the input is switched on via the back-to-back circuit. The drain of the first PMOS transistor is connected to a TVS transistor V3 for suppressing surge voltage, and one end of the TVS transistor V3 is grounded. The control circuit of the back-to-back PMOS circuit includes resistors R1 and R3, capacitors C1 and C2, a TVS diode V1, and an NPN transistor U3. The collector of the NPN transistor U3 is connected to the input terminal of resistor R5. The output terminal of resistor R5 is connected to the anode of Zener diode V4 and one end of resistor R4, with its emitter grounded. Its base is connected to the anode of Zener diode V2. The cathode of Zener diode V2 is connected to the input terminal of resistor R3 and the output terminal of resistor R2. The output terminal of resistor R3 is connected to the emitter of transistor U3. The input terminal of the current-limiting resistor R2 is connected to the key KEY. A resistor R1 is connected in parallel to the input terminal of the current-limiting resistor R2, and capacitors C1 and C2 are connected in parallel to the output terminal. One end of the key KEY is connected to one end of the TVS diode V1, and the other end of the TVS diode V1 is grounded.

2. The back-to-back PMOS anti-reverse circuit according to claim 1, characterized in that, During the reverse polarity test, the power supply of the low-side drive output circuit flows into the body diode of the second PMOS transistor through the body diode of transistor U3, and blocks the power supply circuit through the first PMOS transistor, thus preventing reverse polarity.

3. The back-to-back PMOS anti-reverse circuit according to claim 2, characterized in that, The key signal input terminal is equipped with an RC filter circuit to meet the 100ms power-off protection requirement.

4. A method for operating a back-to-back PMOS anti-reverse circuit, characterized in that, The back-to-back PMOS anti-reverse circuit according to any one of claims 1 to 3 is characterized in that the operating method includes, Step 1: Based on the normal power supply voltage required by the product, determine the parameters of the Zener diode V2 and the resistance value of the current limiting resistor to ensure that the key signal input voltage can control the transistor to enable / disable. Step 2: When the key signal is disabled, the first PMOS transistor and the second PMOS transistor are disabled. The body diode inside the first PMOS transistor is turned on, and when the second PMOS transistor is not turned on, the input power supply does not form a loop. When the key signal is enabled, both the first PMOS transistor and the second PMOS transistor are in the on state, and the power supply voltage supplies power to the product through the first PMOS transistor and the second PMOS transistor. When the power supply is reversed, the transistor in the control circuit is disabled, the body diode of the second PMOS transistor is turned on, and when the first PMOS transistor is not turned on, the reverse power supply does not form a current loop, which is used to prevent the circuit from being powered by the reverse polarity.

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