Display data processing method and apparatus, and display apparatus

Abstract

A display data processing method, a display data processing device applying the method, and a multi-view pixel island architecture (100b) based display device (100c) including the display data processing device. The display data processing method includes: receiving a pixel display data stream, wherein the pixel display data stream includes a plurality of sub-pixel display data (210) corresponding to respective pixels; converting the pixel display data stream into a pixel island (103) display data stream, wherein the pixel island (103) display data stream includes a plurality of view display data (220) corresponding to respective pixel islands (103); and generating single-row display data based on the pixel island (103) display data stream, wherein the single-row display data includes view display data corresponding to output channels of a plurality of chips one by one (230).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display data processing method applicable to multi-viewpoint pixel islands and a display data processing apparatus using the method, and also to a display apparatus including the display data processing apparatus. Background Technology

[0002] With the development of display technology, the demand for display products with high resolution, high refresh rate, and 3D display effects is increasing. Traditional display products are generally based on a pixel architecture design that includes RGB subpixels, making it difficult to meet the requirements for high resolution, high refresh rate, and 3D display effects. Recently, the concept of pixel islands has been proposed, in which multiple viewpoints are designed as a pixel island, enabling high resolution and multi-view 3D display effects. Furthermore, when the pixel island architecture is combined with a multiplexing (MUX) design, even better display effects can be achieved.

[0003] However, due to the design differences between the pixel island architecture and the RGB pixel architecture, products based on the pixel island architecture need to perform display data processing on the image based on the pixel island architecture first, otherwise they cannot be displayed normally. Summary of the Invention

[0004] According to a first aspect of this disclosure, a display data processing method is provided, comprising: receiving a pixel display data stream, wherein the pixel display data stream includes a plurality of sub-pixel display data corresponding to each pixel; converting the pixel display data stream into a pixel island display data stream, wherein the pixel island display data stream includes a plurality of viewpoint display data corresponding to each pixel island; and generating single-line display data based on the pixel island display data stream, wherein the viewpoint display data included in the single-line display data corresponds one-to-one with the output channels of a plurality of chips.

[0005] According to some exemplary embodiments, the step of converting the pixel display data stream into a pixel island display data stream includes: obtaining i×k sub-pixel display data corresponding to i pixels from the pixel display data stream, where i and k are both integers greater than 0; marking m×n sub-pixel display data among the i×k sub-pixel display data as viewpoint display data corresponding to m×n viewpoints of m pixel islands, where m and n are both integers greater than 0, and m×n = i×k; and rearranging the viewpoint display data according to the architecture of the pixel islands to convert the pixel display data stream into the pixel island display data stream.

[0006] According to some exemplary embodiments, the step of converting the pixel display data stream into a pixel island display data stream includes: obtaining i×k sub-pixel display data corresponding to i pixels from the pixel display data stream, where i and k are both integers greater than 0; marking m×n sub-pixel display data among the i×k sub-pixel display data as viewpoint display data corresponding to m×n viewpoints of m pixel islands, where m and n are both integers greater than 0, and m×n < i×k; marking the sub-pixel display data among the i×k sub-pixel display data that are not marked as viewpoint display data as dummy viewpoint display data; and rearranging the viewpoint display data and the dummy viewpoint display data together according to the architecture of the pixel islands to convert the pixel display data stream into the pixel island display data stream.

[0007] According to some exemplary embodiments, the step of generating single-line display data based on the pixel island display data stream includes: performing data functionalization processing on the pixel island display data stream to generate a data functionalized pixel island display data stream; distinguishing the viewpoint display data corresponding to each chip from the data functionalized pixel island display data stream according to the amount of viewpoint display data corresponding to each chip in the single-line display data; and sequentially reorganizing the viewpoint display data corresponding to each chip according to the chip input port order according to the numbering order of the multiple chips to generate the single-line display data.

[0008] According to some exemplary embodiments, the step of performing data functionalization processing on the pixel island display data stream to generate a data functionalized pixel island display data stream includes: reorganizing the pixel island display data stream into an odd-numbered chip display data stream and an even-numbered chip display data stream, wherein the odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips; wherein the odd-numbered chip display data stream and the even-numbered chip display data stream together constitute the data functionalized pixel island display data stream.

[0009] According to some exemplary embodiments, the step of distinguishing viewpoint display data corresponding to each chip from the pixel island display data stream after data functionalization, based on the amount of viewpoint display data corresponding to each chip in the single row of display data, includes: distinguishing viewpoint display data corresponding to each odd-numbered chip among the plurality of chips from the odd-numbered chip display data stream based on the amount of viewpoint display data corresponding to each chip in the single row of display data; and distinguishing viewpoint display data corresponding to each even-numbered chip among the plurality of chips from the even-numbered chip display data stream based on the amount of viewpoint display data corresponding to each chip in the single row of display data.

[0010] According to some exemplary embodiments, the step of performing data functionalization processing on the pixel island display data stream to generate a pixel island display data stream after data functionalization includes: reorganizing the pixel island display data stream into an odd-numbered chip display data stream and an even-numbered chip display data stream, wherein the odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips; and reorganizing the odd-numbered chip display data stream into an odd-numbered chip multiplexed display data stream with the same number of multiplexed groups as the pixel island. In this process, an odd-numbered chip multiplexed display data stream is used to provide viewpoint display data to an odd-numbered chip corresponding to a corresponding multiplexed group; the even-numbered chip display data stream is reorganized into an even-numbered chip multiplexed display data stream with the same number of multiplexed groups as the pixel island, wherein an even-numbered chip multiplexed display data stream is used to provide viewpoint display data to an even-numbered chip corresponding to a corresponding multiplexed group; and all the odd-numbered chip multiplexed display data streams and all the even-numbered chip multiplexed display data streams together constitute the pixel island display data stream after data functionalization.

[0011] According to some exemplary embodiments, the step of distinguishing viewpoint display data corresponding to each chip from the pixel island display data stream after data functionalization, based on the amount of viewpoint display data corresponding to each chip in the single row of display data, includes: distinguishing viewpoint display data provided to each odd-numbered chip from all odd-numbered chip multiplexed display data streams based on the amount of viewpoint display data corresponding to each chip in the single row of display data; and distinguishing viewpoint display data provided to each even-numbered chip from all even-numbered chip multiplexed display data streams based on the amount of viewpoint display data corresponding to each chip in the single row of display data.

[0012] According to some exemplary embodiments, the step of performing data functionalization processing on the pixel island display data stream to generate a data functionalized pixel island display data stream includes: recombining the pixel island display data stream into a number of multiplexed display data streams equal to the number of multiplexed groups of the pixel island, wherein one multiplexed display data stream provides viewpoint display data for the pixel island included in a corresponding multiplexed group; and all multiplexed display data streams constitute the data functionalized pixel island display data stream.

[0013] According to some exemplary embodiments, the step of generating single-line display data based on the pixel island display data stream includes: distinguishing the viewpoint display data corresponding to each chip from the pixel island display data stream according to the amount of viewpoint display data corresponding to each chip in the single-line display data; and sequentially reorganizing the viewpoint display data corresponding to each chip according to the order of the chip input ports in the numerical order of the plurality of chips to generate the single-line display data.

[0014] According to some exemplary embodiments, the step of generating single-line display data based on the pixel island display data stream includes: removing the dull point display data from the pixel island display data stream; and generating the single-line display data based on the pixel island display data stream after removing the dull point display data.

[0015] According to some exemplary embodiments, the display data processing method further includes: when the bit width of the viewpoint display data included in the single-line display data is smaller than the bit width of the display screen display data, compensating for the viewpoint display data based on the difference between the two.

[0016] According to some exemplary embodiments, when the difference between the bit width of the viewpoint display data included in the single-line display data and the bit width of the display screen display data is a bits, the viewpoint display data is multiplied by 2a for compensation, where a is an integer greater than 0.

[0017] According to some exemplary embodiments, the display data processing method further includes: caching the single-line display data; and outputting the single-line display data in response to a received power signal.

[0018] According to a second aspect of this disclosure, a display data processing apparatus is provided, comprising: a pixel display data stream receiving module configured to: receive a pixel display data stream, wherein the pixel display data stream includes a plurality of sub-pixel display data corresponding to each pixel; a display data stream conversion module configured to: convert the pixel display data stream into a pixel island display data stream, wherein the pixel island display data stream includes a plurality of viewpoint display data corresponding to each pixel island; and a single-line display data generation module configured to: generate single-line display data based on the pixel island display data stream, wherein the viewpoint display data included in the single-line display data corresponds one-to-one with the output channels of a plurality of chips.

[0019] According to some exemplary embodiments, the display data processing apparatus further includes a display data compensation module, which is configured to compensate the viewpoint display data based on the difference when the bit width of the viewpoint display data included in the single-line display data is smaller than the bit width of the display screen display data.

[0020] According to some exemplary embodiments, the display data processing apparatus further includes: a display data access module configured to: cache the single-line display data; and output the single-line display data in response to a received power signal.

[0021] According to some exemplary embodiments, the display data processing apparatus further includes: an arrangement module configured to: determine the arrangement of pixel display data corresponding to each pixel of the image to be displayed.

[0022] According to some exemplary embodiments, the display data processing device is implemented based on an FPGA.

[0023] According to a third aspect of this disclosure, a display device based on a multi-view pixel island architecture is provided, wherein the multi-view pixel island architecture-based display device includes a display data processing device provided according to a second aspect of this disclosure.

[0024] Therefore, the display data processing method and apparatus provided in this disclosure, by converting pixel-based display data into pixel-island-based display data, not only enables normal image display on display devices based on multi-view pixel-island architecture, but also achieves higher display resolution and multi-view 3D display effects. Furthermore, by performing functional processing, data compensation, and data buffering on the data, the display data processing method and apparatus provided in this disclosure can be compatiblely applied to display data processing in various hardware structures, including MUX design, multi-COF chip design, and COF chip parity alternation design. Thus, it has versatility for data processing on pixel-island-based display devices. Attached Figure Description

[0025] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so as to provide a fuller understanding of the further details, features, and advantages of this disclosure; in the accompanying drawings:

[0026] Figure 1a A pixel architecture is illustrated schematically;

[0027] Figure 1b A multi-view pixel island architecture is schematically illustrated.

[0028] Figure 1c A display device based on a pixel island architecture and featuring a MUX design is schematically illustrated.

[0029] Figure 2 A display data processing method according to some exemplary embodiments of the present disclosure is illustrated in the form of a flowchart;

[0030] Figure 3Further exemplary embodiments of this disclosure are shown Figure 2 The diagram shows some details of the data processing method;

[0031] Figure 4 According to some exemplary embodiments of this disclosure, a data stream conversion process from pixel display data stream to pixel island display data stream is schematically illustrated;

[0032] Figure 5 Further exemplary embodiments of this disclosure are shown Figure 2 The diagram shows some details of the data processing method;

[0033] Figure 6 According to some exemplary embodiments of this disclosure, a data stream conversion process from pixel display data stream to pixel island display data stream is schematically illustrated;

[0034] Figure 7 Further exemplary embodiments of this disclosure are shown Figure 2 The diagram shows some details of the data processing method;

[0035] Figure 8 Further exemplary embodiments of this disclosure are shown Figure 7 The diagram shows some details of the data processing method;

[0036] Figure 9 Further exemplary embodiments of this disclosure are shown Figure 7 The diagram shows some details of the data processing method;

[0037] Figure 10 Further exemplary embodiments of this disclosure are shown Figure 7 The diagram shows some details of the data processing method;

[0038] Figure 11 Further exemplary embodiments of this disclosure are shown Figure 7 The diagram shows some details of the data processing method;

[0039] Figure 12 Further exemplary embodiments of this disclosure are shown Figure 7 The diagram shows some details of the data processing method;

[0040] Figure 13 According to some exemplary embodiments of this disclosure, a data functionalization process for a pixel island display data stream is schematically illustrated;

[0041] Figure 14The interface requirements of the chip in the CEDS interface transmission protocol are illustrated schematically.

[0042] Figure 15 It schematically shows the following based on Figure 14 The interface of the chip shown requires a method for reorganizing the viewpoint display data included in the pixel island display data stream;

[0043] Figure 16 Further exemplary embodiments of this disclosure are shown Figure 2 The diagram shows some details of the data processing method;

[0044] Figure 17 Another display data processing method according to some exemplary embodiments of this disclosure is illustrated in the form of a flowchart;

[0045] Figure 18 This schematically illustrates a compensation process for viewpoint display data.

[0046] Figure 19 Another display data processing method according to some exemplary embodiments of this disclosure is illustrated in the form of a flowchart;

[0047] Figure 20 This schematically illustrates the access process of caching and retrieving single-line display data;

[0048] Figures 21a to 21d Some display data processing apparatuses according to some exemplary embodiments of the present disclosure are schematically illustrated in block diagram form;

[0049] Figure 22 A display device based on a multi-view pixel island architecture according to some exemplary embodiments of the present disclosure is illustrated schematically in block diagram form.

[0050] It should be understood that the contents shown in the accompanying drawings are merely illustrative and therefore need not be drawn to scale. Furthermore, throughout all the accompanying drawings, identical or similar features are indicated by identical or similar reference numerals. Detailed Implementation

[0051] The following description provides specific details of various exemplary embodiments of the present disclosure so that those skilled in the art can fully understand and implement the technical solutions according to the present disclosure.

[0052] See Figure 1a The illustration shows a pixel architecture. Figure 1aThe pixel architecture 100a shown includes eight pixels 101, each of which comprises three sub-pixels: a red sub-pixel R (i.e., R sub-pixel), a green sub-pixel G (i.e., G sub-pixel), and a blue sub-pixel B (i.e., B sub-pixel). The multiple pixels 101 are arranged in an array, enabling the display of an image based on the received RGB sub-pixel display data. It should be understood that... Figure 1a The pixel architecture 100a shown is exemplary and not limiting. In some exemplary embodiments not illustrated in this disclosure, each pixel may also include sub-pixels of other colors, such as white sub-pixels (i.e., W sub-pixels), or each pixel may include more than one R sub-pixel, G sub-pixel, and / or B sub-pixel.

[0053] See Figure 1b It schematically illustrates a multi-viewpoint pixel island architecture. Figure 1b The multi-view pixel island architecture 100b shown includes 12 viewpoints 102, where each viewpoint 102 includes three sub-pixels: an R sub-pixel, a G sub-pixel, and a B sub-pixel. Based on the multi-view pixel island architecture, high display resolution and multi-view 3D display effects can be achieved. However, due to the design differences between the pixel island architecture and the pixel architecture, pixel display data that includes multiple sub-pixel display data (e.g., RGB sub-pixel display data) suitable for the pixel architecture needs to be converted into pixel island display data that includes multiple viewpoint display data suitable for the multi-view pixel island architecture. It should be understood that, by design, the viewpoints in the pixel island correspond to the sub-pixels in the pixel.

[0054] See Figure 1c This schematically illustrates a display device based on a pixel island architecture and featuring a MUX design. For example... Figure 1c As shown, the display device 100c includes a plurality of pixel islands 103, wherein the plurality of pixel islands 103 are divided into two multiplexing groups, namely: MUX1 and MUX2. Therefore, Figure 1cThe MUX design shown is a MUX1:2 design. Each of the multiple pixel islands 103 included in the multiplexed group MUX1 is electrically connected to a corresponding switching circuit element (e.g., a thin-film transistor) 104, such that when a strobe signal is received from the multiplexed group MUX1, all switching circuit elements 104 are turned on, allowing pixel island display data to be transmitted to the corresponding pixel island 103 included in the multiplexed group MUX1. Similarly, each of the multiple pixel islands 103 included in the multiplexed group MUX2 is also electrically connected to a corresponding switching circuit element (e.g., a thin-film transistor) 105, such that when a strobe signal is received from the multiplexed group MUX2, all switching circuit elements 105 are turned on, allowing pixel island display data to be transmitted to the corresponding pixel island 103 included in the multiplexed group MUX2. The multi-view pixel island architecture combined with the MUX design enables higher display resolution.

[0055] See Figure 2 The flowchart illustrates a display data processing method according to some exemplary embodiments of the present disclosure, which is capable of converting display data suitable for pixels into display data suitable for pixel islands. Figure 2 As shown, the data processing method 200 includes steps 210, 220 and 230.

[0056] In step 210, a pixel display data stream is received, wherein the pixel display data stream includes a plurality of subpixel display data corresponding to each pixel. As a non-limiting example, when each pixel includes RGB subpixels, the pixel display data stream may include RGB subpixel display data corresponding to the RGB subpixels of each pixel. However, it should be understood that the pixel display data stream may also include more types of subpixel data; for example, when the pixel also includes W subpixels, the pixel display data stream may also include W subpixel display data.

[0057] In step 220, the pixel display data stream is converted into a pixel island display data stream, wherein the pixel island display data stream includes multiple viewpoint display data corresponding to each pixel island. As explained earlier, due to the design differences between the pixel island architecture and the pixel architecture, the pixel display data stream including multiple sub-pixel display data (e.g., RGB sub-pixel display data) needs to be converted into a pixel island display data stream including multiple viewpoint display data in order to be applicable to a multi-view pixel island architecture. Therefore, it should be understood that this conversion essentially establishes a one-to-one correspondence between the multiple sub-pixel display data of the pixel display data stream and the multiple viewpoint display data of the pixel island, thereby converting the pixel display data stream into a pixel island display data stream.

[0058] See Figure 3According to some exemplary embodiments of this disclosure, it further illustrates Figure 2 This is one embodiment of step 220 in the displayed data processing method 200. For example... Figure 3 As shown, the implementation method 220a of step 220 includes steps 220a-1, 220a-2 and 220a-3.

[0059] In step 220a-1, i×k sub-pixel display data corresponding to i pixels are obtained from the pixel display data stream, where i and k are both integers greater than 0. In this step, the display data corresponding to a pixel obtained from the data input channel during each valid clock pulse is truncated according to the size of the sub-pixel display data (e.g., 8-bit width) to obtain the corresponding sub-pixel display data (e.g., for a pixel including RGB sub-pixels, the display data of each pixel includes sub-pixel display data corresponding to R sub-pixels, G sub-pixels, and B sub-pixels respectively, i.e., R sub-pixel display data, G sub-pixel display data, and B sub-pixel display data), and can be determined in a specific order (e.g., from low bit to high bit) as, for example, R1, G1, B1, R2, ... etc. Thus, the extraction of sub-pixel display data from the input data stream is achieved. It should be understood that in some exemplary embodiments, in one valid clock pulse, sub-pixel display data corresponding to one pixel can be obtained from one data input channel. Therefore, when multiple data input channels are available (e.g., 8 data input channels), subpixel display data corresponding to multiple pixels (e.g., 8 pixels) can be obtained from multiple data input channels within a single valid clock pulse. However, in some other exemplary embodiments, subpixel display data corresponding to multiple pixels (e.g., two or more pixels) can also be obtained from one data input channel within a single valid pixel clock pulse. It should be understood that this disclosure does not limit the manner or quantity of obtaining subpixel display data from the data input channels.

[0060] In step 220a-2, m×n sub-pixel display data from the i×k sub-pixel display data are marked as viewpoint display data corresponding to m×n viewpoints of m pixel islands, where m and n are both integers greater than 0, and m×n = i×k. That is, in this step, the sub-pixel display data of multiple pixels obtained from the pixel display data stream in step 220a-1 are matched one-to-one with the viewpoints of the corresponding number of pixel islands. It should be understood that when matching sub-pixel display data with viewpoints, it is necessary to ensure that the number of sub-pixel display data acquired in each valid clock pulse matches the number of viewpoints. Figure 3In the exemplary embodiment shown, the number of subpixel display data included in the plurality of pixels matches the number of viewpoints included in the plurality of pixel islands. Cases where the two do not match will be described in detail below.

[0061] In step 220a-3, the viewpoint display data is rearranged according to the architecture of the pixel island to convert the pixel display data stream into the pixel island display data stream. This is because, in step 220a-2, the marking of sub-pixel display data to viewpoint display data can be performed solely based on the sequential numbering of viewpoints within the pixel island. The resulting marking may not conform to the actual arrangement of multiple viewpoints within the pixel island. Therefore, it is necessary to rearrange the marked viewpoint display data according to the pixel island architecture to generate the pixel island display data stream. It should be understood that, depending on the actual architecture of the pixel island, there can be different ways to rearrange the viewpoint display data, and this disclosure does not limit this.

[0062] It should also be understood that, in Figure 3 In the exemplary embodiment shown, marking subpixel display data as viewpoint display data means establishing a one-to-one mapping relationship between the subpixel display data and the viewpoints of the pixel islands. For example, this step can be used to add corresponding labels to m×n subpixel display data out of i×k subpixel display data. These labels map the marked subpixel display data to the viewpoints of the corresponding pixel islands, so the marked subpixel display data can be used as viewpoint display data for that viewpoint. Therefore, in some non-limiting examples, the labels of all marked subpixel display data together form a label information table, which describes the mapping relationship between each marked subpixel display data and the viewpoint of the corresponding pixel island. In this case, the subpixel display data and the corresponding label information table can be considered to constitute the viewpoint display data.

[0063] See Figure 4 According to some exemplary embodiments of this disclosure, it schematically illustrates a data stream conversion process from pixel display data stream to pixel island display data stream, the data stream conversion process corresponding to Figure 3 The method shown. (As illustrated) Figure 4 As shown, the data stream conversion process 220' includes four stages: data reception, data extraction, data conversion, and pixel islanding. In the data reception stage, input data can be received from the eight data input channels (i.e., data-in1-8) shown in the diagram. This input data constitutes the pixel display data stream, which includes the sub-pixel display data corresponding to each pixel. In the data extraction stage, within one valid clock pulse, display data corresponding to one pixel can be obtained from each data input channel. Therefore, within one valid clock pulse, from... Figure 4The eight data input channels shown (data-in1-8) can acquire display data corresponding to eight pixels. Figure 4 In the exemplary embodiment shown, each pixel includes R sub-pixels, G sub-pixels, and B sub-pixels. Therefore, the display data of each pixel is truncated according to the size of the sub-pixel display data (e.g., 8-bit width), thereby obtaining R sub-pixel display data, G sub-pixel display data, and B sub-pixel display data, which can be labeled as R1, G1, B1, R2, ..., R8, G8, B8, for a total of 24 sub-pixel display data. Figure 4 In the exemplary embodiment shown, each pixel island includes 12 viewpoints. Therefore, in the data marking stage, the 24 sub-pixel display data can be marked according to the viewpoint numbering order to establish a one-to-one mapping relationship between the 24 sub-pixel display data of the 8 pixels (i.e., sub-pixel display data R1, G1, B1, R2, ..., R8, G8, B8) and the 24 viewpoints of the two pixel islands (i.e., a-VIEW1, a-VIEW2, ..., b-VIEW11, b-VIEW12). Figure 4 As shown, the data labeling stage displays a label information table obtained by labeling 24 sub-pixel display data, which describes the correspondence between each sub-pixel display data and the corresponding viewpoints in the pixel island. Finally, in the pixel islanding stage, the 24 viewpoint display data (i.e., the 24 sub-pixel display data and their corresponding label information tables) are rearranged according to the actual architecture of the pixel island. Figure 4 As shown, for example, for each data input channel, the low-order viewpoint display data and the high-order viewpoint display data can be interchanged. Then, the rearranged viewpoint display data constitutes the pixel island display data stream.

[0064] See Figure 5 According to other exemplary embodiments of this disclosure, it further illustrates Figure 2 Another embodiment of step 220 in the data processing method 200 shown. For example... Figure 5 As shown, implementation 220b of step 220 includes steps 220b-1, 220b-2, 220b-3 and 220a-4.

[0065] In step 220b-1, i×k sub-pixel display data corresponding to the i pixels are obtained from the pixel display data stream, where i and k are both integers greater than 0. It should be understood that this step is the same as step 220a-1 already described, and therefore will not be repeated here.

[0066] In step 220b-2, m×n sub-pixel display data from the i×k sub-pixel display data are marked as viewpoint display data corresponding to the m×n viewpoints of the m pixel islands, where m and n are both integers greater than 0, and m×n < i×k. That is, in this step, the sub-pixel display data of multiple pixels obtained from the pixel display data stream in step 220b-1 are matched one-to-one with the corresponding number of pixel island viewpoints. In this exemplary embodiment, the number of sub-pixel display data included in multiple pixels does not match the number of viewpoints included in multiple pixel islands, and the amount of viewpoint display data is less than the amount of sub-pixel display data. Therefore, in this step, m×n sub-pixel display data from the i×k sub-pixel display data are marked.

[0067] In step 220b-3, the sub-pixel display data that were not marked as viewpoint display data among the i×k sub-pixel display data are marked as dummy viewpoint display data. The purpose of dummy viewpoint display data is to match the quantity of i×k sub-pixel display data together with the m×n viewpoint display data, thereby facilitating subsequent data functionalization processing. After data functionalization processing, the dummy viewpoint display data can be removed during the process of distinguishing the viewpoint display data corresponding to each chip from the pixel island display data stream, which will be detailed below.

[0068] In step 220b-4, the viewpoint display data and the dumb viewpoint display data are rearranged together according to the architecture of the pixel islands to convert the pixel display data stream into the pixel island display data stream. This step is largely the same as step 220a-3, which has already been described, and therefore will not be repeated here.

[0069] It should be understood that, in Figure 5 In the exemplary embodiment shown, marking subpixel display data as viewpoint display data means establishing a one-to-one mapping relationship between the numbered subpixel display data and the viewpoints of the pixel islands. For example, this step can be used to add corresponding labels to m×n subpixel display data out of i×k subpixel display data. These labels map the marked subpixel display data to the viewpoints of the pixel islands, so the marked subpixel display data can be used as viewpoint display data for that viewpoint. Furthermore, the subpixel display data that are not marked as viewpoint display data out of the i×k subpixel display data also have corresponding labels, i.e., labels marking these subpixel display data as dumb viewpoint display data. In a non-limiting example, the labels of all marked subpixel display data (including labels marked as dumb viewpoint display data) can together form a label information table, which describes the mapping relationship between each marked subpixel display data and the viewpoint of the corresponding pixel island, and also describes the mapping relationship between each unmarked subpixel display data and dumb viewpoint display data.

[0070] See Figure 6 According to some exemplary embodiments of this disclosure, another data stream conversion process from pixel display data stream to pixel island display data stream is schematically illustrated, which corresponds to Figure 5 The method shown. (As illustrated) Figure 6 As shown, the data stream conversion process 220" also includes four stages: data reception, data extraction, data conversion, and pixel islanding. In the data reception stage, input data can be received from the eight data input channels (i.e., data-in1-8) shown in the diagram. This input data constitutes the pixel display data stream, which includes the sub-pixel display data corresponding to each pixel. In the data extraction stage, within one valid clock pulse, display data corresponding to one pixel can be obtained from each data input channel. Therefore, within one valid clock pulse, from... Figure 6 The eight data input channels shown, data-in1-8, can acquire display data corresponding to eight pixels. Figure 6 In the exemplary embodiment shown, each pixel includes R sub-pixels, G sub-pixels, and B sub-pixels. Therefore, by truncating the display data of each pixel according to the size of the sub-pixel display data (e.g., 8-bit width), R sub-pixel display data, G sub-pixel display data, and B sub-pixel display data can be obtained, and can be labeled as R1, G1, B1, R2, ..., R8, G8, B8, for a total of 24 sub-pixel display data. Figure 6 In the exemplary embodiment shown, each pixel island includes 10 viewpoints. Therefore, in the data labeling stage, a one-to-one mapping relationship can be established between 20 of the 24 sub-pixel display data (i.e., sub-pixel display data R1, G1, B1, R2, ..., R4, R5, ..., R8) and the 20 viewpoint display data of the two pixel islands (i.e., viewpoint display data a-VIEW1, ..., a-VIEW10, b-VIEW1, ..., b-VIEW10) according to the viewpoint numbering order. For the 4 unlabeled sub-pixel display data, they are labeled as dummy viewpoint display data (i.e., DUMMY tags). Therefore, in the data labeling stage, the 24 sub-pixel display data can be labeled according to the viewpoint numbering order so that 20 of the 24 sub-pixel display data correspond one-to-one with the 20 viewpoints of the two pixel islands. Figure 6As shown, it illustrates a label information table (including DUMMY labels for marking dummy viewpoint display data) obtained by labeling 24 sub-pixel display data. This table describes the correspondence between each sub-pixel display data and the corresponding viewpoints within the pixel island. Finally, in the pixel islanding process, the 20 labeled viewpoint display data and 4 dummy viewpoint display data (i.e., the 24 sub-pixel display data and their corresponding label information table) are rearranged according to the actual architecture of the pixel islands. (See diagram for details.) Figure 4 As shown, for example, for each data input channel, the low-order display data and the high-order display data are interchanged. Thus, the rearranged viewpoint display data and the dull viewpoint display data constitute the pixel island display data stream.

[0071] See also Figure 2 In step 230, single-line display data is generated based on the pixel island display data stream. The viewpoint display data included in the single-line display data corresponds one-to-one with the output channels of multiple chips. In this disclosure, the chips can be COF chips (Chip on Film), COG chips (Chip on Glass), or COP chips (Chip on Pi), and this disclosure does not impose any limitations. The chip output channels correspond one-to-one with the data lines of the pixel island array of the display screen. Therefore, the viewpoint display data included in the single-line display data generated in this step actually corresponds to one line of display data applied to the pixel island array of the display screen. Thus, the display data processing method 200 according to this disclosure can realize the driving and normal display of a display device based on a pixel island architecture.

[0072] See Figure 7 According to some exemplary embodiments of this disclosure, it further illustrates Figure 2 This is one embodiment of step 230 in the displayed data processing method 200. For example... Figure 7 As shown, the implementation method 230a of step 230 includes steps 230a-1, 230a-2 and 230a-3.

[0073] In step 230a-1, the pixel island display data stream undergoes data functionalization processing to generate a functionalized pixel island display data stream. Data functionalization primarily targets MUX designs (e.g., MUX1:2 or MUX1:3, or conventional non-MUX designs), multi-chip designs, chip parity / even alternation designs, and display data line routing methods (e.g., using parity / even alternation routing or sequential routing), etc., to decompose and reconstruct the viewpoint display data included in the pixel island display data stream to ensure compatibility with different hardware structures.

[0074] In step 230a-2, the viewpoint display data corresponding to each chip is distinguished from the pixel island display data stream after data functionalization, according to the amount of viewpoint display data corresponding to each chip in the single row display data.

[0075] Because each output channel of the chip corresponds one-to-one with the data lines on the display screen, the amount of data required by each chip in a line of displayed data can be determined from the chip's interface requirements in the interface transmission protocol. See also Figure 14 This schematically illustrates the interface requirements of the chip in the CEDS interface transmission protocol. For example... Figure 14 As shown, each chip has 8 input data channels and 1440 output data channels. Therefore, for the display data processing method according to this disclosure, if 8 chips (e.g., COF chips) are used, the number of viewpoint display data included in a single line of display data corresponding to a line of display data required by the display screen should be 1440 × 8, where the number of viewpoint display data required by each chip is 1440. It should be understood that the interface requirements of the chips in the CEDS interface transmission protocol described in this disclosure are merely exemplary and not limiting; therefore, other interface transmission protocols are also possible, and this disclosure does not limit them.

[0076] In this disclosure Figures 8 to 12 The text shows information about... Figure 7 Some exemplary embodiments of steps 230a-1 and 230a-2 shown are described below.

[0077] See Figure 8 According to some exemplary embodiments of this disclosure, it further illustrates Figure 7 One embodiment of step 230a-1 shown. For example... Figure 8 As shown, implementation 230a-1a of step 230a-1 includes the step of: reorganizing the pixel island display data stream into an odd-numbered chip display data stream and an even-numbered chip display data stream, wherein the odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips. The odd-numbered chip display data stream and the even-numbered chip display data stream together constitute the pixel island display data stream after data functionalization processing. Therefore, the function of implementation 230a-1a is to split and reconstruct the viewpoint display data included in the pixel island display data stream to accommodate the parity of the chip numbering in the chip odd-even alternating design, so as to adapt to the hardware structure including the chip odd-even alternating design.

[0078] See Figure 9 According to some exemplary embodiments of this disclosure, it further illustrates Figure 7 One embodiment of step 230a-2 shown. For example... Figure 9 As shown, implementation 230a-2a of step 230a-2 includes steps 230a-2a-1 and 230a-2a-2. In step 230a-2a-1, viewpoint display data corresponding to each odd-numbered chip among the plurality of chips is distinguished from the odd-numbered chip display data stream according to the amount of viewpoint display data corresponding to each chip in the single-row display data. In step 230a-2a-2, viewpoint display data corresponding to each even-numbered chip among the plurality of chips is distinguished from the even-numbered chip display data stream according to the amount of viewpoint display data corresponding to each chip in the single-row display data. Therefore, Figure 9 The embodiments 230a-2a shown are actually... Figure 8 The subsequent processing of the odd-numbered chip display data stream and the even-numbered chip display data stream obtained in the embodiments 230a-1a shown is that the viewpoint display data of each chip is distinguished from the odd-numbered chip display data stream and the even-numbered chip display data stream.

[0079] See Figure 10 According to some exemplary embodiments of this disclosure, it further illustrates Figure 7 Another implementation of step 230a-1 shown. For example... Figure 10As shown, implementation 230a-1b of step 230a-1 includes steps 230a-1b-1, 230a-1b-2, and 230a-1b-3. In step 230a-1b-1, the pixel island display data stream is reorganized into an odd-numbered chip display data stream and an even-numbered chip display data stream. The odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips. This step is essentially the same as step 230a-1a described above. In step 230a-1b-2, the odd-numbered chip display data stream is reorganized into an odd-numbered chip multiplexed display data stream with the same number of multiplexed groups as the pixel island. Each odd-numbered chip multiplexed display data stream is used to provide viewpoint display data to an odd-numbered chip corresponding to a specific multiplexed group. In step 230a-1b-3, the even-numbered chip display data stream is reorganized into an even-numbered chip multiplexed display data stream with the same number of multiplexing groups as the pixel island. Each even-numbered chip multiplexed display data stream provides viewpoint display data to a chip with an even-numbered chip corresponding to a specific multiplexing group. The odd-numbered chip multiplexed display data stream and the even-numbered chip multiplexed display data stream together constitute the pixel island display data stream after data functionalization. Therefore, the purpose of implementation 230a-1b is to split and reconstruct the viewpoint display data included in the pixel island display data stream, taking into account the parity of chip numbering in an alternating chip design and the MUX design of the display screen, so as to adapt to hardware structures including alternating chip design and MUX design.

[0080] See Figure 11 According to some exemplary embodiments of this disclosure, it further illustrates Figure 7 Another implementation of step 230a-2 shown. For example... Figure 11 As shown, implementation 230a-2b of step 230a-2 includes steps 230a-2b-1 and 230a-2b-2. In step 230a-2b-1, viewpoint display data for each odd-numbered chip is distinguished from the multiplexed display data stream of all odd-numbered chips according to the amount of viewpoint display data corresponding to each chip in the single-line display data. In step 230a-2b-2, viewpoint display data for each even-numbered chip is distinguished from the multiplexed display data stream of all even-numbered chips according to the amount of viewpoint display data corresponding to each chip in the single-line display data. Therefore, Figure 11 The embodiments 230a-2b shown are actually... Figure 10The subsequent processing of the odd-numbered chip multiplexed display data stream and the even-numbered chip multiplexed display data stream obtained in the embodiments 230a-1b shown is that the viewpoint display data of each chip is distinguished from the odd-numbered chip multiplexed display data stream and the even-numbered chip multiplexed display data stream.

[0081] See Figure 12 According to some exemplary embodiments of this disclosure, it further illustrates Figure 7 Another implementation of step 230a-1 shown. For example... Figure 12 As shown, implementation 230a-1c of step 230a-1 includes the step of: recombining the pixel island display data stream into a number of multiplexed display data streams equal to the number of multiplexed groups of the pixel island, wherein one multiplexed display data stream provides viewpoint display data for the pixel islands included in a corresponding multiplexed group. Therefore, Figure 12 The illustrated implementations 230a-1c function to split and reconstruct the viewpoint display data included in the pixel island display data stream for the MUX design of the display screen, thereby adapting to, for example, the MUX design of the display screen. Accordingly, the viewpoint display data provided to each chip can be distinguished from all multiplexed display data streams according to the amount of viewpoint display data corresponding to each chip in the single row of display data.

[0082] Return to continue reading Figure 7 In step 230a-3, according to the numbering order of the plurality of chips, the viewpoint display data corresponding to each chip is sequentially reorganized according to the order of the chip input ports to generate the single-line display data. (See also...) Figure 14 and Figure 15 ,in, Figure 14 The diagram schematically illustrates the interface requirements of the chip in the CEDS interface transmission protocol. Figure 15 It schematically shows the following based on Figure 14 The interface of the chip shown requires a method for reconstructing viewpoint display data. For example... Figure 14 As shown, each chip has 8 input data channels (CED0A / B to CED7A / B) and 1440 output data channels (Y1 to Y1440). Data from input data channels CED0A / B and CED1A / B is transmitted to output data channels Y1 to Y360; data from input data channels CED2A / B and CED3A / B is transmitted to output data channels Y361 to Y720; data from input data channels CED4A / B and CED5A / B is transmitted to output data channels Y721 to Y1080; and data from input data channels CED6A / B and CED7A / B is transmitted to output data channels Y1081 to Y1440. According to... Figure 14The interface requirements of the chips shown require that the viewpoint display data corresponding to each chip need to be reassembled according to the output data channel. Accordingly, Figure 15 An assembly method is illustrated, in which the viewpoint display data corresponding to each chip is reassembled into eight port data streams, Port1 to Port8. Port data streams Port1 and Port2 transmit viewpoint display data for channels 1-360; Port data streams Port3 and Port4 transmit viewpoint display data for channels 361-720; Port data streams Port5 and Port6 transmit viewpoint display data for channels 721-1080; and Port data streams Port7 and Port8 transmit viewpoint display data for channels 1081-1440. The viewpoint display data corresponding to each chip, reassembled according to the order of the chip input ports, constitutes a single line of display data, corresponding to one line of display data provided to the display screen.

[0083] See Figure 13 According to some exemplary embodiments of this disclosure, it schematically illustrates a data functionalization process for a pixel display data stream. For example... Figure 13As shown, the data functionalization process 230' performs data functionalization processing on the pixel island display data stream for a hardware structure including the COF chip parity alternation design and the MUX1:2 design. In the viewpoint display data receiving stage, viewpoint display data is received from the eight viewpoint display data input channels view-in1 to view-in8 during one effective clock pulse de. Then, in the MUX processing and chip parity processing stages, based on the parity of the MUX1:2 design and the COF chip numbering, the viewpoint display data is reorganized from the 8 viewpoint display data input channels view-in1 to view-in8 into 4 processed viewpoint display data channels, namely mux1-odd, mux2-odd, mux1-even, and mux2-even. Among them, the processed viewpoint display data channel mux1-odd provides viewpoint display data for the MUX1 multiplexed group of odd-numbered chips, the processed viewpoint display data channel mux2-odd provides viewpoint display data for the MUX2 multiplexed group of odd-numbered chips, the processed viewpoint display data channel mux1-even provides viewpoint display data for the MUX1 multiplexed group of even-numbered chips, and the processed viewpoint display data channel mux2-even provides viewpoint display data for the MUX2 multiplexed group of even-numbered chips. It should be understood that compared to the eight viewpoint display data input channels view-in1 to view-in8, the amount of viewpoint display data provided by each of the four processed viewpoint display data channels mux1-odd, mux2-odd, mux1-even, and mux2-even in one effective clock pulse de is doubled. For example, if the amount of viewpoint display data provided by each of the eight viewpoint display data input channels view-in1 to view-in8 in one effective clock pulse de is 24 bits, then the amount of viewpoint display data provided by each of the four processed viewpoint display data channels mux1-odd, mux2-odd, mux1-even, and mux2-even in one effective clock pulse de is 48 bits. In the process of determining the viewpoint display data of the chip, as described above, the viewpoint display data corresponding to each chip (e.g., chips COF1 to COF8) can be distinguished from the pixel island display data stream after data functionalization based on the amount of viewpoint display data corresponding to each chip in the single row of display data. For example, viewpoint display data for chips COF1, COF3, COF5, and COF7 with odd numbers can be distinguished from the processed viewpoint display data channels mux1-odd and mux2-odd, and viewpoint display data for chips COF2, COF4, COF6, and COF8 with even numbers can be distinguished from the processed viewpoint display data channels mux1-even and mux2-even.In the viewpoint display data output stage, according to the chip interface requirements in the CEDS interface transmission protocol, the viewpoint display data of chips COF1 to COF8 are reassembled in the order of the chip input ports to generate the single-line display data. For example, the viewpoint display data of each chip are reassembled into chip port data streams ic-port1 to ic-port8 respectively. For details regarding chip port data streams ic-port1 to ic-port8, please refer to the previous section. Figure 14 and Figure 15 The description of the process will not be repeated here. Therefore, the viewpoint display data corresponding to each chip, after being reorganized according to the order of the chip input ports, constitutes a single line of display data, which corresponds to a line of display data provided to the display screen.

[0084] See Figure 16 According to some exemplary embodiments of this disclosure, it further illustrates Figure 2 Another embodiment of step 230 of the display data processing method 200 shown. For example... Figure 16 As shown, implementation 230b of step 230 includes steps 230b-1 and 230b-2. In step 230b-1, viewpoint display data corresponding to each chip is distinguished from the pixel island display data stream according to the amount of viewpoint display data corresponding to each chip in the single-row display data. Step 230b-2 is the same as steps 230a-3 described above, and will not be repeated here. It should be understood that... Figure 16 The embodiment 230b shown is for a situation where there is no need to perform data functionalization processing on the pixel display data stream. Therefore, it is only necessary to directly distinguish the viewpoint display data corresponding to each chip from the pixel display data stream.

[0085] Furthermore, it should be understood that, for example... Figure 5 and Figure 6 In the exemplary embodiment shown, since there is a case where sub-pixel display data is marked as dull point display data during the process of converting the pixel display data stream into a pixel island display data stream, therefore, for data including dull point display data, Figure 2 Step 230 in the display data processing method 200 shown can also be implemented as follows: removing the dull point display data from the pixel island display data stream; and generating the single-line display data based on the pixel island display data stream after removing the dull point display data.

[0086] See Figure 17 This illustrates, in flowchart form, another method for displaying data processing according to some exemplary embodiments of this disclosure. For example... Figure 17As shown, the display data processing method 200' includes steps 210, 220, 230, and 240. Steps 210, 220, and 230 are the same as the corresponding steps in the display data processing method 200 described in detail above, and will not be repeated here. In step 240, when the bit width of the viewpoint display data is smaller than the bit width of the display screen display data, the viewpoint display data is compensated based on the difference between the two. The display data processing method 200' is applicable to the following situation: the color depth of a display device based on a pixel island architecture does not match that of a general display device. For example, the front-end image data on existing host computers is generally 8 bits wide, while display devices based on a pixel island architecture are usually designed with a high contrast of 10 bits color depth. Therefore, it is necessary to compensate the 8-bit wide viewpoint display data to a 10-bit wide bit width to achieve color depth matching. In the display data processing method 200', data compensation is performed based on the difference in color depth values ​​between the two to achieve color depth matching.

[0087] See also Figure 18 This schematically illustrates a compensation process for compensating for viewpoint display data. For example... Figure 18 As shown, in the compensation process 240', the input is 8-bit wide viewpoint display data VIEW1, which includes 8 bit values ​​VIEW1[0] to VIEW1[7] from bits 0 to 7. The output is 10-bit wide viewpoint display data, in which 8 bit values ​​VIEW1[7] to VIEW1[0] are written sequentially from the high bit to the low bit of the 10-bit wide data. The remaining two bits, bit1 and bit0, can have a value of 0. Thus, the compensated 10-bit wide viewpoint display data is obtained. It should be understood that... Figure 18 The compensation process 240' shown essentially shifts the 8-bit wide viewpoint display data to the higher bits, and if the shift number is 'a', it is equivalent to multiplying the 8-bit wide viewpoint display data by 2. a , where a is an integer greater than 0. It should be understood that other suitable compensation methods are also possible, and this disclosure does not limit them.

[0088] See Figure 19 This illustrates, in flowchart form, another method for displaying data processing according to some exemplary embodiments of this disclosure. For example... Figure 19As shown, the display data processing method 200" includes steps 210, 220, 230, 240, and 250. Steps 210, 220, and 230 are the same as the corresponding steps in the previously described display data processing method 200, and step 240 is the same as the corresponding steps in the previously described display data processing method 200'. Therefore, these steps will not be described again here. In step 250, the single-line display data is cached; in response to the received line scan signal, the single-line display data is output. Normal display of the image requires the matching output of the line scan signal (e.g., GOA signal) and the display data signal. Therefore, the processed single-line display data can be cached in RAM memory / storage areas first, and then the single-line display data can be output according to the received line scan signal and the timing signal, thereby ensuring that the output single-line display data matches the timing of the line scan signal. In an exemplary embodiment, the processed single-line display data can be cached in different RAM memory / storage areas, for example, in conjunction with the above. Figure 15 Data in port data streams Port1 and Port2 can be stored in a first RAM memory / storage area, data in port data streams Port3 and Port4 can be stored in a second RAM memory / storage area, data in port data streams Port5 and Port6 can be stored in a third RAM memory / storage area, and data in port data streams Port7 and Port8 can be stored in a fourth RAM memory / storage area. However, any other suitable caching method is possible, and this disclosure does not limit the specific caching method.

[0089] See Figure 20 This schematically illustrates an access process for caching and retrieving single-line display data. For example... Figure 20 As shown, in access process 250', in response to clock counting, the generated single-line display data can be stored in RAM memory / storage area, which is a caching process for single-line display data; in read process, in response to the GOA row scan signal received from GOA circuit, a single-line display data is read from RAM memory / storage area and the single-line display data is output to achieve output matching of GOA timing signal.

[0090] See Figure 21a The diagram schematically illustrates a display data processing apparatus according to some exemplary embodiments of the present disclosure. The display data processing apparatus 300 can apply various display data processing methods described in this disclosure. For example... Figure 21aAs shown, the display data processing device 300 includes: a pixel display data stream receiving module 310, a display data stream conversion module 320, and a single-line display data generation module 330. The pixel display data stream receiving module 310 is configured to receive a pixel display data stream, wherein the pixel display data stream includes multiple sub-pixel display data corresponding to each pixel. The display data stream conversion module 320 is configured to convert the pixel display data stream into a pixel island display data stream, wherein the pixel island display data stream includes multiple viewpoint display data corresponding to each pixel island. The single-line display data generation module 330 is configured to generate single-line display data based on the pixel island display data stream, wherein the viewpoint display data included in the single-line display data corresponds one-to-one with the output channels of multiple chips. The above modules relate to the concepts discussed above. Figure 2 The operations described in steps 210 to 250 will not be repeated here.

[0091] See Figures 21b to 21d The diagram schematically illustrates other display data processing apparatuses according to some exemplary embodiments of the present disclosure. For example... Figure 21b As shown, the display data processing device 300a, in addition to modules 310, 320, and 330, also includes a display data compensation module 340. The display data compensation module 340 is configured to compensate the viewpoint display data based on the difference when the bit width of the viewpoint display data included in the single-line display data is less than the bit width of the display screen display data. In a non-limiting embodiment, when the difference between the bit width of the viewpoint display data included in the single-line display data and the bit width of the display screen display data is 'a', the difference is calculated by multiplying the viewpoint display data by 2. a To perform compensation, where 'a' is an integer greater than 0. The data compensation module 340 relates to the above-mentioned... Figure 17 The operation of step 240, as described, will not be repeated here. Figure 21c As shown, the display data processing device 300b, in addition to modules 310, 320, and 330, also includes a display data access module 350. The display data access module 350 is configured to: buffer the single-line display data; and, in response to a received power signal, output the single-line display data. The display data access module 350 relates to the information described above regarding... Figure 19 The operation of step 250, as described, will not be repeated here. Figure 21dAs shown, the display data processing apparatus 300c, in addition to modules 310, 320, and 330, also includes an image arrangement module 360. The image arrangement module 360 ​​is configured to determine the arrangement of pixel display data corresponding to each pixel of the image to be displayed. It should be understood that, in addition to modules 310, 320, and 330, the display data processing apparatus according to this disclosure may include any one or any combination of the display data compensation module 340, the display data access module 350, and the image arrangement module 360, and the resulting display data processing apparatus falls within the scope of this disclosure.

[0092] The above about Figures 21a to 21d Each module of the described display data processing apparatus 300, 300a, 300b, 300c can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer-executable code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuit. For example, in some exemplary embodiments, these modules can all be implemented using a field-programmable gate array (i.e., FPGA). Furthermore, in other exemplary embodiments, one or more of these modules can be implemented together in a system-on-a-chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a central processing unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or one or more components of other circuitry) and may optionally execute received program code and / or include embedded firmware to perform functions.

[0093] See Figure 22 The diagram schematically illustrates, in block form, a display device based on a multi-viewpoint pixel island architecture according to some exemplary embodiments of the present disclosure. Figure 22 As shown, the display device 500 based on a multi-view pixel island architecture includes a display data processing unit 510. The display data processing unit 510 can be implemented as described above regarding... Figures 21a to 21d The described display data processing apparatus 300, 300a, 300b, 300c or any combination of the modules included therein.

[0094] The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and “including,” when used in this disclosure, refer to the presence of the mentioned feature but do not exclude the presence of one or more other features or the addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various features, these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0095] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It shall also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0096] In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example that is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] This paper describes various techniques within the general context of software and hardware components or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. As used herein, the terms "module," "function," and "component" generally refer to software, firmware, hardware, or a combination thereof. The techniques described herein are characterized as platform-independent, meaning that these techniques can be implemented on a variety of computing platforms with various processors.

[0098] The logic and / or steps illustrated in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). Furthermore, it should be understood that the various steps of the methods illustrated in the flowcharts or otherwise described herein are merely exemplary and do not imply that the steps of the illustrated or described methods must be performed in accordance with the steps shown or described. Rather, the various steps of the methods illustrated in the flowcharts or otherwise described herein may be performed in a different order than that shown in this disclosure, or may be performed simultaneously. Additionally, the methods illustrated in the flowcharts or otherwise described herein may include other additional steps as needed.

[0099] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0100] Those skilled in the art will understand that all or part of the steps of the methods described in the above specific embodiments can be implemented by hardware related to program instructions. The program can be stored in a computer-readable storage medium, and when executed, the program includes performing one of the steps of the method embodiments or any combination thereof.

[0101] Although this disclosure has been described in detail with reference to some exemplary embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of this disclosure is defined only by the appended claims.

Claims

1. A method for processing display data, comprising: Receive pixel display data stream, wherein the pixel display data stream includes multiple sub-pixel display data corresponding to each pixel; The pixel display data stream is converted into a pixel island display data stream, wherein the pixel island display data stream includes multiple viewpoint display data corresponding to each pixel island; Based on the pixel island display data stream, single-line display data is generated, wherein the viewpoint display data included in the single-line display data corresponds one-to-one with the output channels of multiple chips; The step of generating single-line display data based on the pixel island display data stream includes: The pixel island display data stream is subjected to data functionalization processing to generate a pixel island display data stream after data functionalization processing; Based on the amount of viewpoint display data corresponding to each chip in the single-row display data, the viewpoint display data corresponding to each chip is distinguished from the pixel island display data stream after data functionalization. According to the numbering order of the multiple chips, the viewpoint display data corresponding to each chip is reorganized in the order of the chip input ports to generate the single-line display data.

2. The display data processing method according to claim 1, wherein, The steps of converting the pixel display data stream into a pixel island display data stream include: Obtain i×k sub-pixel display data corresponding to i pixels from the pixel display data stream, where i and k are both integers greater than 0; Mark the m×n sub-pixel display data in the i×k sub-pixel display data as viewpoint display data corresponding to the m×n viewpoints of the m pixel islands, where m and n are both integers greater than 0, and m×n = i×k; Based on the architecture of the pixel islands, the viewpoint display data is rearranged to convert the pixel display data stream into the pixel island display data stream.

3. The display data processing method according to claim 1, wherein, The steps of converting the pixel display data stream into a pixel island display data stream include: Obtain i×k sub-pixel display data corresponding to i pixels from the pixel display data stream, where i and k are both integers greater than 0; Mark the m×n sub-pixel display data in the i×k sub-pixel display data as the viewpoint display data corresponding to the m×n viewpoints of the m pixel islands, where m and n are both integers greater than 0, and m×n < i×k; Mark the sub-pixel display data that are not marked as viewpoint display data among the i×k sub-pixel display data as dumb viewpoint display data; Based on the architecture of the pixel island, the viewpoint display data and the dumb viewpoint display data are rearranged together to convert the pixel display data stream into the pixel island display data stream.

4. The display data processing method according to claim 1, wherein, The steps of performing data functionalization processing on the pixel island display data stream to generate a functionalized pixel island display data stream include: The pixel island display data stream is reorganized into an odd-numbered chip display data stream and an even-numbered chip display data stream, wherein the odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips; The odd-numbered chip display data stream and the even-numbered chip display data stream together constitute the pixel island display data stream after data functionalization processing.

5. The display data processing method according to claim 4, wherein, The steps of distinguishing the viewpoint display data corresponding to each chip from the pixel island display data stream after data functionalization, based on the amount of viewpoint display data corresponding to each chip in the single-line display data, include: Based on the amount of viewpoint display data corresponding to each chip in the single-line display data, the viewpoint display data corresponding to each chip with an odd number among the multiple chips is distinguished from the display data stream of the odd-numbered chips; Based on the amount of viewpoint display data corresponding to each chip in the single-line display data, the viewpoint display data corresponding to each chip with an even number among the multiple chips is distinguished from the even-numbered chip display data stream.

6. The display data processing method according to claim 1, wherein, The steps of performing data functionalization processing on the pixel island display data stream to generate a functionalized pixel island display data stream include: The pixel island display data stream is reorganized into an odd-numbered chip display data stream and an even-numbered chip display data stream, wherein the odd-numbered chip display data stream is used to provide viewpoint display data to odd-numbered chips, and the even-numbered chip display data stream is used to provide viewpoint display data to even-numbered chips; The odd-numbered chip display data stream is reorganized into an odd-numbered chip multiplexed display data stream with the same number of multiplexed groups as the pixel island, wherein an odd-numbered chip multiplexed display data stream is used to provide viewpoint display data to an odd-numbered chip corresponding to a corresponding multiplexed group; The even-numbered chip display data stream is reorganized into an even-numbered chip multiplexed display data stream with the same number of multiplexed groups as the pixel island. One even-numbered chip multiplexed display data stream is used to provide viewpoint display data to an even-numbered chip corresponding to a corresponding multiplexed group. Among them, all the odd-numbered chip multiplexed display data streams and all the even-numbered chip multiplexed display data streams together constitute the pixel island display data stream after data functionalization processing.

7. The display data processing method according to claim 6, wherein, The steps of distinguishing the viewpoint display data corresponding to each chip from the pixel island display data stream after data functionalization, based on the amount of viewpoint display data corresponding to each chip in the single-line display data, include: Based on the amount of viewpoint display data corresponding to each chip in the single-line display data, viewpoint display data is distinguished from all the multiplexed display data streams of odd-numbered chips and provided to each chip with an odd number among the multiple chips. Based on the amount of viewpoint display data corresponding to each chip in the single-line display data, viewpoint display data is distinguished from the multiplexed display data streams of all even-numbered chips and provided to each chip with an even number among the multiple chips.

8. The display data processing method according to claim 1, wherein, The steps of performing data functionalization processing on the pixel island display data stream to generate a functionalized pixel island display data stream include: The pixel island display data stream is recombined into a number of multiplexed display data streams that are the same as the number of multiplexed groups of the pixel island, wherein one multiplexed display data stream provides viewpoint display data for the pixel islands included in a corresponding multiplexed group; All the multiplexed display data streams constitute the pixel island display data stream after the data functionalization process.

9. The display data processing method according to claim 3, wherein, The steps for generating single-line display data based on the pixel island display data stream include: Remove the matte display data from the pixel island display data stream; The single-line display data is generated based on the pixel island display data stream after removing the dull viewpoint display data.

10. The display data processing method according to claim 1, further comprising: When the bit width of the viewpoint display data included in the single-line display data is smaller than the bit width of the display screen display data, the viewpoint display data is compensated based on the difference between the two.

11. The display data processing method according to claim 10, wherein, When the bit width of the viewpoint display data included in the single-line display data is smaller than the bit width of the display screen display data, the step of compensating for the viewpoint display data based on the difference between the two includes: When the difference between the bit width of the viewpoint display data included in the single-line display data and the bit width of the display screen data is 'a' bits, the viewpoint display data is multiplied by 2. a To compensate, where a is an integer greater than 0.

12. The display data processing method according to claim 1, further comprising: The single-line display data is cached; In response to the received power signal, the single-line display data is output.

13. A display data processing apparatus, comprising: A pixel display data stream receiving module is configured to receive a pixel display data stream, wherein the pixel display data stream includes multiple sub-pixel display data corresponding to each pixel; The display data stream conversion module is configured to convert the pixel display data stream into a pixel island display data stream, wherein the pixel island display data stream includes multiple viewpoint display data corresponding to each pixel island; A single-line display data generation module is configured to: generate single-line display data based on the pixel island display data stream, wherein the single-line display data includes viewpoint display data that corresponds one-to-one with the output channels of multiple chips; wherein generating single-line display data based on the pixel island display data stream includes: performing data functionalization processing on the pixel island display data stream to generate a data functionalized pixel island display data stream; distinguishing the viewpoint display data corresponding to each chip from the data functionalized pixel island display data stream according to the amount of viewpoint display data corresponding to each chip in the single-line display data; and sequentially reorganizing the viewpoint display data corresponding to each chip according to the chip input port order according to the chip numbering order to generate the single-line display data.

14. The display data processing apparatus according to claim 13, further comprising: The display data compensation module is configured to compensate the viewpoint display data based on the difference when the bit width of the viewpoint display data included in the single-line display data is smaller than the bit width of the display screen display data.

15. The display data processing apparatus according to claim 13, further comprising: The display data access module is configured to cache the single-line display data. In addition, in response to the received power signal, the single-line display data is output.

16. The display data processing apparatus according to claim 13, further comprising: The image arrangement module is configured to determine the arrangement of pixel display data corresponding to each pixel of the image to be displayed.

17. The display data processing apparatus according to any one of claims 13 to 16, wherein, The display data processing device is implemented based on an FPGA.

18. A display device based on a multi-viewpoint pixel island architecture, wherein, The display device based on the multi-view pixel island architecture includes a display data processing device according to any one of claims 13 to 17.

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