Gate drive circuit

Abstract

A gate driving circuit is provided. The gate driving circuit includes a plurality of output circuits and a noise resistance circuit. An Nth stage output circuit among the plurality of output circuits includes a pre-charge circuit, a coupling circuit, and an output transistor. The pre-charge circuit pre-charges a low bias value of a bias node of the Nth stage output circuit to a first bias value. The coupling circuit raises the first bias value of the bias node to a second bias value. The output transistor raises the second bias value of the bias node to a third bias value in response to the bias value of the bias node to output an Nth stage clock signal as an Nth stage gate driving signal. The noise resistance circuit performs a noise resistance operation on the plurality of output circuits after a bias value of a bias node of a last stage output circuit among the plurality of output circuits is pulled down to a low bias value.

Description

Technical Field

[0001] This invention relates to a gate drive circuit, and more particularly to a gate drive circuit having a low layout area and suitable for low-temperature environments. Background Technology

[0002] Currently, the design of display panels for electronic devices is gradually moving towards narrow bezels. From a design perspective, reducing the number of components (such as transistors) in the gate drive circuit of the display panel and minimizing the distance between components are the main design goals.

[0003] Generally, reducing the distance between components increases the risk of interference from neighboring components, thus generating noise. Therefore, noise suppression circuitry in the gate drive circuitry is necessary. However, noise suppression circuitry increases the layout area.

[0004] Furthermore, gate drive circuits based on amorphous silicon thin-film transistors exhibit low electron mobility, resulting in poor driving capability at low temperatures. Therefore, further reducing the layout area of ​​gate drive circuits with noise suppression circuitry and improving their driving capability at low temperatures is a key research focus for those skilled in the art. Summary of the Invention

[0005] This invention provides a gate drive circuit with a low layout area that can have high driving capability in low temperature environments.

[0006] The gate drive circuit of the present invention includes multiple output circuits and a noise suppression circuit. The multiple output circuits each provide different gate drive signals. The Nth stage output circuit includes a pre-charge circuit, a coupling circuit, and an output transistor. The pre-charge circuit pre-charges the low bias value of the bias node of the Nth stage output circuit to a first bias value. N is a positive integer. The coupling circuit is coupled to the bias node. The coupling circuit responds to the (N-1)th stage gate drive signal via capacitive coupling to raise the first bias value of the bias node to a second bias value. The output transistor is coupled to the bias node. The output transistor responds to the bias value of the bias node to use the Nth stage clock signal as the Nth stage gate drive signal, and responds to the positive pulse of the Nth stage clock signal to raise the second bias value of the bias node to a third bias value. The noise suppression circuit is coupled to the multiple output circuits. After the bias value of the last stage output circuit in the multiple output circuits is pulled down to a low bias value, the noise reduction circuit pulls down the bias values ​​of the multiple gate drive signals and the bias values ​​of the multiple output circuits to a low reference voltage value.

[0007] Based on the above, the gate driving circuit of the present invention includes multiple output circuits and a noise suppression circuit. The noise suppression circuit performs noise suppression operation on the multiple output circuits. Therefore, the layout area of ​​the gate driving circuit can be significantly reduced. Furthermore, the bias values ​​at the bias nodes of each of the multiple output circuits are increased in three stages. Therefore, the driving capability of the gate driving circuit in low-temperature environments can be improved.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention.

[0011] Figure 3 This is a schematic diagram of an anti-noise control circuit according to an embodiment of the present invention.

[0012] Figure 4 This is a signal timing diagram according to an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures

[0014] 100, 200: Gate drive circuit

[0015] 110(N)~110(N+3), 210(N)~210(N+3): Output circuit

[0016] 111(N)~111(N+3), 211(N)~211(N+3): Pre-charge circuit

[0017] 112(N)~112(N+3), 212(N)~212(N+3): Coupled circuit

[0018] 120, 220: Noise suppression circuit

[0019] 230: Noise suppression control circuit

[0020] A(N)~A(N+3): Reference nodes

[0021] C1~C4: Coupling capacitors

[0022] CLK(N-2): The (N-2)th level clock signal

[0023] CLK(N-1): The (N-1)th level clock signal

[0024] CLK(N): Nth level clock signal

[0025] CLK(N+1): The (N+1)th level clock signal

[0026] CLK(N+2): The (N+2)th level clock signal

[0027] CLK(N+3): The (N+3)th level clock signal

[0028] CLK(N+4): The (N+4)th level clock signal

[0029] CLK(N+5): The (N+5)th level clock signal

[0030] G(N-2): Gate drive signal of the (N-2)th stage

[0031] G(N-1): Gate drive signal of the (N-1)th stage

[0032] G(N): Gate drive signal of the Nth stage

[0033] G(N+1): Gate drive signal of the (N+1)th stage

[0034] G(N+2): Gate drive signal of the (N+2)th stage

[0035] G(N+3): Gate drive signal of the (N+3)th stage

[0036] G(N+5): Gate drive signal of the (N+5)th stage

[0037] G(N+6): Gate drive signal of the (N+6)th stage

[0038] G(N+7): Gate drive signal of the (N+7)th stage

[0039] M1, M1a, M1b, M1c: Precharge transistors

[0040] M2, M2a, M2b, M2c, M3, M3a, M3b, M3c: Bridge transistors

[0041] M4, M4a, M4b, M4c: Pull-down transistors

[0042] M5~M7, M5a~M7a, M5b~M8b, M5c~M7c: Transistors

[0043] MC1~MC6: Control transistors

[0044] MO, MOa, MOb, MOc, MO(N), MO(N+1), MO(N+2), MO(N+3): output transistor

[0045] Q(N)~Q(N+3): Bias nodes

[0046] SN1: First noise reduction control signal

[0047] SN2: Second noise reduction control signal

[0048] T1~T11: Time interval

[0049] VDD: High reference voltage

[0050] VSS: Low reference voltage Detailed Implementation

[0051] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0052] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit 100 may be at least a portion of a gate driving device. The gate driving circuit 100 may be a single gate driving unit. The gate driving circuit 100 includes output circuits 110(N) to 110(N+3) and noise suppression circuit 120. The output circuits 110(N) to 110(N+3) each provide different gate driving signals. For example, output circuit 110(N) provides an Nth-level gate driving signal G(N). Output circuit 110(N+1) provides an (N+1)th-level gate driving signal G(N+1). Output circuit 110(N+2) provides an (N+2)th-level gate driving signal G(N+2). Output circuit 110(N+3) provides an (N+3)th-level gate driving signal G(N+3). In this embodiment, the output circuits 110(N) to 110(N+3) are connected in series. Output circuit 110(N) can be considered as the first stage output circuit of gate drive circuit 100. Output circuit 110(N+1) can be considered as the second stage output circuit of gate drive circuit 100. Output circuit 110(N+2) can be considered as the third stage output circuit of gate drive circuit 100. Output circuit 110(N+3) can be considered as the last stage output circuit of gate drive circuit 100.

[0053] In this embodiment, the output circuit 110(N) includes a pre-charge circuit 111(N), a coupling circuit 112(N), and an output transistor MO(N). The pre-charge circuit 111(N) pre-charges the low bias value of the bias node Q(N) of the output circuit 110(N) to a first bias value. N is a positive integer. The coupling circuit 112(N) is coupled to the bias node Q(N). The coupling circuit 112(N) responds to the (N-1)th stage gate drive signal G(N-1) via capacitive coupling to raise the first bias value of the bias node Q(N) to a second bias value. The output transistor MO(N) is coupled to the bias node Q(N). The output transistor MO(N) responds to the bias value of the bias node Q(N) to use the Nth level clock signal CLK(N) as the Nth level gate drive signal G(N), and responds to the positive pulse of the Nth level clock signal CLK(N) to raise the second bias value of the bias node Q(N) to the third bias value.

[0054] The output circuit 110(N+1) includes a pre-charge circuit 111(N+1), a coupling circuit 112(N+1), and an output transistor MO(N+1). The pre-charge circuit 111(N+1) pre-charges the low bias value of the bias node Q(N+1) of the output circuit 110(N+1) to a first bias value. The coupling circuit 112(N+1) is coupled to the bias node Q(N+1). The coupling circuit 112(N+1) responds to the Nth-stage gate drive signal G(N) via capacitive coupling to raise the first bias value of the bias node Q(N+1) to a second bias value. The output transistor MO(N+1) is coupled to the bias node Q(N+1). The output transistor MO(N+1) responds to the bias value of the bias node Q(N+1) to use the (N+1)th stage clock signal CLK(N+1) as the (N+1)th stage gate drive signal G(N+1), and responds to the positive pulse of the (N+1)th stage clock signal CLK(N+1) to raise the second bias value of the bias node Q(N+1) to the third bias value.

[0055] The output circuit 110(N+2) includes a pre-charge circuit 111(N+2), a coupling circuit 112(N+2), and an output transistor MO(N+2). The pre-charge circuit 111(N+2) pre-charges the low bias value of the bias node Q(N+2) of the output circuit 110(N+2) to a first bias value. The coupling circuit 112(N+2) is coupled to the bias node Q(N+2). The coupling circuit 112(N+2) responds to the (N+1)th stage gate drive signal G(N+1) via capacitive coupling to raise the first bias value of the bias node Q(N+2) to a second bias value. The output transistor MO(N+2) is coupled to the bias node Q(N+2). The output transistor MO(N+2) responds to the bias value of the bias node Q(N+2) to use the (N+2)th stage clock signal CLK(N+2) as the (N+2)th stage gate drive signal G(N+2), and responds to the positive pulse of the (N+2)th stage clock signal CLK(N+2) to raise the second bias value of the bias node Q(N+2) to the third bias value.

[0056] The output circuit 110(N+3) includes a pre-charge circuit 111(N+3), a coupling circuit 112(N+3), and an output transistor MO(N+3). The pre-charge circuit 111(N+3) pre-charges the low bias value of the bias node Q(N+3) of the output circuit 110(N+3) to a first bias value. The coupling circuit 112(N+3) is coupled to the bias node Q(N+3). The coupling circuit 112(N+3) responds to the (N+2)th stage gate drive signal G(N+2) via capacitive coupling to raise the first bias value of the bias node Q(N+3) to a second bias value. The output transistor MO(N+3) is coupled to the bias node Q(N+3). The output transistor MO(N+3) responds to the bias value of the bias node Q(N+3) to use the (N+3)th stage clock signal CLK(N+3) as the (N+3)th stage gate drive signal G(N+3), and responds to the positive pulse of the (N+3)th stage clock signal CLK(N+3) to raise the second bias value of the bias node Q(N+3) to the third bias value.

[0057] In this embodiment, the noise suppression circuit 120 is coupled to the output circuits 110(N) to 110(N+3). After the bias value of the bias node of the last stage output circuit (i.e., output circuit 110(N+3)) in the output circuits 110(N) to 110(N+3) is pulled down to a low bias value, the noise suppression circuit 120 pulls down the bias values ​​of the Nth stage gate drive signal G(N), the (N+1)th stage gate drive signal G(N+1), the (N+2)th stage gate drive signal G(N+2), the (N+3)th stage gate drive signal G(N+3), and the bias nodes Q(N) to Q(N+3) of the output circuits 110(N) to 110(N+3) to the low reference voltage VSS.

[0058] It is worth mentioning that the gate drive circuit 100 includes output circuits 110(N) to 110(N+3) and a noise suppression circuit 120. The noise suppression circuit 120 performs noise suppression operation on the output circuits 110(N) to 110(N+3). The output circuits 110(N) to 110(N+3) can share a single noise suppression circuit 120. Therefore, the layout area of ​​the gate drive circuit 100 can be significantly reduced. Furthermore, taking the output circuit 110(N) as an example, the precharge circuit 111(N) precharges the low bias value of the bias node Q(N) to a first bias value. The coupling circuit 112(N) raises the first bias value of the bias node Q(N) to a second bias value. The output transistor MO(N) uses the Nth stage clock signal CLK(N) to raise the second bias value of the bias node Q(N) to a third bias value. In other words, the bias value of the bias node Q(N) is raised in three stages. In this way, the driving capability of the gate drive circuit 100 in low-temperature environments can be improved.

[0059] Taking output circuit 110(N) as an example, the first terminal of output transistor MO(N) receives the Nth-stage clock signal CLK(N). The second terminal of output transistor MO(N) outputs the Nth-stage gate drive signal G(N). The control terminal of output transistor MO(N) is coupled to the bias node Q(N). There is a parasitic capacitance between the control terminal and the second terminal of output transistor MO(N). Output transistor MO(N) uses the parasitic capacitance and the positive pulse of the Nth-stage clock signal CLK(N) to raise the bias node Q(N) from the second bias value to the third bias value.

[0060] In this embodiment, the output transistors MO(N), MO(N+1), MO(N+2), and MO(N+3) are, for example, N-type transistors. Furthermore, the output transistors MO(N), MO(N+1), MO(N+2), and MO(N+3) are, for example, N-type thin-film transistors.

[0061] For ease of explanation, this embodiment uses four output circuits 110(N) to 110(N+3) as an example. However, the number of output circuits in this invention is not limited to this. The number of output circuits in this invention can be multiple.

[0062] Please refer to Figure 2 , Figure 2This is a schematic diagram of a gate driving circuit according to another embodiment of the present invention. In this embodiment, the gate driving circuit 200 includes output circuits 210(N) to 210(N+3) and a noise suppression circuit 220. The output circuits 210(N) to 210(N+3) each provide different gate driving signals. For example, output circuit 210(N) provides the Nth level gate driving signal G(N). Output circuit 210(N+1) provides the (N+1)th level gate driving signal G(N+1), and so on.

[0063] In this embodiment, the output circuit 210(N) includes a pre-charge circuit 211(N), a coupling circuit 212(N), an output transistor M0, and a pull-down circuit 213(N). The pre-charge circuit 211(N) includes a pre-charge transistor M1. The first terminal of the pre-charge transistor M1 is coupled to a high reference voltage VDD. The second terminal of the pre-charge transistor M1 is coupled to a bias node Q(N). The control terminal of the pre-charge transistor M1 is coupled to the (N-2)th stage gate drive signal G(N-2). The pre-charge transistor M1 is turned on in response to the positive pulse of the (N-2)th stage gate drive signal G(N-2), and pre-charges the low bias value of the bias node Q(N) to a first bias value using the high reference voltage VDD.

[0064] In this embodiment, the coupling circuit 212(N) includes bridge transistors M2 and M3 and a coupling capacitor C1. The first terminal of bridge transistor M2 receives the (N-1)th stage gate drive signal G(N-1). The second terminal of bridge transistor M2 is coupled to a reference node A(N). The control terminal of bridge transistor M2 receives the (N-2)th stage clock signal CLK(N-2). In some embodiments, the control terminal of bridge transistor M2 receives the (N-2)th stage gate drive signal G(N-2). The first terminal of bridge transistor M3 is coupled to the reference node A(N). The control terminal of bridge transistor M3 receives a high reference signal VDD. The coupling capacitor C1 is coupled between the bias node Q(N) and the second terminal of bridge transistor M3.

[0065] In this embodiment, the (N-2)th stage gate drive signal G(N-2) and the (N-1)th stage gate drive signal G(N-1) can be provided by the previous stage gate drive circuit of the gate drive circuit 200.

[0066] Bridge transistor M2 is turned on by the positive pulse of the (N-2)th stage clock signal CLK(N-2), and the voltage at the second terminal of bridge transistor M2 is raised to a high voltage value using the (N-1)th stage gate drive signal G(N-1). Therefore, the voltage at the second terminal of bridge transistor M3 is also raised to a high voltage value. It should be noted that when the voltage at the second terminal of bridge transistor M3 is lower than the default voltage value, bridge transistor M3 couples the coupling capacitor C1 to the second terminal of bridge transistor M2. When the voltage at the second terminal of bridge transistor M3 is greater than or equal to the default voltage value, bridge transistor M3 isolates the coupling capacitor C1 from bridge transistor M2. The default voltage value is the voltage difference between the high reference voltage VDD and the critical voltage value of bridge transistor M3. Therefore, when the voltage at the second terminal of the bridge transistor M3 is less than the default voltage, the voltage difference between the high reference voltage VDD and the voltage at the second terminal of the bridge transistor M3 is greater than the critical voltage of the bridge transistor M3. Consequently, the on-state current of the bridge transistor M3 will be greater than zero.

[0067] On the other hand, when the voltage at the second terminal of bridge transistor M3 is greater than or equal to the second default voltage, the voltage difference between the high reference voltage VDD and the voltage at the second terminal of bridge transistor M3 is less than or equal to the critical voltage of bridge transistor M3. Therefore, the conduction current of bridge transistor M3 will be zero, exhibiting an isolated state, or high impedance (Hi-z) state. Bridge transistor M3 isolates the coupling capacitor C1 from bridge transistor M2. Therefore, the high voltage charge at the second terminal of bridge transistor M3 is maintained. It should also be noted that when the (N-1)th stage gate drive signal G(N-1) does not have a positive pulse, a sufficiently large voltage difference is provided between the disconnected second terminal of bridge transistor M3 and the first terminal of bridge transistor M2. Therefore, the charge at the second terminal of bridge transistor M3 does not leak.

[0068] In this embodiment, the coupling circuit 212(N) uses the coupling capacitor C1 and the high voltage value located at the second end of the bridge transistor M3 to couple the first bias value of the bias node Q(N) to the second bias value.

[0069] In this embodiment, the output transistor MO raises the bias node Q(N) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the Nth-level clock signal CLK(N).

[0070] In this embodiment, pull-down circuit 213(N) is coupled to bias node Q(N). Pull-down circuit 213(N) responds to the (N+a)th stage gate drive signal G(N+a) to pull down the bias value at bias node Q(N) to a low voltage value. In this embodiment, a is greater than or equal to the number of output circuits of gate drive circuit 200. a is, for example, equal to 5. Pull-down circuit 213(N) includes pull-down transistor M4. The first terminal of pull-down transistor M4 is coupled to a low reference voltage VSS. The second terminal of pull-down transistor M4 is coupled to bias node Q(N). The control terminal of pull-down transistor M4 receives the (N+5)th stage gate drive signal G(N+5). Pull-down transistor M4 is turned on in response to the positive pulse of the (N+5)th stage gate drive signal G(N+5) and uses the low reference voltage VSS to pull down the bias value at bias node Q(N).

[0071] In this embodiment, the output circuit 210(N+1) includes a pre-charge circuit 211(N+1), a coupling circuit 212(N+1), an output transistor M0a, and a pull-down circuit 213(N+1). The pre-charge circuit 211(N+1) includes a pre-charge transistor M1a. The first terminal of the pre-charge transistor M1a is coupled to a high reference voltage VDD. The second terminal of the pre-charge transistor M1a is coupled to a bias node Q(N+1). The control terminal of the pre-charge transistor M1a is coupled to the (N-1)th stage gate drive signal G(N-1). The pre-charge transistor M1a is turned on in response to the positive pulse of the (N-1)th stage gate drive signal G(N-1), and pre-charges the low bias value of the bias node Q(N+1) to a first bias value using the high reference voltage VDD.

[0072] In this embodiment, the coupling circuit 212(N+1) includes bridge transistors M2a and M3a, and a coupling capacitor C2. The first terminal of bridge transistor M2a receives the Nth-stage gate drive signal G(N). The second terminal of bridge transistor M2a is coupled to reference node A(N+1). The control terminal of bridge transistor M2a receives the (N-1)th-stage gate drive signal G(N-1). The first terminal of bridge transistor M3a is coupled to reference node A(N+1). The control terminal of bridge transistor M3a receives a high reference signal VDD. The coupling capacitor C2 is coupled between the bias node Q(N+1) and the second terminal of bridge transistor M3a. When the voltage at the second terminal of bridge transistor M3a is lower than the default voltage, bridge transistor M3a couples the coupling capacitor C2 to the second terminal of bridge transistor M2a. When the voltage at the second terminal of bridge transistor M3a is greater than or equal to the default voltage, bridge transistor M3a isolates the coupling capacitor C2 from bridge transistor M2a. Therefore, the charge at the high voltage value at the second terminal of the bridging transistor M3a is retained. Furthermore, a sufficiently large voltage difference is provided between the second terminal of the disconnected bridging transistor M3a and the first terminal of the bridging transistor M2a. Therefore, the charge at the second terminal of the bridging transistor M3a does not leak. The coupling circuit 212(N+1) uses the coupling capacitor C2 and the high voltage value at the second terminal of the bridging transistor M3a to couple the first bias value of the bias node Q(N+1) to the second bias value.

[0073] In this embodiment, the output transistor MOa raises the bias node Q(N+1) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the (N+1)th stage clock signal CLK(N+1).

[0074] In this embodiment, pull-down circuit 213(N+1) is coupled to bias node Q(N+1). Pull-down circuit 213(N+1) responds to the (N+6)th stage gate drive signal G(N+6) to pull down the bias value at bias node Q(N+1) to a low voltage value. Pull-down circuit 213(N+1) includes pull-down transistor M4a. A first terminal of pull-down transistor M4a is coupled to a low reference voltage VSS. A second terminal of pull-down transistor M4a is coupled to bias node Q(N+1). The control terminal of pull-down transistor M4a receives the (N+6)th stage gate drive signal G(N+6). Pull-down transistor M4a is turned on in response to the positive pulse of the (N+6)th stage gate drive signal G(N+6) and uses the low reference voltage VSS to pull down the bias value at bias node Q(N+1).

[0075] In this embodiment, the output circuit 210(N+2) includes a pre-charge circuit 211(N+2), a coupling circuit 212(N+2), an output transistor MOb, and a pull-down circuit 213(N+2). The pre-charge circuit 211(N+2) includes a pre-charge transistor M1b. The first terminal of the pre-charge transistor M1b is coupled to a high reference voltage VDD. The second terminal of the pre-charge transistor M1b is coupled to a bias node Q(N+2). The control terminal of the pre-charge transistor M1b is coupled to the Nth-stage gate drive signal G(N). The pre-charge transistor M1b is turned on in response to the positive pulse of the Nth-stage gate drive signal G(N), and pre-charges the low bias value of the bias node Q(N+2) to a first bias value using the high reference voltage VDD.

[0076] In this embodiment, the coupling circuit 212(N+2) includes bridge transistors M2b and M3b, and coupling capacitor C3. The first terminal of bridge transistor M2b receives the (N+1)th stage gate drive signal G(N+1). The second terminal of bridge transistor M2b is coupled to reference node A(N+2). The control terminal of bridge transistor M2b receives the Nth stage gate drive signal G(N). The first terminal of bridge transistor M3b is coupled to reference node A(N+2). The control terminal of bridge transistor M3b receives a high reference signal VDD. Coupling capacitor C3 is coupled between bias node Q(N+2) and the second terminal of bridge transistor M3b. When the voltage at the second terminal of bridge transistor M3b is lower than the default voltage, bridge transistor M3b couples coupling capacitor C3 to the second terminal of bridge transistor M2b. When the voltage at the second terminal of bridge transistor M3b is greater than or equal to the default voltage, bridge transistor M3b isolates coupling capacitor C3 from bridge transistor M2b. Therefore, the high voltage charge at the second terminal of the bridging transistor M3b is retained. Furthermore, a sufficiently large voltage difference is provided between the second terminal of the disconnected bridging transistor M3b and the first terminal of the bridging transistor M2b. Therefore, the charge at the second terminal of the bridging transistor M3b does not leak. The coupling circuit 212(N+2) uses the coupling capacitor C3 and the high voltage at the second terminal of the bridging transistor M3b to couple the first bias value of the bias node Q(N+2) to the second bias value.

[0077] In this embodiment, the output transistor MOb uses parasitic capacitance and the positive pulse of the (N+2)th stage clock signal CLK(N+2) to raise the bias node Q(N+2) from the second bias value to the third bias value.

[0078] In this embodiment, pull-down circuit 213(N+2) is coupled to bias node Q(N+2). Pull-down circuit 213(N+2) responds to the (N+7)th stage gate drive signal G(N+7) to pull down the bias value at bias node Q(N+2) to a low voltage value. Pull-down circuit 213(N+2) includes pull-down transistor M4b. A first terminal of pull-down transistor M4b is coupled to a low reference voltage VSS. A second terminal of pull-down transistor M4b is coupled to bias node Q(N+2). The control terminal of pull-down transistor M4b receives the (N+7)th stage gate drive signal G(N+7). Pull-down transistor M4b is turned on in response to the positive pulse of the (N+7)th stage gate drive signal G(N+7) and uses the low reference voltage VSS to pull down the bias value at bias node Q(N+2).

[0079] In this embodiment, the output circuit 210(N+3) includes a pre-charge circuit 211(N+3), a coupling circuit 212(N+3), an output transistor MOc, and a pull-down circuit 213(N+3). The pre-charge circuit 211(N+3) includes a pre-charge transistor M1c. The first terminal of the pre-charge transistor M1c is coupled to a high reference voltage VDD. The second terminal of the pre-charge transistor M1c is coupled to a bias node Q(N+3). The control terminal of the pre-charge transistor M1c is coupled to the (N+1)th stage gate drive signal G(N+1). The pre-charge transistor M1c is turned on in response to the positive pulse of the (N+1)th stage gate drive signal G(N+1), and pre-charges the low bias value of the bias node Q(N+3) to a first bias value using the high reference voltage VDD.

[0080] In this embodiment, the coupling circuit 212(N+3) includes bridge transistors M2c and M3c, and coupling capacitor C4. The first terminal of bridge transistor M2c receives the (N+2)th stage gate drive signal G(N+2). The second terminal of bridge transistor M2c is coupled to reference node A(N+3). The control terminal of bridge transistor M2c receives the (N+1)th stage gate drive signal G(N+1). The first terminal of bridge transistor M3c is coupled to reference node A(N+3). The control terminal of bridge transistor M3c receives a high reference signal VDD. Coupling capacitor C3 is coupled between the bias node Q(N+3) and the second terminal of bridge transistor M3c. When the voltage at the second terminal of bridge transistor M3c is lower than the default voltage, bridge transistor M3c couples coupling capacitor C4 to the second terminal of bridge transistor M2c. When the voltage at the second terminal of bridge transistor M3c is greater than or equal to the default voltage, bridge transistor M3c isolates coupling capacitor C4 from bridge transistor M2c. Therefore, the charge at the high voltage at the second terminal of bridge transistor M3c is retained. Furthermore, a sufficiently large voltage difference is provided between the disconnected second terminal of bridge transistor M3c and the first terminal of bridge transistor M2c. Therefore, the charge at the second terminal of bridge transistor M3b does not leak. Coupling circuit 212(N+3) uses coupling capacitor C4 and the high voltage at the second terminal of bridge transistor M3c to couple the first bias value of bias node Q(N+3) to the second bias value.

[0081] In this embodiment, the output transistor MOc uses parasitic capacitance and the positive pulse of the (N+3)th stage clock signal CLK(N+3) to raise the bias node Q(N+3) from the second bias value to the third bias value.

[0082] In this embodiment, pull-down circuit 213(N+3) is coupled to bias node Q(N+3). Pull-down circuit 213(N+3) responds to the (N+8)th stage gate drive signal G(N+8) to pull down the bias value at bias node Q(N+3) to a low voltage value. Pull-down circuit 213(N+3) includes pull-down transistor M4c. A first terminal of pull-down transistor M4c is coupled to a low reference voltage VSS. A second terminal of pull-down transistor M4c is coupled to bias node Q(N+3). The control terminal of pull-down transistor M4c receives the (N+8)th stage gate drive signal G(N+8). Pull-down transistor M4c is turned on in response to the positive pulse of the (N+8)th stage gate drive signal G(N+8) and uses the low reference voltage VSS to pull down the bias value at bias node Q(N+3).

[0083] In this embodiment, the (N+5)th stage gate drive signal G(N+5), the (N+6)th stage gate drive signal G(N+6), and the (N+7)th stage gate drive signal G(N+7) can be provided by the next stage gate drive circuit of the gate drive circuit 200.

[0084] In this embodiment, the noise suppression circuit 220 includes transistors M5-M7, M5a-M7a, M5b-M8b, and M5c-M7c. The noise suppression circuit 220 performs noise suppression operation on the output circuit 210(N) through transistors M5-M7, on the output circuit 210(N+1) through transistors M5a-M7a, on the output circuit 210(N+2) through transistors M5b-M8b, and on the output circuit 210(N+3) through transistors M5c-M7c.

[0085] Transistor M5's first terminal is coupled to the Nth-stage gate drive signal G(N). In other words, transistor M5's first terminal is coupled to the second terminal of output transistor MO. Transistor M5's second terminal is coupled to the low reference voltage VSS. Transistor M5's control terminal receives the first noise reduction control signal SN1. Transistor M6's first terminal is coupled to the Nth-stage gate drive signal G(N). Transistor M6's second terminal is coupled to the low reference voltage VSS. Transistor M6's control terminal receives the second noise reduction control signal SN2. Transistor M7's first terminal is coupled to the bias node Q(N). Transistor M7's second terminal is coupled to the low reference voltage VSS. Transistor M7's control terminal receives the first noise reduction control signal SN1.

[0086] The first terminal of transistor M5a is coupled to the (N+1)th stage gate drive signal G(N+1). In other words, the first terminal of transistor M5a is coupled to the second terminal of output transistor MOa. The second terminal of transistor M5a is coupled to the low reference voltage VSS. The control terminal of transistor M5a receives the first noise reduction control signal SN1. The first terminal of transistor M6a is coupled to the (N+1)th stage gate drive signal G(N+1). The second terminal of transistor M6a is coupled to the low reference voltage VSS. The control terminal of transistor M6a receives the second noise reduction control signal SN2. The first terminal of transistor M7a is coupled to the bias node Q(N+1). The second terminal of transistor M7a is coupled to the low reference voltage VSS. The control terminal of transistor M7a receives the first noise reduction control signal SN1.

[0087] The first terminal of transistor M5b is coupled to the (N+2)th stage gate drive signal G(N+2). In other words, the first terminal of transistor M5b is coupled to the second terminal of output transistor MOb. The second terminal of transistor M5b is coupled to the low reference voltage VSS. The control terminal of transistor M5b receives the first noise reduction control signal SN1. The first terminal of transistor M6b is coupled to the (N+2)th stage gate drive signal G(N+2). The second terminal of transistor M6b is coupled to the low reference voltage VSS. The control terminal of transistor M6b receives the second noise reduction control signal SN2. The first terminal of transistor M7b is coupled to the bias node Q(N+2). The second terminal of transistor M7b is coupled to the low reference voltage VSS. The control terminal of transistor M7b receives the first noise reduction control signal SN1. The first terminal of transistor M8b is coupled to the bias node Q(N+2). The second terminal of transistor M8b is coupled to the low reference voltage VSS. The control terminal of transistor M8b receives the second noise reduction control signal SN2.

[0088] The first terminal of transistor M5c is coupled to the (N+3)th stage gate drive signal G(N+3). In other words, the first terminal of transistor M5c is coupled to the second terminal of output transistor MOc. The second terminal of transistor M5c is coupled to the low reference voltage VSS. The control terminal of transistor M5c receives the first noise immunity control signal SN1. The first terminal of transistor M6c is coupled to the (N+3)th stage gate drive signal G(N+3). The second terminal of transistor M6c is coupled to the low reference voltage VSS. The control terminal of transistor M6c receives the second noise immunity control signal SN2. The first terminal of transistor M7c is coupled to the bias node Q(N+3). The second terminal of transistor M7c is coupled to the low reference voltage VSS. The control terminal of transistor M7c receives the first noise immunity control signal SN1.

[0089] It should be noted that the first noise suppression control signal SN1 is complementary to the second noise suppression control signal SN2. Taking transistors M5 and M6 as examples, during noise suppression operation, transistors M5 and M6 can be turned on alternately. This extends the lifespan of transistors M5 and M6. Furthermore, transistors M7b and M8b can be turned on alternately. This also extends the lifespan of transistors M7b and M8b.

[0090] In this embodiment, the precharge transistors M1, M1a, M1b, M1c, the bridge transistors M2, M2a, M2b, M2c, M3, M3a, M3b, M3c, the pull-down transistors M4, M4a, M4b, M4c, and transistors M5-M7, M5a-M7a, M5b-M8b, and M5c-M7c are, for example, N-type transistors. Furthermore, the precharge transistors M1, M1a, M1b, M1c, the bridge transistors M2, M2a, M2b, M2c, M3, M3a, M3b, M3c, the pull-down transistors M4, M4a, M4b, M4c, and transistors M5-M7, M5a-M7a, M5b-M8b, and M5c-M7c are, for example, N-type thin-film transistors.

[0091] In this embodiment, the gate drive circuit 200 further includes a noise suppression control circuit 230. The noise suppression control circuit 230 is coupled to the noise suppression circuit 220. The noise suppression control circuit 230 provides a first noise suppression control signal SN1 and a second noise suppression control signal SN2. The noise suppression control circuit 230 begins providing the first noise suppression control signal SN1 and the second noise suppression control signal SN2 after the bias value of the bias node of the last stage output circuit in the output circuits 210(N) to 210(N+3) is pulled down to the low bias value. For example, in this embodiment, the noise suppression control circuit 230 begins providing the first noise suppression control signal SN1 and the second noise suppression control signal SN2 after the bias value of the bias node Q(N+3) is pulled down to the low bias value.

[0092] In this embodiment, the noise reduction control circuit 230 is also coupled to reference nodes A(N) and A(N+1) and receives the (N-2)th level clock signal CLK(N-2) and the (N+2)th level clock signal CLK(N+2). The noise reduction control circuit 230 controls the noise reduction circuit 220 to perform noise reduction operation based on the voltage values ​​at reference nodes A(N) and A(N+1), the (N-2)th level clock signal CLK(N-2), and the (N+2)th level clock signal CLK(N+2).

[0093] Please refer to Figure 2 as well as Figure 3 , Figure 3 This is a schematic diagram of a noise suppression control circuit according to an embodiment of the present invention. In this embodiment, the noise suppression control circuit 230 includes control units 231 and 232. Control unit 231 provides a first noise suppression control signal SN1 in response to the (N+2)th stage clock signal CLK(N+2) after the bias value of bias node Q(N+3) is pulled down to a low bias value. Control unit 232 provides a second noise suppression control signal SN2 in response to the clock signal CLK(N-2) after the bias value of bias node Q(N+3) is pulled down to a low bias value.

[0094] Control unit 231 includes control transistors MC1 to MC3. The first terminal and control terminal of control transistor MC1 are coupled to a high reference voltage VDD. The second terminal of control transistor MC1 is used to output a first noise suppression control signal SN1. The first terminal of control transistor MC2 is coupled to the second terminal of control transistor MC1. The second terminal of control transistor MC2 is coupled to a low reference voltage VSS. The control terminal of control transistor MC2 is coupled to the (N+2)th stage clock signal CLK(N+2). The first terminal of control transistor MC3 is coupled to the second terminal of control transistor MC1. The second terminal of control transistor MC3 is coupled to the low reference voltage VSS. The control terminal of control transistor MC3 is coupled to reference node A(N) (i.e., the reference node of the first stage output circuit).

[0095] Control unit 232 includes control transistors MC4 to MC6. The first terminal and control terminal of control transistor MC4 are coupled to a high reference voltage VDD. The second terminal of control transistor MC4 is used to output a second noise suppression control signal SN2. The first terminal of control transistor MC5 is coupled to the second terminal of control transistor MC4. The second terminal of control transistor MC5 is coupled to a low reference voltage VSS. The control terminal of control transistor MC5 is coupled to the (N-2)th stage clock signal CLK(N-2). The first terminal of control transistor MC6 is coupled to the second terminal of control transistor MC4. The second terminal of control transistor MC6 is coupled to the low reference voltage VSS. The control terminal of control transistor MC6 is coupled to reference node A(N+2) (i.e., the reference node of the third-stage output circuit).

[0096] It is worth mentioning that the noise suppression control circuit 230 is not connected to the bias nodes Q(N) to Q(N+3). Therefore, the charge located at the bias nodes Q(N) to Q(N+3) is not shared with the noise suppression control circuit 230. Furthermore, the control transistors MC1 and MC4 are diode-connected transistors. Therefore, the parasitic capacitance of the noise suppression control circuit 230 is reduced.

[0097] In this embodiment, the control transistors MC1 to MC6 are, for example, N-type transistors. More specifically, the control transistors MC1 to MC6 are, for example, N-type thin-film transistors.

[0098] In some embodiments, the noise immunity control circuit 230 may provide a first noise immunity control signal SN1 and a second noise immunity control signal SN2 by at least two of a plurality of voltage values, a plurality of clock signals, and a plurality of gate drive signals located at reference nodes A(N) to A(N+3). The manner in which the first noise immunity control signal SN1 and the second noise immunity control signal SN2 are provided is not limited to this embodiment.

[0099] Please also refer to Figure 2 , Figure 3 as well as Figure 4 , Figure 4 This is a signal timing diagram according to an embodiment of the present invention. In this embodiment, during time interval T1, the precharge transistor M1 in the output circuit 210(N) is turned on in response to the (N-2)th stage gate drive signal G(N-2), and precharges the low bias value at the bias node Q(N) to a first bias value using the high reference voltage VDD. Therefore, the first bias value is approximately equal to the voltage difference between the voltage value of the high reference voltage VDD and the critical voltage value of the precharge transistor M1. Furthermore, the noise suppression control circuit 230 stops providing the first noise suppression control signal SN1 and the second noise suppression control signal SN2 with high voltage values. Therefore, the noise suppression circuit 220 begins to stop performing noise suppression operations. For example, during time interval T1, the (N+2)th stage clock signal CLK(N+2) turns on the control transistor MC2. The (N-2)th stage clock signal CLK(N-2) turns on the control transistor MC5. The voltage values ​​of both the first noise reduction control signal SN1 and the second noise reduction control signal SN2 are maintained at low voltage values.

[0100] During time interval T2, the bridge transistor M2 in the output circuit 210(N) has been turned on by the (N-2)th stage clock signal CLK(N-2). Therefore, the bridge transistor M2 charges the reference node A(N) and the second terminal of the bridge transistor M3 using the (N-1)th stage gate drive signal G(N-1). The coupling circuit 212(N) uses the coupling capacitor C1 to couple the first bias value at the bias node Q(N) to the second bias value.

[0101] During time interval T2, the precharge transistor M1a in the output circuit 210(N+1) has been turned on in response to the (N-1)th stage gate drive signal G(N-1), and the low bias value at the bias node Q(N+1) is precharged to the first bias value using the high reference voltage VDD.

[0102] During time interval T3, the output transistor MO in the output circuit 210(N) raises the bias node Q(N) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the Nth level clock signal CLK(N).

[0103] During time interval T3, the bridge transistor M2a in output circuit 210(N+1) has already been turned on in response to the (N-1)th stage gate drive signal G(N-1). Therefore, bridge transistor M2a charges reference node A(N+1) and the second terminal of bridge transistor M3a using the Nth stage gate drive signal G(N). Coupling circuit 212(N+1) uses coupling capacitor C2 to couple the first bias value at bias node Q(N+1) to the second bias value.

[0104] During time interval T3, the precharge transistor M1b in the output circuit 210(N+2) is turned on in response to the Nth gate drive signal G(N), and uses the high reference voltage VDD to precharge the low bias value at the bias node Q(N+2) to the first bias value.

[0105] During time interval T4, the output transistor MOa in the output circuit 210(N+1) raises the bias node Q(N+1) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the (N+1)th stage clock signal CLK(N+1).

[0106] During time interval T4, the bridge transistor M2b in output circuit 210(N+2) has already been turned on in response to the Nth stage gate drive signal G(N). Therefore, bridge transistor M2b charges reference node A(N+2) and the second terminal of bridge transistor M3b using the (N+1)th stage gate drive signal G(N+1). Coupling circuit 212(N+2) uses coupling capacitor C3 to couple the first bias value at bias node Q(N+2) to the second bias value.

[0107] During time interval T4, the precharge transistor M1c in the output circuit 210(N+3) is turned on in response to the (N+1)th stage gate drive signal G(N+1), and uses the high reference voltage VDD to precharge the low bias value at the bias node Q(N+3) to the first bias value.

[0108] During time interval T5, the output transistor MOb in the output circuit 210(N+2) raises the bias node Q(N+2) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the (N+2)th stage clock signal CLK(N+2).

[0109] During time interval T5, the bridge transistor M2c in output circuit 210(N+3) is turned on in response to the (N+1)th stage gate drive signal G(N+1). Therefore, bridge transistor M2c charges reference node A(N+3) and the second terminal of bridge transistor M3c using the (N+2)th stage gate drive signal G(N+2). Coupling circuit 212(N+3) uses coupling capacitor C4 to couple the first bias value at bias node Q(N+3) to the second bias value.

[0110] During time interval T6, the output transistor MOc in the output circuit 210(N+3) raises the bias node Q(N+3) from the second bias value to the third bias value by utilizing the parasitic capacitance and the positive pulse of the (N+3)th stage clock signal CLK(N+3).

[0111] During time interval T7, the Nth-level clock signal CLK(N) does not have a positive pulse. Therefore, the third bias value at the bias node Q(N) is pulled down to the second bias value.

[0112] During time interval T8, the pull-down transistor M4 in the output circuit 210(N) is turned on in response to the positive pulse of the (N+5)th stage gate drive signal G(N+5), and uses the low reference voltage VSS to pull down the second bias value located at the bias node Q(N) to a low bias value.

[0113] In time interval T8, the (N+1)th stage clock signal CLK(N+1) does not have a positive pulse. Therefore, the third bias value at the bias node Q(N+1) is pulled down to the second bias value.

[0114] During time interval T9, the pull-down transistor M4a in the output circuit 210(N+1) is turned on in response to the positive pulse of the gate drive signal G(N+6) at the (N+6)th stage, and uses the low reference voltage VSS to pull down the second bias value located at the bias node Q(N+1) to a low bias value.

[0115] In time interval T9, the (N+2)th stage clock signal CLK(N+2) does not have a positive pulse. Therefore, the third bias value at the bias node Q(N+2) is pulled down to the second bias value.

[0116] During time interval T10, the pull-down transistor M4b in the output circuit 210(N+2) is turned on in response to the positive pulse of the (N+7)th stage gate drive signal G(N+7), and uses the low reference voltage VSS to pull down the second bias value located at the bias node Q(N+2) to a low bias value.

[0117] In time interval T10, the (N+3)th stage clock signal CLK(N+3) does not have a positive pulse. Therefore, the third bias value at the bias node Q(N+3) is pulled down to the second bias value.

[0118] During time interval T11, the pull-down transistor M4c in the output circuit 210(N+3) is turned on in response to the positive pulse of the gate drive signal G(N+8) at the (N+8) stage, and uses the low reference voltage VSS to pull down the second bias value at the bias node Q(N+3) to a low bias value.

[0119] Furthermore, during time interval T11, the noise suppression period begins. The noise suppression control circuit 230 provides complementary first noise suppression control signals SN1 and second noise suppression control signals SN2. Therefore, during the noise suppression period, the noise suppression circuit 220 responds to the complementary first noise suppression control signals SN1 and second noise suppression control signals SN2 to perform full-time noise suppression operation on the output circuits 210(N) to 210(N+3).

[0120] In summary, the gate drive circuit of the present invention includes multiple output circuits and a noise suppression circuit. The noise suppression circuit performs noise suppression operation on the multiple output circuits. The multiple output circuits can share a single noise suppression circuit. Therefore, the layout area of ​​the gate drive circuit can be significantly reduced. Furthermore, the pre-charge circuit pre-charges the low bias value of the bias node to a first bias value. The coupling circuit raises the first bias value of the bias node to a second bias value. The output transistor reacts to the bias node to use the Nth stage clock signal as the Nth stage gate drive signal and raises the second bias value of the bias node to a third bias value. Therefore, the driving capability of the gate drive circuit in low-temperature environments can be improved.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: Multiple output circuits, each providing different gate drive signals, wherein the Nth stage output circuit among the multiple output circuits includes: A pre-charge circuit is configured to pre-charge the low bias value of the bias node of the Nth stage output circuit to a first bias value. A coupling circuit, coupled to the bias node, is configured to raise the first bias value of the bias node to a second bias value via capacitive coupling in response to the (N-1)th stage gate drive signal; and An output transistor, coupled to the bias node, is configured to use the Nth-stage clock signal as the Nth-stage gate drive signal in response to the bias value of the bias node, and to raise the second bias value of the bias node to a third bias value in response to the positive pulse of the Nth-stage clock signal; and A noise reduction circuit, coupled to the plurality of output circuits, is configured to pull down the plurality of gate drive signals and the bias values ​​of the bias nodes of the plurality of output circuits to a low reference voltage value after the bias value of the bias node of the last stage of the plurality of output circuits is pulled down to the low bias value. Where N is a positive integer.

2. The gate driving circuit according to claim 1, characterized in that, The coupling circuit includes: A first bridge transistor, wherein a first terminal of the first bridge transistor receives the (N-1)th level gate drive signal, a control terminal of the first bridge transistor receives the (N-2)th level gate drive signal, and a second terminal of the first bridge transistor is coupled to a reference node. A second bridge transistor, the first terminal of which is coupled to the reference node, and the control terminal of which receives a high reference voltage; and A coupling capacitor is coupled between the bias node and the second terminal of the second bridge transistor.

3. The gate driving circuit according to claim 2, characterized in that: When the voltage at the second terminal of the second bridge transistor is lower than the default voltage, the second bridge transistor couples the coupling capacitor to the second terminal of the first bridge transistor, and When the voltage at the second terminal of the second bridge transistor is greater than or equal to the default voltage value, the second bridge transistor isolates the coupling capacitor from the first bridge transistor.

4. The gate driving circuit according to claim 3, characterized in that, The default voltage value is the voltage difference between the high reference voltage and the critical voltage value of the second bridge transistor.

5. The gate driving circuit according to claim 2, characterized in that, The noise reduction circuit includes: A first transistor, wherein a first terminal of the first transistor is coupled to the Nth gate drive signal, a second terminal of the first transistor is coupled to the low reference voltage, and a control terminal of the first transistor receives a first noise reduction control signal; A second transistor, wherein a first terminal of the second transistor is coupled to the Nth-stage gate drive signal, a second terminal of the second transistor is coupled to the low reference voltage, and a control terminal of the second transistor receives a second noise reduction control signal; and A third transistor, wherein a first terminal of the third transistor is coupled to the bias node, a second terminal of the third transistor is coupled to the low reference voltage, and a control terminal of the third transistor receives the first noise reduction control signal.

6. The gate driving circuit according to claim 5, characterized in that, The first noise reduction control signal is complementary to the second noise reduction control signal.

7. The gate driving circuit according to claim 5, characterized in that, The gate driving circuit further includes: An anti-noise control circuit, coupled to the anti-noise circuit, includes: A first control unit is configured to respond to the (N+2)th stage clock signal by providing the first noise immunity control signal after the bias value of the bias node of the last stage output circuit in the plurality of output circuits is pulled down to the low bias value; and The second control unit is configured to respond to the (N-2)th stage clock signal to provide the second noise immunity control signal after the bias value of the bias node of the last stage output circuit in the plurality of output circuits is pulled down to the low bias value.

8. The gate driving circuit according to claim 7, characterized in that, The first control unit includes: A first control transistor, wherein a first terminal of the first control transistor and a control terminal of the first control transistor are coupled to a high reference voltage, and a second terminal of the first control transistor is used to output the first noise reduction control signal. A second control transistor, wherein a first terminal of the second control transistor is coupled to a second terminal of the first control transistor, a second terminal of the second control transistor is coupled to the low reference voltage, and a control terminal of the second control transistor is coupled to the (N+2)th stage clock signal; and A third control transistor, wherein a first terminal of the third control transistor is coupled to a second terminal of the first control transistor, the second terminal of the third control transistor is coupled to the low reference voltage, and the control terminal of the third control transistor is coupled to a reference node of the first stage output circuit among the plurality of output circuits.

9. The gate driving circuit according to claim 8, characterized in that, The second control unit includes: The fourth control transistor has a first terminal and a control terminal coupled to a high reference voltage, and a second terminal of the fourth control transistor is used to output the second noise reduction control signal. A fifth control transistor, wherein the first terminal of the fifth control transistor is coupled to the second terminal of the fourth control transistor, the second terminal of the fifth control transistor is coupled to the low reference voltage, and the control terminal of the fifth control transistor is coupled to the (N-2)th stage clock signal; and A sixth control transistor, wherein the first terminal of the sixth control transistor is coupled to the second terminal of the fourth control transistor, the second terminal of the sixth control transistor is coupled to the low reference voltage, and the control terminal of the sixth control transistor is coupled to the reference node of the third-stage output circuit among the plurality of output circuits.

10. The gate driving circuit according to claim 1, characterized in that, The Nth stage output circuit also includes: A pull-down circuit, coupled to the bias node, is configured to respond to the (N+a)th stage gate drive signal to pull down the bias value of the bias node to a low voltage value. Where a is greater than or equal to the number of output circuits of the gate drive circuit.

11. The gate driving circuit according to claim 1, characterized in that: The first terminal of the output transistor receives the Nth-level clock signal. The second terminal of the output transistor outputs the Nth-stage gate drive signal. The control terminal of the output transistor is coupled to the bias node. There is a parasitic capacitance between the control terminal and the second terminal of the output transistor, and The output transistor raises the bias node from the second bias value to the third bias value by utilizing parasitic capacitance and the positive pulse of the Nth-level clock signal.

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