Front-end calibration circuit and working method for dynamic comparator offset voltage elimination
By using the front-end calibration circuit of parallel NMOS tube and shift register in the dynamic comparator, the problems of large power consumption, large area and deterioration of delay in the dynamic comparator offset voltage cancellation scheme are solved, and the effect of low power consumption, small area and improved delay is achieved.
CN117498862BActive Publication Date: 2025-04-01XIAN UNIV OF POSTS & TELECOMM
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Patent Information
- Application Number
- CN202311515765.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-14
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2043-11-14
AI Technical Summary
Technical Problem
The existing dynamic comparator offset voltage cancellation scheme has problems such as large power consumption, large area and deterioration of delay.
Method used
Using a foreground calibration circuit including 2n NMOS tubes, shift registers and calibration logic circuits, the mismatch of the dynamic comparator input pair is compensated by parallel NMOS tubes, and the offset is identified through the shift registers and calibration logic circuits and generate a clock during the calibration cycle.
Benefits of technology
A front-end calibration circuit with low power consumption and small area is realized, which improves the deterioration of comparator delay and effectively eliminates the offset voltage of the dynamic comparator.
✦ Generated by Eureka AI based on patent content.
Abstract
The present invention belongs to the technical field of integrated circuits, and discloses a foreground calibration circuit and working method for eliminating the offset voltage of a dynamic comparator; wherein the foreground calibration circuit comprises: 2n NMOS tubes, used to compensate for the mismatch of the input pair of the dynamic comparator; a shift register, comprising 2n triggers; wherein each of the 2n triggers is used to generate a control signal for controlling the working area of each NMOS tube in the 2n NMOS tubes; a calibration logic circuit, used to input the offset polarity of the dynamic comparator and the output of the shift register, identify whether the dynamic comparator has an offset and generate a clock of the shift register within the calibration cycle. The present invention specifically provides a foreground calibration circuit with low power consumption and small area, which can improve the deterioration of the comparator delay.
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