Design method of beidou short message receiver based on FPGA

Abstract

The application provides a design method of a Beidou short message receiver based on an FPGA, which realizes capturing of global short messages and regional short messages, ensures continuous tracking of signals under truncated m1 sequence spreading, and receives Beidou short message signals without distortion. A short message sampling data buffer module is combined with a capturing module, and through timing control, the capturing module realizes capturing of a regional short message frame header using truncated m sequence spreading and a global short message frame header using periodic short code spreading; a tracking module integrating a pseudo code switching control module, a lead-just-lag code oscillator, a PN code length calculation module, a frequency synchronization loop and a timing synchronization loop is interacted with a short message decoding module, and realizes continuous tracking of global short messages and regional short messages; and the Beidou receiver architecture can receive global short messages and regional short messages.

Description

Technical Field

[0001] This invention belongs to the field of spread spectrum communication technology, specifically relating to a design method based on FPGA for a BeiDou global short message and BeiDou regional short message receiver (hereinafter referred to as a BeiDou short message receiver). Background Technology

[0002] After years of development, the BeiDou system has become an important new infrastructure providing all-weather, all-time, high-precision positioning, navigation, and timing services to global users. The BeiDou-3 global short message service can provide three basic functions: location reporting, emergency search and rescue, and message communication.

[0003] When a BeiDou short message receiver receives a BeiDou short message, the initial position of the received signal bits is random. Combined with Doppler frequency shift, this results in two uncertain parameters in the received signal: carrier and pseudocode. The receiver can only perform despreading and demodulation of the signal after achieving synchronization, and then reconstruct the original communication message according to the protocol file. The first step after receiving the signal is acquisition, which involves obtaining the starting position of the received signal, the phase delay of the message signal, and the Doppler frequency value. Due to environmental interference and other factors during signal transmission, the BeiDou short message needs to be tracked to obtain more accurate pseudocode phase and Doppler frequency offset values. After completing signal acquisition and tracking, the receiver obtains the BeiDou short message data frame, which can then be processed.

[0004] BeiDou short message receivers need to decode global and regional short message messages. For example... Figure 1 The image shows the frame structure of a global short message, consisting of a synchronization header, a service segment, and a data segment. Figure 2 As shown, the synchronization header and service segment header of the Global Short Message Service (GSMS) use periodic short codes for spread spectrum. The main body of the service segment uses a truncated m1 sequence for spread spectrum. In the data segment, the spread spectrum code needs to be XORed with a truncated m2 sequence and the truncated m1 sequence at the service segment to form Gold codes for spread spectrum. The service segment contains key information such as the initial phase of the m2 sequence, the number length indicator, and the CRC checksum. The pseudocode rate and information rate of the GSMS remain unchanged within a frame. Figure 3 The image shows the frame structure of a regional short message, which is similar to that of a global short message. The difference is that the regional short message uses a truncated m1 sequence for spread spectrum at the synchronization header. The specific spread spectrum method is as follows: Figure 4As shown. The pseudocode rate and information rate of the regional short message at the synchronization header are certain and known, while the information rates of the service segment and the data segment are different, specifically indicated by the frame identifier. Both global and regional short messages are convolutionally encoded in the service segment. CRC check exists in the service segment of the BeiDou short message to check the integrity of the received service segment data. When implementing the BeiDou short message receiver on FPGA, the following issues need to be addressed: (1) For global short messages, periodic short code spread spectrum is used at the short message frame header; while for regional short messages, truncated m1 sequence spread spectrum is used at the short message signal frame header. A universal short message acquisition module needs to be designed; (2) During the short message tracking process, there is the problem of how to continuously track and despread the signals under truncated m1 sequence and Gold sequence spread spectrum. This invention uses FPGA to implement a general architecture for BeiDou global and regional short message receivers to address the above issues. Summary of the Invention

[0005] The purpose of this invention is to provide a general architecture for a BeiDou global and regional short message receiver based on FPGA, so as to achieve the acquisition of global and regional short messages, ensure continuous tracking of signals under truncated m1 sequence spread spectrum, and receive BeiDou short message signals without distortion.

[0006] In response to the global and regional short message frame structures, this invention proposes a general architecture design method for a BeiDou global and regional short message receiver (BeiDou short message receiver). This method enables rapid and effective acquisition of global and regional short messages with different spread spectrum methods, continuous and stable tracking, and the reception of a complete BeiDou short message frame.

[0007] Specifically, the FPGA-based BeiDou short message receiver structure of this invention is as follows: Figure 5 As shown, it includes: a short message sampling data buffer module, a BeiDou short message general capture module, a BeiDou short message general tracking module, and a short message decoding module, etc.

[0008] in,

[0009] The short message sampling data buffer module buffers the received BeiDou short message data stream. Based on the timing requirements of the BeiDou short message general capture module and the BeiDou short message general tracking module, it buffers the short message sampling data stream and outputs the buffering results. The overall structure of the short message sampling data buffer module is as follows: Figure 6 As shown.

[0010] The BeiDou short message universal acquisition module processes the local spread spectrum sequence and the received demodulated data stream. It uses timing control to manage the data buffering of the short message sampling data buffer module, completing the acquisition of global and regional short messages, and outputting pseudo-code phase and Doppler frequency offset. The overall structure of the BeiDou short message universal acquisition module is as follows: Figure 10 As shown.

[0011] When tracking global short messages, the BeiDou short message universal tracking module tracks the carrier frequency and pseudocode phase of the sampled data through a frequency synchronization loop and a timing synchronization loop, thus completing the despreading of the short message sampled data. It selects the local spreading sequence through a lead-instant-lag code oscillator module, and supplements this with the generation of the truncated m1 sequence spreading code and the Gold sequence, as well as the iteration of the carrier tracking loop and the timing synchronization loop. Ultimately, it achieves continuous and stable tracking of the short message sampled data and outputs the despreading result to the short message decoding module.

[0012] When tracking regional short messages, the BeiDou short message universal tracking module only needs to adjust the global short message tracking process, without requiring major modifications. This is because the frame structures of regional and global short messages are similar. The difference lies in the fact that the spreading code for information bits in the frame header of regional short messages is a truncated m1 sequence, and there are no information bits with periodic short codes as spreading codes. The pseudocode rate and information rate of global short messages are constant in both the service segment and the data segment, but the pseudocode rate and information rate of regional short messages are constant only in the synchronization header. The pseudocode rate in the service segment and the data segment is the same as in the synchronization header, while the information rate is determined by the frame identifier. The BeiDou receiver architecture designed in this invention can track both global and regional short messages without requiring changes to the receiver structure. The overall tracking structure of the BeiDou short message universal tracking module is as follows: Figure 11 As shown.

[0013] The short message decoding module decodes the service segment, performs CRC checks, and outputs valid signals such as the end-of-frame flag signal, the initial phase of the m2 sequence, and the CRC check result. The overall structure of the short message decoding module is as follows: Figure 20 As shown.

[0014] The specific implementation steps are as follows:

[0015] S1: As Figure 8The diagram illustrates a parallel timing design for two-channel acquisition. During the acquisition phase, FIFO1 buffers the short message sample data stream required for one acquisition within time T1_acq. After time T2_acq, FIFO2 begins buffering the same short message sample data stream for another acquisition, with the buffering time being T1_acq. Subsequently, the Mux module selects the data, and within time T1_acq, the first-level register buffers the sampled data required for one acquisition. Within time T2_acq, the first-level register inputs the buffered data from T1_acq into the second-level register. The data is then cyclically output to the quadrature demodulation module to obtain the demodulated result.

[0016] like Figure 9 The diagram shows the tracking timing. During the tracking phase, noise signals at lower address bits in the first-level register are first discarded. Then, whenever the FIFO module in the first-level register completes buffering the short message sampling signal required for one tracking iteration, the tracking module begins tracking and despreading the sampled data. Simultaneously, the FIFO module in the first-level register continuously buffers the sampled data.

[0017] S2: The frequency sweep control module inputs the local oscillator frequency of this sweep into the quadrature demodulation module to obtain the demodulated signal at the current frequency. After receiving the demodulated data stream and the local PN sequence, the correlation operation module correlates the demodulated data with the local PN sequence and inputs the correlation result into the maximum value storage module. The maximum value storage module receives the correlation result and inputs the maximum value of the correlation result into the acquisition result determination module. The acquisition result determination module determines the acquisition result output by the maximum value storage module. If the acquisition is successful, it outputs the carrier frequency and pseudocode phase to the BeiDou short message universal tracking module; otherwise, it performs the operation at the next frequency and repeats the above acquisition process until the acquisition is successful.

[0018] S3: During global short message tracking, the lead-instant-hysteresis code despreading module selects from the periodic short code RAM according to the code address and outputs the instant code, lead code, and hysteresis code, which are then sequence-correlated with the input demodulated data stream. The correlation result is output to the tracking loop, and the correlation result with the instant code is output as the despreading result. The short message sampled data is continuously tracked until the frame identifier of the current frame is found, after which the tracking of the service segment begins, and the global short message spreading code changes from the periodic short code to a truncated m-sequence. The sequence conversion and padding module ensures the stability of the loop when the spreading method of the tracked information bits changes from the periodic short code to the truncated m-sequence. Then, the pseudo-code switching control module supplements the functionality of the tracking loop, continuously tracking the service segment sampled data. After tracking a certain number of information bits, the tracking of the data segment begins. At this time, the global short message spreading code changes from the truncated m-sequence to the Gold sequence. The short message sampled data is continuously tracked until the end of the current frame.

[0019] When tracking a regional short message, the lead-instant-hysteresis despreading module receives the captured pseudocode phase, generates a code address, and outputs the instant code, lead code, and hysteresis code from the truncated sequence RAM. These are then correlated with the input demodulated data. The correlation result is input into the tracking loop, and the correlation result with the instant code is output as the despreading result. At this point, tracking of the first bit of the regional short message is complete. Afterward, the synchronization header information bits are tracked through the pseudocode switching control module and the tracking loop until the frame identifier is found. The information rates of the current frame's service segment and data segment are obtained from the frame identifier, and the length of the generated truncated sequence is adjusted. The service segment information bits are continuously tracked, and after tracking a certain number of bits, tracking of the data segment begins. At this time, the spreading code of the regional short message is changed from the truncated m-sequence to the Gold sequence. The short message sampled data is continuously tracked until the end of the current frame.

[0020] S4: Upon receiving the despread signal, the frame identifier detection module first identifies the frame identifier. After identifying the frame identifier, it counts the despread signal. When the counter's accumulated value equals the count length, the current frame reception is complete, and a frame end flag signal is output. Simultaneously, the despread signal is input to the Viterbi decoding module, which decodes the despread signal and outputs key signals such as the initial phase of the m2 sequence and the CRC checksum. The decoded signal is then input to the CRC checksum module for CRC verification of the current frame.

[0021] Specifically, S1 includes the following steps:

[0022] S11, During the acquisition phase, when the short message sampling signal enters the short message sampling data buffer module, it is first stored by the first-level register module. The first-level register module contains two FIFO modules, FIFO1 and FIFO2, which start storing the short message sampling data stream at different times. During the tracking phase, only one FIFO in the first-level register module stores the short message sampling data stream.

[0023] like Figure 7The diagram shows a common acquisition timing scheme, employing a single acquisition method. The sampled data is buffered during the T1_acq time period, and the buffered data is captured during the T2_acq time period. However, for this acquisition timing design, when capturing regional short messages, if the sampled data buffered in the first-stage register is only a small portion of the first bit of the synchronization header, the correlation result obtained by the acquisition-related operation module will be poor, and the correlation peak will be submerged in the background value, resulting in the inability to capture the initial pseudocode phase of the first bit of the synchronization header. This problem does not occur for global short message acquisition because global short messages have a full-zero segment in the frame header, and the full-zero segment is spread using periodic short codes. Therefore, capturing any bit of the full-zero segment is considered a successful acquisition. This invention designs a two-channel parallel acquisition structure for both global and regional short message acquisition. When the receiver is in the acquisition phase, the acquisition module sends an acquisition pipeline timing control signal to the FIFO timing control circuit, which then controls the timing of writing the short message sampled data stream into the two FIFOs in the first-stage register module. Timing design for two-way parallel acquisition, as follows Figure 8 As shown, during the capture phase, FIFO1 first buffers the short message sample data stream required for one capture. After a time interval T2_acq, FIFO2 begins buffering the data stream. T1_acq is the time taken to buffer the sample data stream required for one capture, i.e., the sample data stream of length blocksize, and T2_acq is the time required to complete one capture. This parallel two-channel capture design ensures that if the sample data buffered in the first-stage register FIFO1 contains only a small portion of the first and second bits of the synchronization header, causing the correlation value obtained by the capture module to be submerged in the background value and resulting in capture failure, the data buffered in the first-stage register FIFO2 contains a large portion of the sample data of the first and second bits of the synchronization header. In this case, the correlation peak value obtained by the capture module is much higher than the background value, and the capture is successful. The value of blocksize is given by the following formula:

[0024]

[0025] chiprate is the pseudocode rate, bitrate is the symbol rate, and upsample is the upsampling factor.

[0026] After the receiver completes acquisition, the acquisition module sends an acquisition end flag signal. At this time, assuming that there is a frame header in the data stream stored in FIFO1 (the same applies if the frame header exists in FIFO2), FIFO2 will write all the sampled data received from the start of the first acquisition to the end of the first acquisition into FIFO1, ensuring the continuity of the data stream during the alternation between the acquisition and tracking modules.

[0027] During subsequent tracking, the bitrate remains unchanged for global short messages; only the sampled data stream of length blocksize stored in FIFO1 needs to be despread. For regional short messages, the bitrate changes, with the specific value indicated by the frame identifier. In this case, the blocksize value will change, and the length of the sampled data stream stored in FIFO1 must also be changed accordingly.

[0028] S12, the data stream output from the first-level register module and the data stream output from the second-level register module are input together into the Mux 2-to-1 data selector, and the Mux outputs the data stream to the second register module.

[0029] When capturing BeiDou short messages, the short message data within the T1_acq time period is input to the first-level register module. After selection by the Mux module, the sampled short message data from the first-level register module is input to the second-level register module. Within the T2_acq time period, to achieve the purpose of controlling variables, the same data stream needs to be sequentially multiplied with local carriers of different frequencies, and then demodulated by LPF filtering. Therefore, within the T2_acq time period, the data buffered within the T1_acq time period needs to be cyclically output, that is, the output port of the second-level register module is connected to the input port.

[0030] When tracking BeiDou short messages, such as Figure 9 The diagram shows the tracking timing. Assuming the first bit of the frame header is present in the short message sampling data stream buffered in FIFO1, when a BeiDou short message signal is captured, FIFO1 will contain short message sampling data buffered within the time periods T1_acq and T2_acq, with a value of blocksize_acqall. The captured pseudo-code phase begins at acqphasebias, indicating that the acqphasebias bits at lower addresses in FIFO1 are noise. Therefore, FIFO1 will first output the acqphasebias data stream, but the tracking module will not operate to discard this sampling data. Figure 9The diagram illustrates two possible scenarios when a BeiDou short message universal receiver switches from short message sampling signal acquisition to sampling signal tracking. If the data buffered in FIFO1 has reached or exceeded the block size, the data buffered in FIFO1 is stored in the second-level register within the T2_track time period, with the clock pulse as the enable signal. Simultaneously, the first-level register continuously buffers the short message sampling data. After the t1_track time period, FIFO1 has buffered the short message sampling data stream required to complete one tracking cycle, the number of which is the block size. If the data buffered in FIFO1 has not yet reached the block size, after the t1_track time period, FIFO1 has buffered the short message sampling data stream required to complete one tracking cycle. At this point, the data buffered in FIFO1 is immediately stored in the second-level register, with the clock pulse as the enable signal. The following steps are repeated throughout the subsequent tracking process until the current frame tracking ends. During the T2_track time period, the first-level register immediately begins storing the next block-size of packet sample data. Due to the selection by the Mux data selector, data transmission between the first-level register module and the second-level register module is blocked. The sample data in the second-level register remains the previous block-size length. During this time period, the second-level register outputs the sample data, and the tracking module begins operation. After the T1_track time period, the data length stored in the first-level register reaches the block-size, and tracking of the previous block-size length of sample data is complete. At this point, the first-level register writes data to the second-level register via the Mux data selector, while the FIFO module in the first-level register continuously stores the next block-size of packet sample data. Therefore, enabling only one FIFO in the first-level register and subsequently enabling one second-level register is sufficient to complete the tracking of the packet sample data.

[0031] S13 completes the demodulation function of the data stream. The second-level register module inputs the data stream to the multiplier, multiplies it with the carrier generated by the local carrier DDS, and obtains the demodulation result through the LPF filter.

[0032] S2 specifically includes the following steps:

[0033] S21, when the capture module starts, it sends the local oscillator frequency of this frequency sweep to the local carrier DDS. The interval between each frequency sweep is freqInc, and the number of frequency cabinets scanned is acqSearchBand.

[0034] S22, the quadrature demodulation module sends the demodulated signal to the relevant arithmetic module.

[0035] S23, the local PN sequence lookup table selects the local spread spectrum sequence required for capture-related operations from the periodic short code storage ROM and the truncated m1 sequence storage ROM, and outputs it to the relevant operation module.

[0036] The local PN sequence lookup table stores the conjugate values ​​of the FFT transforms of the PRN group periodic short code sequence and the conjugate values ​​of the FFT transforms of the truncated m1 sequence of the PRN group blocksize length. The periodic short code is the spreading code for the message information bits in the global short message synchronization header, and the truncated m1 sequence of blocksize length is the spreading code for the first bit of the regional short message. Different satellites transmit BeiDou short messages, and the spreading sequence used in the frame header varies, requiring selection based on the PRN value of the satellite currently tracking the BeiDou short message.

[0037] S24, after receiving the demodulated data stream and the local PN sequence, the correlation operation module correlates the demodulated data with the local PN sequence.

[0038] S25, the correlation results are sent to the maximum value memory for storing the frequency sweep results and determining the maximum value of the correlation results. The storage area of ​​the maximum value memory module contains a ping-pong structure composed of two RAMs. After one frequency sweep, the maximum value memory module can provide the maximum correlation peak value from the first frequency sweep to the current frequency point, as well as all correlation results of the frequency point where the maximum correlation peak value is located. After all frequency points have been scanned, the maximum correlation peak value among all frequency points and all correlation results of the frequency point where the maximum correlation peak value is located can be output.

[0039] S26, determine the output capture result. Find the second peak value from all correlation results at the frequency point where the maximum correlation peak value is stored, calculate the ratio of the maximum correlation peak value to the second peak value, and compare it with the set threshold. If the ratio is greater than the set threshold, the capture is considered successful; otherwise, it is considered that no BeiDou short message data frame has been captured, and the capture fails. Repeat steps S21 to S26 until the capture is successful.

[0040] S3 specifically includes the following steps:

[0041] The tracking module's steps are divided into two parts depending on the frame structure of global short messages and regional short messages. However, the tracking steps are largely the same for both. The tracking module first tracks the synchronization header based on the captured carrier frequency offset and pseudocode phase value. After receiving the frame identifier, it enters the service segment tracking, and after tracking the specified bits, it enters the data segment tracking. Finally, upon receiving the frame end flag signal, the tracking ends. The specific steps for both are as follows.

[0042] The following is the tracking process for BeiDou global short messages.

[0043] S31, the quadrature demodulation module sends the demodulated I and Q signals to the lead-instant-hysteresis code despreading module.

[0044] S32, the lead-instant-lag code oscillator selects from short periodic codes based on code address, outputting an instant code pcode, a lead code ecode (leading the instant code by 0.5 chips), and a lag code lcode (lagging the instant code by 0.5 chips). These are then correlated with the input I-channel and Q-channel demodulated signals. After integration, accumulation, and addition / subtraction of squares, the correlation results I_E, I_P, I_L, Q_E, Q_P, and Q_L are obtained.

[0045] S33, the lead-instant-hysteresis code despreading module outputs the relevant results to the frequency synchronization loop and the timing synchronization loop. The carrier synchronization loop outputs the carrier frequency control word to the lead-instant-hysteresis code despreading module, thereby correcting the frequency of the local carrier in the quadrature demodulation module. The timing synchronization loop then corrects the pseudocode phase, ensuring that the generated local spreading code used for despreading is aligned with the code phase of the input short message data stream.

[0046] In step S34, the correlation value I_P is output as the despreading result to the short message decoding module. The short message decoding module will check whether the frame identifier position has been tracked. If the frame identifier is tracked, the spreading sequence of the BeiDou short message needs to be switched from the periodic short code to the truncated m1 sequence, and step S35 is performed. Otherwise, the iterative process of S31, S32, S33, and S34 continues until the frame identifier of the current frame is found.

[0047] S35, the sequence conversion and padding module receives the pseudo-code phase signal from the lead-instant-hysteresis code despreading module. This pseudo-code phase represents the sum of the phase of the last chip of the last bit of the frame identifier and the pseudo-code phase control word, that is, the phase corresponding to the first short message sampling data of the first bit entering the service segment. The PN code length calculation unit inputs the calculated chip length M into the initial sequence length generation unit. The structure of the sequence conversion and padding module is as follows: Figure 13 As shown.

[0048] The initial sequence length generation unit converts the received pseudocode phase into a metric value M, denoted as len_begin. len_begin is then input into a zero-padding / dropout decision unit. If the most significant bit of len_begin is 0 under metric value M, the generated local spreading code needs to discard the data in len_begin under metric value M; if the most significant bit of len_begin is 1 under metric value M, the generated local PN sequence needs to be padded with zeros up to len_begin+1 under metric value M.

[0049] To ensure accuracy when selecting local spreading codes, the local spreading code selected via the code address must be aligned with the short message sampled data stream to achieve the best despreading result. The bit width N of the code address should be much larger than the number of spreading codes M required per bit. However, regardless of the bit width, the code address is essentially a step value within the spreading chip. Therefore, when determining whether to discard or pad the beginning of the spreading code when switching from a periodic short code to a truncated m1 sequence, the code address should be transformed from bit width N to bit width M. The required number of spreading codes M is determined by the chip rate and bit rate. For global short messages with different PRN numbers, the chip rate and bit rate are fixed. The value of M is given by the following formula:

[0050]

[0051] chiprate is the pseudocode rate, and bitrate is the information rate.

[0052] The reason why local spreading codes need to be padded with zeros or have data dropped when switching to truncated m-sequences is that, ideally, the short message sampled data stream should be aligned with the local spreading sequence for the best despreading result. Figure 14 As shown. However, in practice, the local spreading sequence may lead or lag behind the short message sampling data stream. This is due to the different sources of the crystal oscillators on the FPGA board of the BeiDou short message transmitter and the BeiDou short message receiver, as well as environmental interference that may occur during the transmission of BeiDou short messages. The tracking loop will correct the pseudocode phase step value initphase and the number of information bits accumulated during despreading (blocksize) to ensure that the local spreading sequence and the short message sampling data correspond one-to-one, such as... Figure 15 As shown. At this point, when despreading the last information bit using the short-code spread spectrum, it's possible that the data stored in the first-level register FIFO of the short message sampling data buffer module contains a segment of information stream spread using a truncated m-sequence, such as... Figure 16 As shown. Alternatively, during the despreading of the first information bit spread using truncated m-sequence spread, a situation arises where the data stored in the first-level register FIFO of the short message sampling data buffer module contains a segment of information stream spread using periodic short codes, such as... Figure 17 As shown. Furthermore, due to the excessive length of the truncated m1 sequence, it cannot be stored in RAM due to FPGA resource limitations. Therefore, the truncated m1 sequence required for despreading the current spreading sequence needs to be generated in real-time before despreading begins. When the following occurs... Figure 16In the scenario shown, the truncated m-sequence generation module needs to generate a spreading code of length M + len_begin + 1, discarding the first len_begin length of the spreading code. The last len_begin + 1 length of the spreading code is written into the truncated sequence RAM. When performing sequence correlation, a lag code of 0.5 chips is needed. Therefore, if the current bit despreading requires M spreading codes, one more spreading code must be generated before despreading. Simultaneously, sequence correlation also requires a lead code of 0.5 chips. In the RAM storing the local low-frequency code in the first bit, the generated local spreading code starts from memory location 1, and memory location 0 stores 0 spreading codes. However, when a situation occurs... Figure 17 In the case shown, zero values ​​of length ~len_begin+1 need to be written into the truncated m-sequence RAM in advance. Then, the truncated m-sequence generation module generates a spreading code of length M-~len_begin and writes it into the truncated sequence RAM in address order.

[0053] S36, based on the spreading code generated in step S35, the first bit of the service segment's information is tracked using the frequency synchronization loop and timing synchronization loop. Then, during the continuous tracking phase of the service segment's message sampling signal stream using the tracking loop, the first bit decision module determines whether to write the spreading code elements from the last two addresses of the spreading code stored in the previous bit's truncated m-sequence RAM to the first two addresses of the current bit's truncated m-sequence RAM, or to write the spreading code elements from the last three addresses of the previous bit's truncated m-sequence RAM to the first three addresses of the current bit's truncated m-sequence RAM. After the first bit decision module makes its decision, the truncated m-sequence generation module generates the spreading code required for despreading the current information bit and writes it into the truncated sequence RAM in address order.

[0054] like Figure 15 At the transmitting end, after spreading each information bit, upsampling is required. For ease of explanation, assume the upsampling factor upsample = 4. When selecting the local spreading sequence, the initial phase initphase needs to be determined first. Then, the code address is generated based on the pseudocode phase step value, also known as the pseudocode phase control word codephase_step. The local spreading sequence for despreading is selected from the generated local spreading codes using the code address.

[0055] like Figure 18If the phase of the last sample point of the previous bit is located within the spreading chip PN(M)_m1, and the pseudo-code phase obtained by adding the pseudo-code phase control word of the previous bit is located within the multi-generated spreading chip PN(M+1)_m1, this indicates that the phase of the first sample point of the current bit should be located within PN(M+1)_m1. Since the lead code output by the lead-instant-hysteresis code oscillator leads the instant code by 0.5 chips, the preceding chip PN(M)_m1 of the spreading chip PN(M+1)_m1 should be written to the first address of the truncated sequence RAM of the next bit, and chip PN(M+1)_m1, as the initial phase of the instant code, should be written to the second address of the truncated sequence RAM of the next bit.

[0056] like Figure 19 If the phase of the last sample point of the previous bit is located within the spreading chip PN(M)_m1, and the pseudo-code phase control word of the current bit is also located within the extra-generated spreading chip PN(M)_m1, this indicates that the phase of the first sample point of the current bit should be located within PN(M)_m1. Then PN(M)_m1 is written to the second address of the truncated sequence RAM of the next bit, and the extra-generated chip PN(M+1)_m1 of the previous bit is written to the third address of the truncated sequence of the next bit. For lead codes, to prevent the corresponding spreading symbol from being unavailable when addressing the lead code ecode, PN(M-1)_m1 should be written to the first address of the truncated sequence RAM of the next bit.

[0057] S37, the lead-instant-lag code oscillator counts the enable signal for generating the instant code, and the accumulated value is recorded as m1_cnt. According to the frame structure of BeiDou short messages, the number of bits at the service end is a fixed value P1 for global short messages. According to the following calculation formula, when m1_cnt counts to m1_cnt_MAX, the truncated m-sequence generation module generates a truncated m2 sequence, which is XORed with the truncated m1 sequence to form a Gold sequence. Afterwards, the spreading symbols output by the truncated m-sequence generation module to the truncated sequence RAM are the Gold sequence, not the truncated m1 sequence output during the service segment. Subsequently, the tracking loop and the first bit decision module continuously track the sampled data stream of the short message data segment. The value of m1_cnt_MAX is given by the following formula:

[0058]

[0059] chiprate is the pseudocode rate, bitrate is the bit rate, and P1 is the number of bits in the global short message service terminal.

[0060] The generator polynomial of the truncated m2 sequence has been determined, and its initial phase information is contained in the service segment. After the short message decoding module solves the polynomial, it inputs the initial phase into the tracking module.

[0061] The number of information bits contained in a single frame of BeiDou short message data is also fixed, and its value is determined by the length indication information in the service segment and calculated by the short message decoding module. After the short message decoding module completes the tracking of all bits of the global short message, it outputs an end signal, clears all state machines, and the state machines of each module control the clearing of all registers within them.

[0062] The following is the tracking process for short messages in the BeiDou region:

[0063] S31, the quadrature demodulation module sends the demodulated I and Q signals to the lead-instant-hysteresis code despreading module.

[0064] S32, after receiving the pseudo-code phase input from the capture module, the sequence filling unit generates the code address corresponding to the spreading code required for despreading the current information bits. Simultaneously, the truncated m-sequence generation module needs to generate a spreading code of length codelen_head+1 and write it into the truncated sequence RAM in address order. The reason the truncated m-sequence generation module generates an extra spreading code is to prevent the problem of not finding the corresponding spreading code when addressing the lcode, which lags behind the immediate code by 0.5 chips. The value of codelen_head is given by the following formula:

[0065]

[0066] chiprate is the pseudocode rate, and bitrate_head is the information rate given in the synchronization header of the area short message.

[0067] The lead-instant-lag code oscillator selects from the truncated sequence RAM according to the code address, outputting the instant code pcode, lead code ecode, and lag code lcode. It performs sequence correlation with the input I-channel and Q-channel demodulated signals to obtain correlation results I_E, I_P, I_L, Q_E, Q_P, and Q_L. The lead-instant-lag code despreading module outputs the correlation results to the tracking loop, which consists of a frequency synchronization loop and a timing synchronization loop. The carrier synchronization loop outputs the carrier frequency control word to the lead-instant-lag code despreading module, thereby correcting the frequency of the local carrier in the quadrature demodulation module. The timing synchronization loop corrects the pseudocode phase, ensuring that the generated local spreading code used for despreading is aligned with the code phase of the input short message data stream.

[0068] S33, based on the tracking loop, is the stage of continuously tracking the sampling signal stream of the synchronization header message. The first bit decision module determines whether to write the spreading code elements from the last two addresses of the spreading code stored in the previous bit's truncated m-sequence RAM to the first two addresses of the current bit's truncated m-sequence RAM, or whether to write the spreading code elements from the last three addresses of the previous bit's truncated m-sequence RAM to the first three addresses of the current bit's truncated m-sequence RAM. After the first bit decision module makes its decision, the truncated m-sequence generation module generates the spreading code of codelen_head length required for despreading the current information bits and writes it into the truncated sequence RAM in address order. The tracking result is input into the short message decoding module for frame identifier identification. The function of the first bit decision module is described in detail in the steps of global short message tracking, and will not be repeated here.

[0069] S34, when a frame identifier is detected, the information rate of the service segment and data segment is determined by the frame identifier. Then, the length of the spreading code of the current service segment and data segment information bits is obtained by the PN code length calculation module, denoted as codelen_data.

[0070]

[0071] chiprate is the pseudocode rate, and bitrate_data is the information rate of the service segment and data segment obtained according to the frame identifier indication.

[0072] The information rate of regional short messages differs between the service segment and the data segment depending on the frame identifier. The information rate of the synchronization header (containing the frame identifier) ​​is fixed at bitrate1. The table below shows the indication of frame identifiers and information rates.

[0073]

[0074]

[0075] S35 is a stage for continuous tracking of the service section message sampling signal stream, based on the tracking loop and supplemented by the function of the first bit decision module.

[0076] S36, the lead-instant-lag code oscillator counts the enable signal for generating the instant code, and the accumulated value is recorded as m2_cnt. The number of bits at the regional short message service end is a fixed value P2. According to the following calculation formula, when m2_cnt counts to m2_cnt_MAX, the truncated m-sequence generation module generates a truncated m2 sequence, which is XORed with the truncated m1 sequence to form a Gold sequence. After that, the spreading symbols output by the truncated m-sequence generation module to the truncated sequence RAM are changed to the Gold sequence. Subsequently, the short message sampling data stream of the data segment is continuously tracked based on the tracking loop and the first bit decision module. The value of m2_cnt_MAX is given by the following formula:

[0077]

[0078] chiprate is the pseudocode rate, bitrate is the bit rate, and P2 is the number of bits in the regional short message service terminal.

[0079] The generator polynomial of the truncated m2 sequence has been determined, and its initial phase information is contained in the service segment. After the short message decoding module calculates the initial phase, it inputs it into the tracking module. After the short message decoding module completes tracking of all bits of the area short message, it outputs an end signal, and the tracking of the current frame ends.

[0080] S4 specifically includes the following steps:

[0081] S41, the frame identifier detection module receives the despread signal and first identifies the frame identifier. Upon identification of the frame identifier, short message tracking enters the service segment. For regional short messages, the frame identifier indicates the symbol rate of the current frame's service segment and information segment. Simultaneously with frame identifier identification, a counter counts the received despread signal. When the counter's accumulated value equals the count length, the current frame reception is complete, and a frame end flag signal is output.

[0082] S42, after receiving the despread signal from the tracking module, the Viterbi decoding module inputs the despread signal into the Viterbi IP core. The Viterbi IP core decodes the service segment before the short message enters the data segment. The decoding result includes the initial phase of the m2 sequence, the number length indicator, and the CRC check code.

[0083] S43, the CRC check module performs CRC check on the signals of the service section and outputs the CRC check result.

[0084] The advantages and beneficial effects of this invention are as follows:

[0085] (1) A short message sampling data buffer module was designed and combined with the capture module. The capture of regional short message frame headers using truncated m-sequence spread spectrum and global short message frame headers using periodic short codes was achieved through timing control.

[0086] (2) An integrated pseudo-code switching control module, a lead-instant-lag code oscillator, a PN code length calculation module, a frequency synchronization loop, and a timing synchronization loop tracking module were designed and interacted with the short message decoding module to achieve continuous tracking of global and regional short messages.

[0087] (3) The designed Beidou receiver architecture can receive global short messages as well as regional short messages. Attached Figure Description

[0088] Figure 1 This refers to the structure of the BeiDou global short message frame.

[0089] Figure 2 This is a spread spectrum method for BeiDou global short message service.

[0090] Figure 3 This is the structure of the BeiDou regional short message frame.

[0091] Figure 4 This is a short message spread spectrum method for the BeiDou region.

[0092] Figure 5 This is a schematic diagram of the overall architecture of the BeiDou short message receiver proposed in this invention.

[0093] Figure 6 This is a schematic diagram of the short message sampling data buffer module proposed in this invention.

[0094] Figure 7 This is a typical capture timing diagram.

[0095] Figure 8 This is a schematic diagram of the BeiDou short message acquisition timing proposed in this invention.

[0096] Figure 9 This is a schematic diagram of the BeiDou short message tracking timing proposed in this invention.

[0097] Figure 10 This is a schematic diagram of the BeiDou short message general capture module proposed in this invention.

[0098] Figure 11 This is a schematic diagram of the BeiDou short message universal tracking module proposed in this invention.

[0099] Figure 12 This is a schematic diagram of the Mr. Bit Supplement Decision Module proposed in this invention (belonging to the Beidou Short Message Tracking Module).

[0100] Figure 13 This is a schematic diagram of the sequence conversion and filling module proposed in this invention (belonging to the BeiDou short message tracking module).

[0101] Figure 14This is a timing diagram of the short message sampling data stream and local spread spectrum sequence proposed in this invention.

[0102] Figure 15 This is a schematic diagram of the local spread spectrum sequence selection proposed in this invention.

[0103] Figure 16 , Figure 17 A schematic diagram illustrating the problems that arise when the spread spectrum method for tracking information bits is switched from a periodic short code to a truncated sequence.

[0104] Figure 18 , Figure 19 This is a schematic diagram of the principle of the first bit decision module proposed in this invention.

[0105] Figure 20 This is a schematic diagram of the short message decoding module proposed in this invention. Detailed Implementation

[0106] The present invention will now be described in further detail with reference to the accompanying drawings and examples.

[0107] Below is an example of a received BeiDou global short message.

[0108] The BeiDou global short message synchronization header contains 20 bits of all-zero information and a 32-bit frame header, which is "1ACFFC1D". The synchronization header uses a 2047-bit periodic short code for spread spectrum, with an initial phase of "0x123", and the generator polynomial is determined by the PRN number. The service segment uses a 24th-order m1 sequence for spread spectrum, with a total length of 2^24-1. The generator polynomial of the m1 sequence is g1 = 1 + x + x. 1 +x 2 +x 24 The initial phase is "0x123456". The m2 sequence is a 24th order m-sequence with a total length of 2^24-1. The generator polynomial of the m2 sequence is g2 = 1 + x. 3 +x 4 +x 5 +x 24 The initial phase is "0xABCDEF". The m2 sequence, starting from the data end, is XORed with the m1 sequence to form a Gold sequence for spreading the BeiDou short message. The initial phase of the m2 sequence is "0x1C4E78", determined by the first 24 bits of the service segment. The least significant bit of the ingress address corresponds to the least significant bit of the initial phase, and also corresponds to the highest power of the polynomial generated. The service segment contains 140 bits of information, using (2, 1, 5) convolutional coding, with a 600-bit data length indicator. The service segment also contains reserved bits, acknowledgment identifiers, etc., while the data segment contains information such as the information category. However, the number of bits for these information is customized. The service segment and data segment together contain 740 bits of signal.

[0109] The BeiDou global short message signal has a chip rate of 1.6376MHz, an information rate of 400bps, uses BPSK modulation, a symbol rate of 800sps, and an intermediate frequency carrier frequency of 3.2752MHz. The upsampling factor is 8.

[0110] S11, during the acquisition phase, the short message sampling signal is stored in FIFO1 of the first-level register of the short message sampling data buffer module. The acquisition module captures the first bit of the BeiDou global short message, and the number of short message sampling data that need to be stored is... Under the onboard crystal oscillator clock of the FPGA, the time required for the FIFO to complete the storage of blocksize sampling points is T1_acq = 2045.88us. The time required to achieve one capture is T2_acq = 1807.98us. Therefore, FIFO2 starts storing short message sampling data after FIFO1 starts storing short message sampling data at T2_acq = 1807.98us.

[0111] After the receiver completes acquisition, the acquisition module outputs an end flag signal. The captured frame header is located in the short message sampling signal stored in FIFO1. The short message sampling data stored in FIFO2 during the last time period T1_acq = 2045.88us is written to the end of FIFO1 in address order. In subsequent tracking, only 16376 short message sampling data need to be stored in FIFO1.

[0112] S12, during the capture process, the data within the time period T1_acq = 2045.88us is input into the first-level register, and after passing through the Mux module, it is also input into the second-level register. The data registered within the time period T2_acq = 1807.98us is cyclically output through the Mux module.

[0113] Upon entering the tracking process, the first-level register FIFO1 buffers 30848 sampled data points, and the pseudo-code phase value obtained by the acquisition module is 1304. Within 15.12µs, FIFO1 first outputs the currently buffered data, discarding 1304 noise samples. At this time, 121 short message samples are input into FIFO1, bringing the total buffered data to 30969. During the time interval T2_track = 166.29µs, the data buffered in FIFO1 is stored in the second-level register. After t1_track = 56.47µs, FIFO1 has buffered the 16376 short message sampled data streams required to complete one tracking cycle. The following steps are repeated throughout the subsequent tracking process until the current frame tracking ends. A tracking process takes T2_track = 166.29us to complete. During the T2_track time period, the first-level register immediately begins storing the next 16376-byte segment of packet sample data. Due to the selection by the Mux data selector, the transmission between the first-level register module and the second-level register module is blocked. The sample data in the second-level register is still the previous 16376-byte segment. During this time period, the second-level register outputs the sample data, and the tracking module begins to work. After T1_track = 2045.88us, the data length stored in the first-level register reaches 16376 bytes, and the tracking of the previous 16376-byte segment is complete. At this point, the first-level register writes data to the second-level register through the Mux data selector, while the FIFO module in the first-level register continuously stores the next 16376-byte segment of packet sample data.

[0114] S13, the data stream input multiplier is multiplied with the carrier generated by the local carrier DDS and the result is obtained by passing through the LPF filter.

[0115] S21, the capture module performs frequency sweeps at intervals of freqInc = 500Hz, scanning 9 frequency cabinets, with the intermediate frequency signal being localIF = 3.275MHz. The capture module scans the BeiDou short message sampling data stream within the range of [3.275MHz - 1 / 2 * 500Hz * 8, 3.275MHz + 1 / 2 * 500Hz * 8]. The local carrier frequency initially sent by the frequency sweep module to the local carrier DDS generation module should be 3.275MHz - 1 / 2 * 500Hz * 8, and this value is accumulated during subsequent sweeps. The accumulated value is the sweep interval of 500Hz.

[0116] S22, after the short message is demodulated, the demodulated signal is sent to the relevant processing module.

[0117] S23, the local PN sequence lookup table module selects the local spreading sequence required for capture-related operations from the periodic short code storage ROM according to the satellite number PRN=36, and outputs this spreading sequence to the related operation module.

[0118] S24, the relevant computation module obtains 16376 I-channel demodulated data streams x I (n), the local spreading sequence pn selected based on satellite PRN=36 bd (n), the modulus of the output results.

[0119] y(n) = IFFT[FFT(x) I (n))*pn bd (n)]

[0120] S25, the correlation result is input to the maximum value storage module. After correlation is completed and the correlation results are output in all 9 frequency cabinets, the correlation between the demodulated short message sampling data and the local spread spectrum sequence at the used frequency point 3.275MHz - 1 / 2 * 500Hz * 4 = 3.274MHz can be obtained. Its maximum correlation peak value is the historical maximum correlation peak value. The captured carrier frequency is 3.275MHz, and the Doppler frequency offset f d At <500Hz, the maximum value of the correlation peak is 13147, and the pseudocode phase corresponding to the maximum value of the correlation peak is 1304.

[0121] S26, The captured output is evaluated, and the ratio of the relevant peak value to the second-highest value, peaksize >> 1.5, is calculated, where 1.5 is the set threshold. Capture passed.

[0122] S31, the quadrature demodulation module inputs the demodulated signal into the lead-instant-hysteresis code despreading module.

[0123] S32, the spreading code length of BeiDou global short message is 2047. The lead-instant-lag code oscillator selects from the periodic short codes of satellite number PRN=36 according to the code address, and outputs instant code pcode, lead code ecode and lag code lcode, and correlates them with the demodulation results of I and Q channels respectively.

[0124] The S33 lead-instant-hysteresis code despreading module outputs the relevant results to the frequency synchronization loop and the timing synchronization loop. It also continuously tracks BeiDou short messages.

[0125] S34, the correlation value I_P is output as the despreading result to the short message decoding module. The short message decoding module performs sliding window correlation to check whether the frame identifier "1ACFFC1D" has been tracked. If the frame identifier is detected, proceed to step S35; otherwise, it indicates that the loop is tracking the synchronization header, and the tracking of the short message sampling data continues.

[0126] S35, the sequence conversion padding module receives the pseudo-code phase signal from the lead-instant-hysteresis code despreading module, calculates len_begin = 2, and inputs len_begin = 2 into the zero-padding decision unit. Since the highest bit of len_begin = 2 is 0 under a code length of 2047, it indicates that the generated local spreading code needs to discard data of len_begin = 2 under a code length of M = 2047. The truncated m-sequence generation module needs to generate a spreading code of length M + len_begin + 1 = 2047 + 2 + 1 = 2050, discards the first two spreading symbols, and writes the last 2048 spreading symbols into the truncated sequence RAM.

[0127] S36. Based on the spreading code generated in step S35, the first bit of the service segment is tracked using the frequency synchronization loop and timing synchronization loop. After tracking the first bit of the service segment, the first bit decision module determines that the phase of the last sampling point of the first bit of the service segment is within the spreading code chip PN(2049)_m1, and even after adding the current pseudo-code phase control word, it is still within the spreading code chip PN(2049)_m1. Therefore, the currently generated spreading symbols PN(2048)_m1, PN(2049)_m1, and PN(2050)_m1 need to be written to the first three addresses of the truncated sequence RAM of the next bit. After the first bit decision module makes its decision, the truncated m-sequence generation module continues to generate a 2046-bit spreading code and writes it into the truncated sequence RAM in address order. Then, based on the supplementary functions of the tracking loop and the bit decision module, the service segment message sampling data is continuously tracked.

[0128] S37, the lead-instant-hysteresis code oscillator counts the enable signal for generating instant codes, and the maximum value accumulated by the counter is... When the counter reaches its maximum value, the XOR of the inserted truncated m2 sequence and the truncated m1 sequence yields the truncated Gold sequence. Subsequently, the spreading symbols output by the truncated m-sequence generation module to the truncated sequence RAM are the Gold sequence, not the truncated m1 sequence output during the service segment. Following this, based on the tracking loop, and employing a first-bit decision module at adjacent information bits, continuous tracking of BeiDou short messages is performed.

[0129] After the short message decoding module outputs the frame end flag signal, the tracking of all bits of the BeiDou global short message is completed. All state machines of the tracking module are cleared to zero. At the same time, the state control machine of each module controls all registers inside to be cleared to zero, waiting for the arrival of the next BeiDou short message capture end signal.

[0130] S41, the frame identifier detection module receives the despread signal and first performs a sliding window correlation on it: synRes = sum((frameHead) * data_win). Where frameHead = "1ACFFC1D". After identifying the frame identifier, it instructs the short message tracking to enter the service segment. At the same time, the counter counts the received despread signal. When the accumulated value reaches 740 bits, it outputs the frame end flag signal.

[0131] S42, the Viterbi decoding module decodes the service section data to obtain the initial phase of the m2 sequence "0x1C4E78", the length indicator 600, and the CRC check code.

[0132] S43 performs CRC check on the signals of the service section and outputs the CRC check result.

[0133] Below is an example of a received BeiDou regional short message.

[0134] The BeiDou regional short message synchronization header contains 30 bits, and the end of the header contains a 12-bit frame identifier, with the remainder being all zeros. The information rate output from the synchronization header is 2 ksps, and the frame identifier is "001101010101". The synchronization header and service segment use a continuous truncated m1 sequence for spread spectrum. The total length of the m1 sequence is 2^24-1, and the generator polynomial is g1 = 1 + x + x. 2 +x 3 +x 24 The initial phase is "0xFAF1AF". The data segment is Gold code spread spectrum. The Gold code is generated by XORing the m1 sequence and the m2 sequence. The m2 sequence is a 24th order m sequence with a total length of 2^24-1, and the generator polynomial of the m2 sequence is g2 = 1 + x. 3 +x 4 +x 5 +x 24 The initial phase is "0x123456". The m2 sequence, starting from the data end, is XORed with the m1 sequence to form a Gold sequence for spreading the BeiDou short message. The initial phase of the m2 sequence is "0xABCDEF", determined by the first 24 bits of the service segment. The least significant bit of the ingress address corresponds to the least significant bit of the initial phase, and also corresponds to the highest power of the polynomial used in its generation. The service segment contains 180 bits of information, using (4, 1, 5) convolutional coding, with a 600-bit data length indicator. The service segment and the data segment together contain 780 bits of signal.

[0135] The chip rate at the synchronization header of the BeiDou regional short message signal is 40.8MHz, the information rate is 1000bps, BPSK modulation is used, the symbol rate is 2000sps, and the intermediate frequency carrier frequency is 8.16MHz. The pseudocode rate of the service segment and data segment remains unchanged, the chip rate is still 40.8MHz, and the information rate is indicated by the frame identifier. The upsampling factor is 8. The table below shows the indication of the frame identifier and information rate.

[0136]

[0137]

[0138] S11, during the acquisition phase, the short message sampling signal is stored in FIFO1 of the first-level register of the short message sampling data buffer module. The acquisition module captures the first bit of the BeiDou global short message, and the number of short message sampling data that need to be stored is... Under the onboard crystal oscillator clock of the FPGA, the time required for the FIFO to complete the storage of 16320 sampling points is T1_acq = 2038.881us. The time required to achieve one capture is T2_acq = 1807.98us. Therefore, FIFO2 starts storing short message sampling data after FIFO1 starts storing short message sampling data at T2_acq = 1807.98us.

[0139] After the receiver completes acquisition, the acquisition module outputs an end flag signal. The captured frame header is located in the short message sampling signal stored in FIFO1. The short message sampling data stored in FIFO2 during the time period T1_acq = 2038.881us is sequentially written to the end of FIFO1.

[0140] During the tracking process, when tracking the sampling data of the synchronization header short message,

[0141] FIFO1 stores short message sampling data of length 16320 bytes. This is used when tracking service segments and data segments.

[0142] FIFO1 stores sampled data of length 8160.

[0143] S12, during the capture process, the data within the time period T1_acq = 2038.881us is input into the first-level register, and after passing through the Mux module, it is also input into the second-level register. The data registered within the time period T2_acq = 1807.98us and T1_acq = 2045.88us are cyclically output through the Mux module.

[0144] Upon entering the tracking process, the first-level register FIFO1 buffers 30792 sampled data points, and the pseudo-code phase value obtained by the acquisition module is 407. Within 6.15µs, FIFO1 first outputs the currently buffered data, discarding 407 noise sample points. At this time, 49 short message sampled data points are input into FIFO1, bringing the total buffered data to 30841. During the time interval T2_track = 165.650µs, the data buffered in FIFO1 is stored in the second-level register. After t1_track = 224.75µs, FIFO1 has buffered the 16320 short message sampled data streams required to complete one tracking cycle. The following steps are repeated throughout the subsequent tracking process until the current frame tracking ends. A tracking process takes T2_track = 165.650us to complete. During the T2_track time period, the first-level register immediately begins storing the next 16320-byte segment of message sample data. Due to the selection by the Mux data selector, the transmission between the first-level register module and the second-level register module is blocked. The sample data in the second-level register is still the previous 16320-byte segment. During this time period, the second-level register outputs the sample data, and the tracking module begins to work. After T1_track = 2038.88us, the data length stored in the first-level register reaches 16320 bytes, and the tracking of the previous 16320-byte segment is complete. At this point, the first-level register writes data to the second-level register through the Mux data selector, while simultaneously storing the next 16320-byte segment of message sample data without interruption. When tracking the sampled data of short messages in the service segment and data segment, due to the change in information rate, the values ​​of T1_track and T2_track are 1019.44us and 84.090us, respectively. FIFO1 stores sampled data of length 8160, while the rest of the steps remain unchanged.

[0145] S13, the data stream input multiplier is multiplied with the carrier generated by the local carrier DDS and the result is obtained by passing through the LPF filter.

[0146] S21, the capture module scans frequencies at intervals of freqInc = 500Hz, scanning 9 frequency cabinets, with the intermediate frequency signal being localIF = 3.275MHz. The capture module scans the BeiDou short message sampling data stream within the range of [3.275MHz - 1 / 2 * 500Hz * 8, 3.275MHz + 1 / 2 * 500MHz * 8]. The local carrier frequency initially sent by the frequency sweep module to the local carrier DDS generation module should be 3.275MHz - 1 / 2 * 500Hz * 8 = 3.273MHz, and this value is accumulated during each subsequent frequency sweep. The accumulated value is calculated at a frequency sweep interval of 500Hz.

[0147] S22, after the short message is demodulated, the demodulated signal is sent to the relevant processing module.

[0148] S23, the local PN sequence lookup table module selects the local spreading sequence required for capture-related operations from the periodic short code storage ROM, and outputs this spreading sequence to the related operation module.

[0149] S24, the relevant computation module obtains 16320 I-channel demodulated data streams x. I (n), the local spreading sequence pn selected based on satellite PRN=36 bd (n), the modulus of the output results.

[0150] y(n) = IFFT[FFT(x) I (n))*pn bd (n)]

[0151] S25, the correlation result is input to the maximum value storage module. After correlation is completed and the correlation results are output in all 9 frequency cabinets, the correlation between the demodulated short message sampling data and the local spread spectrum sequence at the used frequency point 3.275MHz-500Hz=3.2745MHz can be obtained. Its maximum correlation peak value is the historical maximum correlation peak value. The captured carrier frequency is 3.2745MHz, and the Doppler frequency offset f d <500Hz, the maximum value of the correlation peak is 19380, and the pseudocode phase corresponding to the maximum value of the correlation peak is 407.

[0152] S26, The captured output is evaluated, and the ratio of the relevant peak value to the second-highest value, peaksize >> 1.5, is calculated, where 1.5 is the set threshold. Capture passed.

[0153] S31, the quadrature demodulation module sends the demodulated I and Q signals to the lead-instant-hysteresis code despreading module.

[0154] S32, the sequence conversion and filling module receives the pseudo-code phase signal from the lead-instant-hysteresis code despreading module, thus generating the code address corresponding to the spreading code required for despreading the current information bits. Simultaneously, the truncated m-sequence generation module needs to generate a spreading code of length 2041 and write it into the truncated sequence RAM in address order. The value of codelen_head is:

[0155]

[0156] The lead-instant-hysteresis code oscillator selects codes from the truncated sequence RAM according to their addresses and outputs instant code pcode, lead code ecode, and hysteresis code lcode. These are then correlated with the input I-channel and Q-channel demodulated signals to obtain the correlation results I_E, I_P, I_L, Q_E, Q_P, and Q_L.

[0157] S33, based on the tracking loop, continuously tracks the sampled data stream of the regional short message synchronization header. The first bit decision module determines whether to write the spreading code elements from the last two addresses of the spreading code stored in the previous bit's truncated m-sequence RAM to the first two addresses of the current bit's truncated m-sequence RAM, or whether to write the spreading code elements from the last three addresses of the previous bit's truncated m-sequence RAM to the first three addresses of the current bit's truncated m-sequence RAM. After the first bit decision module makes its decision, the truncated m-sequence generation module generates the 2040-byte spreading code required for despreading the current information bits and writes it into the truncated sequence RAM in address order. The tracking result is input into the short message decoding module for frame identification. The function of the first bit decision module is detailed in the steps of global short message tracking and will not be repeated here.

[0158] S34, the short message decoding module detects a frame identifier of "110010101010", indicating that the received short message sampling data stream frame header sequence number is 1, the information rate is 4000sps, and a reversed π phenomenon has occurred. The despreading signal decision symbol needs to be flipped to obtain the correct BeiDou short message signal. Then, the length of the spreading code for the current service segment and data segment information bits is obtained through the PN code length calculation module.

[0159]

[0160] S35 is a stage for continuous tracking of the service section message sampling signal stream, based on the tracking loop and supplemented by the function of the first bit decision module.

[0161] S36, the lead-instant-hysteresis code oscillator counts the enable signal for generating the instant code, and the accumulated value is recorded as m2_cnt. The number of bits in the regional short message service terminal is a fixed value of 180. When m2_cnt counts to... At that time, the truncated m-sequence generation module generates a truncated m2 sequence, which is XORed with the truncated m1 sequence to form a Gold sequence. Afterwards, the spreading symbols output by the truncated m-sequence generation module to the truncated sequence RAM are changed to the Gold sequence. Subsequently, the tracking loop and the first bit decision module continuously track the sampled data stream of the short data segment.

[0162] The generator polynomial of the truncated m2 sequence has been determined, and its initial phase information is contained in the service segment. After the short message decoding module calculates the initial phase, it inputs it into the tracking module. After the short message decoding module completes tracking of all bits of the area short message, it outputs an end signal, and the tracking of the current frame ends.

[0163] S41, the frame identifier detection module receives the despread signal and first performs a sliding window correlation on it: synRes = sum((frameHead) * data_win). Where frameHead = "001101010101". Upon identifying the frame identifier, it instructs short message tracking to enter the service segment. Simultaneously, a counter counts the received despread signal. When the accumulated value reaches 780 bits, it outputs a frame end flag signal.

[0164] S42, the Viterbi decoding module decodes the service section data to obtain the initial phase of the m2 sequence "0xABCDEF", the length indicator 600 and the CRC check code.

[0165] S43 performs CRC check on the signals of the service section and outputs the CRC check result.

Claims

1. A design method for a BeiDou short message receiver based on FPGA, characterized in that, Includes the following steps: S1: The timing design is divided into two-way acquisition parallel sequence. During the acquisition phase, FIFO1 buffers the short message sampling data stream required for one acquisition within the time T1_acq. After the time T2_acq, FIFO2 starts buffering the short message sampling data stream required for one acquisition, and the buffering time is T1_acq. Then, after selection by the Mux module, the first-level register completes the sampling data required for one acquisition within the time period T1_acq. Within the time period T2_acq, the first-level register inputs the data buffered within the time period T1_acq into the second-level register. After that, the data is cyclically output to the quadrature demodulation module to obtain the demodulation result. During the tracking phase, noise signals in the lower address bits of the first-level register are first discarded; then, whenever the FIFO module in the first-level register has finished buffering the short message sampling signal required for one tracking cycle, the tracking module begins to track and despread the sampled data; at the same time, the FIFO module in the first-level register continuously buffers the sampled data. S2: The frequency sweep control module inputs the local oscillator frequency of this frequency sweep into the quadrature demodulation module to obtain the demodulated signal at the current frequency point; after receiving the demodulated data stream and the local PN sequence, the correlation operation module correlates the demodulated data with the local PN sequence and inputs the correlation result into the maximum value storage module; The maximum value storage module receives the relevant results and inputs the maximum value of the relevant results into the capture result determination module; The capture result determination module determines the capture result output by the maximum value storage module; if the capture is successful, it outputs the carrier frequency and pseudocode phase to the Beidou short message general tracking module; otherwise, it performs the calculation for the next frequency point and repeats the above capture process until the capture is successful. S3: When tracking global short messages, the lead-instant-hysteresis code despreading module selects from the periodic short code RAM according to the code address and outputs instant code, lead code and hysteresis code, which are then sequence correlated with the input demodulated data stream; The results are output to the tracking loop, and the correlation results with the instant code are output as the despreading results. The short message sampling data is continuously tracked until the frame identifier of the current frame is found. Then, the tracking of the service segment begins. The spreading code of the global short message is changed from a periodic short code to a truncated m-sequence. The sequence conversion and filling module ensures the stability of the loop when the spreading method of the tracked information bits is changed from a periodic short code to a truncated m-sequence. Then, the tracking loop is supplemented by the pseudocode switching control module to continuously track the sampled data of the service segment; after tracking a certain number of information bits, the tracking of the data segment begins; at this time, the spreading code of the global short message is changed from the truncated m sequence to the Gold sequence. The short message sampling data is continuously tracked until the end of the current frame; When tracking a regional short message, the lead-instant-hysteresis code despreading module receives the captured pseudo-code phase, generates a code address, and outputs the instant code, lead code, and hysteresis code from the truncated sequence RAM. It then performs sequence correlation with the input demodulated data. The correlation result is input into the tracking loop, and the correlation result with the instant code is output as the despreading result. At this point, the tracking of the first bit of the regional short message is complete. Then, the synchronization header information bits are tracked through the pseudocode switching control module and the tracking loop until the frame identifier is found; the information rates of the current frame's service segment and data segment are obtained through the frame identifier, and the length of the generated truncated sequence is adjusted; the service segment information bits are continuously tracked, and after tracking a certain number of bits, the tracking of the data segment begins; at this time, the spreading code of the area short message is changed from the truncated m sequence to the Gold sequence; the short message sampled data is continuously tracked until the end of the current frame; S4: The frame identifier detection module receives the despread signal and first identifies the frame identifier. After identifying the frame identifier, it counts the despread signal. When the counter value equals the count length, the current frame reception is complete, and the frame end flag signal is output. The despread signal is simultaneously input to the Viterbi decoding module, which decodes the despread signal and outputs the initial phase of the m2 sequence and the CRC check code signal. The decoded signal is input to the CRC check module to perform CRC check on the current frame.

2. The design method of a Beidou short message receiver based on FPGA according to claim 1, characterized in that: S1 specifically includes the following steps: S11, During the acquisition phase, when the short message sampling signal enters the short message sampling data buffer module, it is first stored by the first-level register module. The first-level register module contains two FIFO modules, FIFO1 and FIFO2, which start storing the short message sampling data stream from different times. During the tracking phase, only one FIFO in the first-level register module will store the short message sampling data stream. S12, the data stream output from the first-level register module and the data stream output from the second-level register module are input together into the Mux 2-to-1 data selector, and the Mux outputs the data stream to the second register module; S13 completes the demodulation function of the data stream. The second-level register module inputs the data stream to the multiplier, multiplies it with the carrier generated by the local carrier DDS, and obtains the demodulation result through the LPF filter.

3. The design method of a Beidou short message receiver based on FPGA according to claim 2, characterized in that: S11 also includes: when the receiver is in the acquisition phase, the acquisition module sends an acquisition pipeline timing control signal to the FIFO timing control circuit, and the FIFO timing control circuit controls the timing of writing short message sampling data streams into the two FIFOs in the first-stage register module; in the acquisition phase, FIFO1 first starts buffering the short message sampling data stream required for one acquisition, and after T2_acq time, FIFO2 starts buffering the data stream; T1_acq is the time used to buffer the sampling data stream required for one acquisition, i.e., the sampling data stream of blocksize length, and T2_acq is the time required to complete one acquisition; the value of blocksize is given by the following formula: chiprate is the pseudocode rate, bitrate is the symbol rate, and upsample is the upsampling factor; When the receiver is in the tracking phase, the information rate will not change for global short messages. Only the sampled data stream of length blocksize stored in FIFO1 needs to be despread. For regional short messages, the information rate bitrate will change. The specific value is indicated by the frame identifier. At this time, the value of blocksize will change, and the length of the sampled data stream stored in FIFO1 must also be changed accordingly.

4. The design method of a Beidou short message receiver based on FPGA according to claim 2, characterized in that: S12 also includes: when capturing BeiDou short messages, the short message data within the T1_acq time period is input into the first-level register module, and after selection by the Mux module, the short message sampled data input into the first-level register module is input into the second-level register module; within the T2_acq time period, the same data stream needs to be multiplied by local carriers of different frequencies, and then demodulated by LPF filtering; therefore, within the T2_acq time period, the data buffered within the T1_acq time period needs to be output cyclically, that is, the output port of the second-level register module is connected to the input port; When tracking BeiDou short messages, noise signals are first discarded based on the captured pseudocode phase. Then, the following steps are repeated until the current frame tracking ends. When the first-level register module has data of blocksize length buffered, tracking of short message sampled data begins. That is, the buffered data is stored in the second-level register within the T2_track time, and the second-level register is input to the quadrature demodulation module. At the same time, the first-level register continuously buffers sampled data. After the T1_track time, when the number of buffered data in the first-level register reaches blocksize, the next tracking is performed.

5. The design method of a Beidou short message receiver based on FPGA according to claim 1, characterized in that: S2 specifically includes the following steps: S21, When the capture module starts, it sends the local oscillator frequency of this frequency sweep to the local carrier DDS; the interval between each frequency sweep is freqInc, and the number of frequency cabinets scanned is acqSearchBand; S22, the quadrature demodulation module sends the demodulated signal to the relevant processing module; S23, the local PN sequence lookup table selects the local spread spectrum sequence required for capture-related operations from the periodic short code storage ROM and the truncated m1 sequence storage ROM, and outputs it to the related operation module; S24, after receiving the demodulated data stream and the local PN sequence, the correlation operation module correlates the demodulated data with the local PN sequence; S25, the correlation results are sent to the maximum value memory for frequency sweep result storage and determination of the maximum value of the correlation results; the storage area of ​​the maximum value memory module contains a ping-pong structure composed of two RAMs. After one frequency sweep is completed, the maximum value memory module provides the maximum correlation peak value from the first frequency sweep to the current frequency point, as well as all correlation results of the frequency point where the maximum correlation peak value is located; after all frequency points have been scanned, the maximum correlation peak value among all frequency points and all correlation results of the frequency point where the maximum correlation peak value is located are output. S26, determine the output capture result; find the second peak value from all the correlation results of the frequency point where the maximum correlation peak value is stored, calculate the ratio of the maximum correlation peak value to the second peak value, and compare it with the set threshold; if the ratio is greater than the set threshold, the capture is considered successful; otherwise, it is considered that no Beidou short message data frame has been captured, the capture fails, and steps S21 to S26 are repeated until the capture is successful.

6. The design method of a Beidou short message receiver based on FPGA according to claim 5, characterized in that: S23 also includes storing the conjugate value of the FFT transform of the PRN group periodic short code sequence and the conjugate value of the FFT transform of the truncated m1 sequence of the PRN group blocksize length in the local PN sequence lookup table; the periodic short code is the spreading code of the message information bits at the global short message synchronization header, and the truncated m1 sequence of the blocksize length is the spreading code of the first bit of the regional short message; the spreading sequence used in the frame header of BeiDou short messages transmitted by different satellites is different, and it needs to be selected according to the PRN value of the satellite number currently tracking BeiDou short messages.

7. The design method of a Beidou short message receiver based on FPGA according to claim 1, characterized in that: S3 specifically includes the following steps: the tracking process for BeiDou global short messages; S31, the quadrature demodulation module sends the demodulated I-channel and Q-channel demodulated signals to the lead-instant-hysteresis code despreading module; S32, the lead-instant-lag code oscillator selects from the short periodic codes according to the code address, and outputs the instant code pcode, the lead code ecode which leads the instant code by 0.5 chips, and the lag code lcode which lags the instant code by 0.5 chips. It performs sequence correlation with the input I-channel and Q-channel demodulated signals, and after integration, accumulation, square addition and subtraction operations, obtains the correlation results I_E, I_P, I_L, Q_E, Q_P, Q_L. S33, the lead-instant-hysteresis code despreading module outputs the relevant results to the frequency synchronization loop and the timing synchronization loop; the carrier synchronization loop outputs the carrier frequency control word to the lead-instant-hysteresis code despreading module, thereby correcting the frequency of the local carrier in the quadrature demodulation module; the timing synchronization loop corrects the pseudocode phase, so that the generated local spreading code used for despreading is aligned with the code phase of the input short message data stream; S34, the correlation value I_P is output as the despreading result to the short message decoding module. The short message decoding module will check whether the position of the frame identifier has been tracked. If the frame identifier is tracked, the spreading sequence of the Beidou short message needs to be switched from the periodic short code to the truncated m1 sequence, and step S35 is performed. Otherwise, the iterative process of S31, S32, S33, and S34 continues until the frame identifier of the current frame is found. S35, the sequence conversion and filling module receives the pseudo-code phase signal from the lead-instant-hysteresis code despreading module. This pseudo-code phase represents the sum of the phase of the last chip of the last bit of the frame identifier and the pseudo-code phase control word, that is, the phase corresponding to the first short message sampling data of the first bit of the service segment. The PN code length calculation unit inputs the calculated chip length M into the initial sequence length generation unit. The truncated m sequence generation module, together with the sequence conversion and filling module, generates the spreading code of the first bit of the service segment and writes it into the truncated sequence RAM. S36, based on the spreading code generated in step S35, the first bit of the service segment's information is tracked using the frequency synchronization loop and timing synchronization loop; then, based on the tracking loop, during the stage of continuous tracking of the service segment's message sampling signal stream, the first bit decision module determines whether to write the spreading code elements from the last two addresses of the spreading code stored in the previous bit's truncated m-sequence RAM into the first two addresses of the current bit's truncated m-sequence RAM, or to write the spreading code elements from the last three addresses of the spreading code stored in the previous bit's truncated m-sequence RAM into the first three addresses of the current bit's truncated m-sequence RAM; after the first bit decision module makes the decision, the truncated m-sequence generation module generates the spreading code required for despreading the current information bit and writes it into the truncated sequence RAM in address order; S37, the lead-instant-lag code oscillator counts the enable signal for generating the instant code, and the accumulated value is recorded as m1_cnt; according to the frame structure of BeiDou short messages, the number of bits at the service end is a fixed value P1 for global short messages; according to the following calculation formula, when m1_cnt counts to m1_cnt_MAX, the truncated m-sequence generation module generates a truncated m2 sequence, which is XORed with the truncated m1 sequence to form a Gold sequence. Afterwards, the spreading code element output by the truncated m-sequence generation module to the truncated sequence RAM is the Gold sequence, not the truncated m1 sequence output during the service segment; subsequently, based on the tracking loop and the first bit decision module, the sampled data stream of the short message segment is continuously tracked; the value of m1_cnt_MAX is given by the following formula: chiprate is the pseudocode rate, bitrate is the bit rate, and P1 is the number of bits in the global short message service terminal. The generator polynomial of the truncated m2 sequence has been determined, and its initial phase information is contained in the service segment. After the short message decoding module solves the problem, it inputs the initial phase into the tracking module. After the short message decoding module completes the tracking of all bits of the global short message, it outputs an end signal, clears all state machines, and the state machines of each module control the clearing of all their internal registers.

8. The design method of a Beidou short message receiver based on FPGA according to claim 1, characterized in that: S3 specifically includes the following steps: the tracking process for short messages in the BeiDou region: S31, the quadrature demodulation module sends the demodulated I-channel and Q-channel demodulated signals to the lead-instant-hysteresis code despreading module; S32, after receiving the pseudo-code phase input from the capture module, the sequence filling unit generates the code address corresponding to the spreading code required for despreading the current information bits; simultaneously, the truncated m-sequence generation module needs to generate a spreading code of length codelen_head+1 and write it into the truncated sequence RAM in address order; the reason why the truncated m-sequence generation module generates an extra spreading code is to prevent the problem of not being able to find the corresponding spreading code when addressing the lcode, which lags behind the immediate code by 0.5 chips; the value of codelen_head is given by the following formula: chiprate is the pseudocode rate, and bitrate_head is the information rate given in the synchronization header of the area short message. The lead-instant-lag code oscillator selects from the truncated sequence RAM according to the code address and outputs the instant code pcode, the lead code ecode, and the lag code lcode; it performs sequence correlation with the input I-channel and Q-channel demodulated signals to obtain correlation results I_E, I_P, I_L, Q_E, Q_P, and Q_L; the lead-instant-lag code despreading module outputs the correlation results to the tracking loop, which consists of a frequency synchronization loop and a timing synchronization loop; the carrier synchronization loop outputs the carrier frequency control word to the lead-instant-lag code despreading module, thereby correcting the frequency of the local carrier in the quadrature demodulation module; the timing synchronization loop corrects the pseudocode phase so that the generated local spreading code used for despreading is aligned with the code phase of the input short message data stream; S33, based on the tracking loop, during the continuous tracking of the synchronization header message sampling signal stream, the first bit decision module determines whether to write the spreading code elements from the last two addresses of the spreading code stored in the previous bit's truncated m-sequence RAM to the first two addresses of the current bit's truncated m-sequence RAM, or whether to write the spreading code elements from the last three addresses of the previous bit's truncated m-sequence RAM to the first three addresses of the current bit's truncated m-sequence RAM. After the first bit decision module makes its decision, the truncated m-sequence generation module generates the spreading code of codelen_head length required for the current information bit despreading and writes it into the truncated sequence RAM in address order. The tracking result is input into the short message decoding module for frame identifier recognition. The function of the first bit decision module is detailed in the steps of global short message tracking and will not be repeated here. S34, when a frame identifier is detected, the information rate of the service segment and the data segment is determined by the frame identifier; then the length of the spreading code of the information bits of the current service segment and the data segment is obtained by the PN code length calculation module, denoted as codelen_data; chiprate is the pseudocode rate, and bitrate_data is the information rate of the service segment and data segment obtained according to the frame identifier indication. S35 is a stage for continuous tracking of the service section message sampling signal stream, based on the tracking loop and supplemented by the function of the first bit decision module; S36, the lead-instant-hysteresis code oscillator counts the enable signal for generating the instant code, and the accumulated value is recorded as m2_cnt; the number of bits at the regional short message service end is a fixed value P2; according to the following calculation formula, when m2_cnt counts to m2_cnt_MAX, the truncated m-sequence generation module generates a truncated m2 sequence, which is XORed with the truncated m1 sequence to form a Gold sequence. After that, the spreading symbols output by the truncated m-sequence generation module to the truncated sequence RAM are changed to the Gold sequence; thereafter, the short message sampling data stream of the data segment is continuously tracked based on the tracking loop and the first bit decision module; the value of m2_cnt_MAX is given by the following formula: chiprate is the pseudocode rate, bitrate is the bit rate, and P2 is the number of bits in the regional short message service terminal. The generator polynomial of the truncated m2 sequence has been determined, and its initial phase information is contained in the service segment. After the short message decoding module solves the polynomial, it inputs the initial phase into the tracking module. After the short message decoding module completes the tracking of all bits of the short message in the region, it outputs an end signal, and the tracking of the current frame ends.

9. The design method of a Beidou short message receiver based on FPGA according to claim 1, characterized in that: S4 specifically includes the following steps: S41, the frame identifier detection module receives the despread signal and first identifies the frame identifier; when the frame identifier is identified, the short message tracking enters the service segment; for regional short messages, the frame identifier indicates the symbol rate of the current frame service segment and information segment; at the same time as the frame identifier is identified, the counter counts the received despread signal, and when the counter's accumulated value equals the length, the current frame reception is completed, and the frame end flag signal is output; S42, after receiving the despread signal from the tracking module, the Viterbi decoding module inputs the despread signal into the Viterbi IP core. The Viterbi IP core decodes the service segment before the short message enters the data segment. The decoding result includes the initial phase of the m2 sequence, the number length indicator, and the CRC check code. S43, the CRC check module performs CRC check on the signals of the service section and outputs the CRC check result.

10. A BeiDou short message receiver applied to the method of any one of claims 1-9, characterized in that, include: The system includes a short message sampling data buffer module, a BeiDou short message universal acquisition module, a BeiDou short message universal tracking module, and a short message decoding module; among which, The short message sampling data buffer module buffers the received BeiDou short message data stream, buffers the short message sampling data stream according to the timing requirements of the BeiDou short message general capture module and the BeiDou short message general tracking module, and outputs the buffering result; The BeiDou short message general acquisition module processes the local spread spectrum sequence and the received demodulated data stream, and uses timing control to control the data buffer of the short message sampling data buffer module to complete the acquisition of global and regional short messages, and outputs pseudo-code phase and Doppler frequency offset; When tracking global short messages, the BeiDou short message general tracking module tracks the carrier frequency and pseudocode phase of the message sampling data through a frequency synchronization loop and a timing synchronization loop, and completes the despreading of the short message sampling data. It selects the local spreading sequence through a lead-instant-lag code oscillator module, and completes the generation of the truncated m1 sequence spreading code and Gold sequence through the function of the pseudocode switching controller, as well as the iteration of the carrier tracking loop and the timing synchronization loop. Finally, it completes the continuous and stable tracking of the short message sampling data and outputs the despreading result to the short message decoding module. The short message decoding module decodes the service segment, performs CRC verification, and outputs the frame end flag signal, the initial phase of the m2 sequence, and the valid signal of the CRC verification result.

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