A preparation method of LBD-MOSFET based on new ion implantation

Abstract

The application discloses a preparation method of LBD-MOSFET based on a new ion implantation, and comprises the following steps: providing a silicon carbide N-type epitaxial wafer; the silicon carbide N-type epitaxial wafer comprises a current expansion layer; a first P-well region and a second P-well region are respectively formed on the MOSFET side and the LBD side of the current expansion layer through multiple times of Al ion implantation; a first P+ source region and a second P+ source region are respectively formed in the first P-well region and the second P-well region; a first N+ source region and a second N+ source region are respectively formed in the first P-well region and the second P-well region; wherein the second P-well region is N-type doped in a first depth range and is P-type uniformly doped in a second depth range, and the second depth range is larger than the first depth range; a gate oxide layer is grown on the surface of the silicon carbide N-type epitaxial wafer; a split polysilicon gate, a source and a drain are formed on the surface of the gate oxide layer, and the LBD-MOSFET is formed. The application can reduce the damage caused by ion implantation.

Description

Technical Field

[0001] This invention belongs to the field of wide bandgap semiconductor manufacturing technology, specifically relating to a novel method for fabricating LBD-MOSFETs based on ion implantation. Background Technology

[0002] Compared to Si bipolar devices, SiC MOSFETs, with their unipolar conduction characteristic, offer superior switching performance and low power loss, making them promising for high-frequency applications. In many power electronics applications, such as motor drives, freewheeling diodes are required for current flow. The industry typically uses anti-parallel Schottky diodes, but this increases device size and cost, while also introducing parasitic inductance, limiting the operating frequency of the SiC MOSFET. Directly operating the MOSFET in the third quadrant can solve this problem; however, the high body diode forward voltage drop and bipolar degradation effect of SiC MOSFETs result in high losses and device degradation when used for freewheeling in the third quadrant. Therefore, LBD-MOSFETs are currently more commonly used.

[0003] The PN junction formed by the N-base region and P-well region of the LBD-MOSFET depletes the charge in the N-base layer, causing band bending and creating a low electron barrier channel from the N-CSL region to the N+ source region. Therefore, the LBD turns on before the body diode, effectively reducing the conduction loss in the third quadrant. At the same time, the LBD and body diode are connected in parallel, forming a source-drain path through the N-base region after the LBD is turned on. Due to the presence of the epitaxial layer and substrate resistance, the voltage drop from the N+ source region to the N- epitaxial layer is reduced, further suppressing the conduction of the body diode and avoiding the bipolar degradation effect caused by the conduction of the body diode.

[0004] However, compared with traditional MOSFETs, LBD-MOSFETs require an additional ion implantation into the N-base region during fabrication, which not only damages the crystal structure again but also increases the process cost and the complexity of the fabrication process. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a novel method for fabricating LBD-MOSFETs based on ion implantation. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a novel method for fabricating LBD-MOSFETs based on ion implantation, comprising:

[0007] A silicon carbide N-type epitaxial wafer is provided; the silicon carbide N-type epitaxial wafer comprises, from bottom to top, a SiCN+ substrate, an N- epitaxial layer and a current spreading layer;

[0008] By repeatedly implanting Al ions, a first P-well region and a second P-well region were fabricated on the MOSFET side and LBD side of the current spread layer, respectively.

[0009] A first P+ source region and a second P+ source region are fabricated in the first P-well region and the second P-well region, respectively. A first N+ source region is fabricated on the side of the first P+ source region near the second P-well region, and a second N+ source region is fabricated on the side of the second P+ source region near the first P-well region. The second P-well region is N-type doped in a first depth range and uniformly doped with P-type in a second depth range, wherein the second depth range is greater than the first depth range.

[0010] A gate oxide layer is grown on the surface of the silicon carbide N-type epitaxial wafer;

[0011] A split polysilicon gate, source, and drain are fabricated on the surface of the gate oxide layer to form the LBD-MOSFET.

[0012] In one embodiment of the present invention, the step of fabricating a first P-well region and a second P-well region on the MOSFET side and LBD side of the current spread layer respectively by multiple Al ion implantations includes:

[0013] A uniformly doped first P-well region is formed on the MOSFET side of the current spreading layer by a first preset number of Al ion implantations.

[0014] A second P-well region is formed on the LBD side of the current-spreading layer by a second predetermined number of Al ion implantations; wherein...

[0015] The first P-well region and the second P-well region have the same depth, which is 0.8 μm, and the first depth ranges from 0 to 0.15 μm.

[0016] In one embodiment of the present invention, the step of forming a uniformly doped first P-well region on the MOSFET side of the current spreading layer by a first predetermined number of Al ion implantations includes:

[0017] A uniformly doped first P-well region is formed on the MOSFET side of the current spread layer through seven Al ion implantations.

[0018] In one embodiment of the present invention, the implantation energies of the first to seventh Al ion implantations are 70 keV, 130 keV, 200 keV, 300 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses of the first to seventh Al ion implantations are 1.17 × 10⁻⁶, respectively.13 cm -3 1.55×10 13 cm -3 1.90×10 13 cm -3 2.40×10 13 cm -3 2.00×10 13 cm -3 1.60×10 13 cm -3 and 4.10×10 13 cm -3 .

[0019] In one embodiment of the present invention, the step of forming a second P-well region on the LBD side of the current spread layer by a second predetermined number of Al ion implantations includes:

[0020] A second P-well region is formed on the LBD side of the current spread layer through five Al ion implantations.

[0021] In one embodiment of the present invention, the implantation energies of the first to fifth Al ion implantations are 300 keV, 350 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses of the first to fifth Al ion implantations are 1.39 × 10⁻⁶, respectively. 13 cm -3 6.55×10 12 cm -3 1.75×10 13 cm -3 1.60×10 13 cm -3 and 4.00×10 13 cm -3 .

[0022] In one embodiment of the present invention, the doping concentration within the second depth range of both the first P-well region and the second P-well region is the same, which is 2.1 × 10⁻⁶. 18 cm -3 .

[0023] In one embodiment of the present invention, in the direction from the first P-well region to the second P-well region, the length of the channel formed in the first P-well region is the same as the length of the N-base region formed in the second P-well region.

[0024] In one embodiment of the present invention, the step of forming the LBD-MOSFET by fabricating a split polysilicon gate, source, and drain on the surface of the gate oxide layer includes:

[0025] Polysilicon is deposited and etched on the surface of the gate oxide layer by chemical vapor deposition to form a split polysilicon gate; the split polysilicon gate includes a first gate on the MOSFET side and a second gate on the LBD side, wherein, along the direction perpendicular to the plane of the SiC N+ substrate, the orthogonal projections of the first gate and the second gate respectively cover the orthogonal projection of the first P-well channel and the orthogonal projection of the N-base region in the second P-well region;

[0026] Metal is deposited in the source and drain regions to form ohmic contacts, forming the source and drain electrodes respectively, thus obtaining the fabricated LBD-MOSFET; wherein, along the direction perpendicular to the plane of the SiC N+ substrate, the orthogonal projections of the first gate and the second gate respectively cover the orthogonal projections of the first P-well channel and the N-base region in the second P-well, the orthogonal projection of the first source covers the orthogonal projection of the first P+ source region and part of the orthogonal projection of the first N+ source region, the orthogonal projection of the second source covers the orthogonal projection of the second P+ source region and part of the orthogonal projection of the second N+ source region, and the drain electrode is located on the side of the SiC N+ substrate away from the N-epitaxial layer.

[0027] In one embodiment of the present invention, the second gate is shorted to the second source to form an S-Gate.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] This invention provides a novel LBD-MOSFET fabrication method based on ion implantation. This method involves multiple Al ion implantations to create a first P-well region and a second P-well region on both the MOSFET and LBD sides of the current spread layer, respectively. Within a first depth range of the second P-well region, the concentration of P-type ions (Al ions) is lower than the concentration of N-type ions in the current spread layer. In other words, the second P-well region is N-type doped within the first depth range and uniformly doped with the same P-type doping concentration as the first P-well region within the second depth range. The doping concentration below this depth remains consistent with that of the first P-well region. Thus, after the second P+ source region and the second N+ source region are fabricated within the second P-well region, a natural N-base region can be formed within the second P-well region. This simplifies the process flow, reduces damage caused by ion implantation, thereby increasing production capacity and lowering production costs.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1This is a flowchart of a novel ion implantation-based LBD-MOSFET fabrication method provided in an embodiment of the present invention;

[0032] Figures 2a-2h This is a schematic diagram of the LBD-MOSFET fabrication method based on novel ion implantation provided in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the longitudinal ion concentration in the first P-well region provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the longitudinal ion concentration in the second P-well region provided in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0036] Figure 1 This is a flowchart of a novel ion implantation-based LBD-MOSFET fabrication method provided in an embodiment of the present invention. Figures 2a-2h This is a schematic diagram of a novel ion implantation-based LBD-MOSFET fabrication method provided in an embodiment of the present invention. Figure 1 , 2a As shown in ~2h, this embodiment of the invention provides a novel method for fabricating LBD-MOSFETs based on ion implantation, comprising:

[0037] S1. A silicon carbide N-type epitaxial wafer 1 is provided; the silicon carbide N-type epitaxial wafer 1 includes, from bottom to top, a SiC N+ substrate 11, an N- epitaxial layer 12 and a current spreading layer 13;

[0038] S2. Through multiple Al ion implantations, a first P-well region 2 and a second P-well region 3 are fabricated on the MOSFET side and LBD side of the current extension layer 13, respectively.

[0039] S3. A first P+ source region 4 and a second P+ source region 5 are fabricated in the first P-well region 2 and the second P-well region 3, respectively. A first N+ source region 6 is fabricated on the side of the first P+ source region 4 near the second P-well region 3, and a second N+ source region 7 is fabricated on the side of the second P+ source region 5 near the first P-well region 2. The second P-well region 3 is N-type doped in the first depth range and uniformly doped with P-type in the second depth range, and the second depth range is greater than the first depth range.

[0040] S4. A gate oxide layer is grown on the surface of silicon carbide N-type epitaxial wafer 1;

[0041] S5. A split polysilicon gate G, source S, and drain D are fabricated on the surface of the gate oxide layer to form an LBD-MOSFET.

[0042] Specifically, a silicon carbide N-type epitaxial wafer 1 is first provided and subjected to RCA (wet chemical cleaning) cleaning to remove organic and inorganic contaminants from the epitaxial surface. For example... Figure 2a As shown, the silicon carbide N-type epitaxial wafer 1 comprises, from bottom to top, a SiC N+ substrate 11, an N- epitaxial layer 12, and a current spreading layer 13, wherein the doping concentration of the SiC N+ substrate 11 is 8 × 10⁻⁶. 19 cm -3 The thickness is 100 μm, and the doping concentration of the N-epitaxial layer 12 is 5 × 10⁻⁶. 14 cm -3 The thickness is 10 μm, and the doping concentration of the current spreading layer 13 is 9 × 10⁻⁶. 16 cm -3 .

[0043] It should be noted that, Figures 2a-2g The SiC N+ substrate 11 is not drawn according to its actual thickness; it is only used to illustrate the location of the SiC N+ substrate 11 through the attached diagram.

[0044] Optionally, in this embodiment, two P-well regions are formed in the current spreading layer 13 by multiple Al ion implantations, wherein the first P-well region 2 is located on the MOSFET side of the current spreading layer 13. Figure 2b From the perspective shown, on the left side, the second P-well region 3 is located on the LBD side of the current spreading layer 13. Figure 2c The right side is shown from the indicated perspective. During multiple Al ion implantations, the Al ion implantation concentration can be adjusted to form N-type doping in the second P-well region 3 on the LBD side within a first depth range and uniform P-type doping within a second depth range. In this embodiment, the "depth" in the first and second depth ranges refers to... Figure 2c From the shown perspective, the depth of the second P-well region 3 along the direction from the current spreading layer 13 to the SiC N+ substrate 11, that is, the first depth range of the second P-well region 3 is actually above the second depth range of the second P-well region 3, i.e. Figure 2c As shown by the dashed line.

[0045] Furthermore, through multiple Al ion implantations, a first P+ source region 4 and a second P+ source region 5 are formed in the first P-well region 2 and the second P-well region 3, respectively. Through multiple N ion implantations, a first N+ source region 6 is formed on the side of the first P+ source region 4 near the second P-well region 3, and a second N+ source region 7 is formed on the side of the second P+ source region 5 near the first P-well region 2. Annealing is then performed, which allows the natural N-base region required for subsequent formation to be formed in the second P-well region 3, thereby simplifying the process and reducing the damage caused by ion implantation.

[0046] As an optional implementation, the first and second P+ source regions and the first and second N+ source regions are formed by multiple Al and N ion implantations at 500°C, with an implantation angle of 7°, and the resulting junction depth is 0.1µm to 0.2µm.

[0047] In steps S4 and S5, a gate oxide layer with a thickness of 60 nm is grown on the surface of the silicon carbide N-type epitaxial wafer 1 by dry oxidation, followed by oxidation annealing at a temperature of 300 °C for 60 min. Finally, a split polysilicon gate (G), source (S), and drain (D) are fabricated on the surface of the gate oxide layer to form an LBD-MOSFET.

[0048] Optionally, step S2, which involves fabricating a first P-well region 2 and a second P-well region 3 on the MOSFET side and LBD side of the current spreading layer 13 respectively through multiple Al ion implantations, includes:

[0049] S201. A uniformly doped first P-well region 2 is formed on the MOSFET side of the current spreading layer 13 by Al ion implantation for a first preset number of times.

[0050] S202, A second P-well region 3 is formed on the LBD side of the current extension layer 13 by a second preset number of Al ion implantations; wherein...

[0051] The first P-well region 2 and the second P-well region 3 have the same depth, both being 0.8 μm, with the first depth ranging from 0 to 0.15 μm.

[0052] In this step, a uniformly doped first P-well region 2 is first formed by Al ion implantation for a first preset number of times. Then, a second P-well region 3 of the same depth is formed by Al ion implantation for a second preset number of times. Optionally, the depth of both the first P-well region 2 and the second P-well region 3 is 0.8 μm. The doping concentration of the second P-well region 3 in the depth range of 0 to 0.15 μm is lower than the doping concentration of the current spreading layer 13, while the doping concentration in the depth range of 0.15 to 0.8 μm is the same as the doping concentration of the first P-well region 2 on the MOSFET side, which is 2.1 × 10⁻⁶. 18 cm -3 Next, after creating N+ source regions and P+ source regions in the two P-well regions respectively, a natural N-base region can be formed in the second P-well region 3.

[0053] It should be noted that, in the direction from the first P-well region 2 to the second P-well region 3, the length of the channel formed in the first P-well region 2 is the same as the length of the N-base region formed in the second P-well region 3, optionally both being 0.5µm, which facilitates the operation of the process flow. Of course, in practice, the channel length and the length of the N-base region can be flexibly adjusted according to performance requirements, and this application does not limit this.

[0054] In addition, there is actually a very thin depletion layer between the first depth range and the second depth range in the second P-well region, but since the present invention does not involve the depletion layer, the depletion layer is not described in detail.

[0055] Step S201, which involves forming a uniformly doped first P-well region 2 on the MOSFET side of the current extension layer 13 through a first preset number of Al ion implantations, includes:

[0056] A first P-well region 2 with uniform doping is formed on the MOSFET side of the current extension layer 13 by seven Al ion implantations.

[0057] Optionally, the implantation energy gradually increases with the number of Al ion implantations. The implantation energies for the first to seventh Al ion implantations are 70 keV, 130 keV, 200 keV, 300 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses for the first to seventh Al ion implantations are 1.17 × 10⁻⁶. 13 cm -3 1.55×10 13 cm -3 1.90×10 13 cm -3 2.40×10 13 cm-3 2.00×10 13 cm -3 1.60×10 13 cm -3 and 4.10×10 13 cm -3 The implantation energy and dosage during the seven Al ion implantation processes are detailed in Table 1 below:

[0058] Table 1 Ion implantation process parameters for the first P-well region

[0059]

[0060]

[0061] Step S202, the step of forming a second P-well region 3 on the LBD side of the current extension layer 13 by Al ion implantation for a second preset number of times, includes:

[0062] A second P-well region 3 is formed on the LBD side of the current extension layer 13 by five Al ion implantations.

[0063] During ion implantation, the implantation energy can be gradually increased with the number of Al ion implantations. The implantation energies for the first to fifth Al ion implantations are 300 keV, 350 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses for the first to fifth Al ion implantations are 1.39 × 10⁻⁶. 13 cm -3 6.55×10 12 cm -3 1.75×10 13 cm -3 1.60×10 13 cm -3 and 4.00×10 13 cm -3 The implantation energy and dosage during the five Al ion implantation processes are shown in Table 2 below:

[0064] Table 2 Ion implantation process parameters for the second P-well region

[0065] Inject elements Energy injected (keV) <![CDATA[Injection dose (cm -3 )]]> Al 300 <![CDATA[1.39x 10 13 ]]> Al 350 <![CDATA[6.55x 10 12 ]]> Al 400 <![CDATA[1.75x 10 13 ]]> Al 500 <![CDATA[1.60x 10 13 ]]> Al 600 <![CDATA[4.00x 10 13 ]]>

[0066] Figure 3 This is a schematic diagram of the longitudinal ion concentration in the first P-well region provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the longitudinal ion concentration in the second P-well region provided in an embodiment of the present invention. Figure 3-4As shown, the horizontal axis represents the depth of the two P-well regions, and the vertical axis represents the doping concentration. It can be seen that the first P-well region is uniformly doped throughout the entire depth range, while the second P-well region is obviously uniformly doped only after the depth is greater than the first depth range.

[0067] It should be understood that during the ion implantation process of the first P-well region 2 and the second P-well region 3, the number of implantations, the implantation energy, and the implantation dose can be flexibly adjusted, and this application does not limit them.

[0068] As an optional implementation, both P-well regions on the MOSFET side and the LBD side are formed by multiple Al ion implantations at 500°C, with an implantation angle of 7°, and a junction depth of 0.7µm to 0.9µm.

[0069] Further, step S5, which involves fabricating a split polysilicon gate G, source S, and drain D on the surface of the gate oxide layer to form an LBD-MOSFET, includes:

[0070] S501. Polysilicon is deposited and etched on the surface of the gate oxide layer by chemical vapor deposition to form a split polysilicon gate G. The split polysilicon gate G includes a first gate G1 located on the MOSFET side and a second gate G2 located on the LBD side, and the source includes a first source S1 located on the MOSFET side and a second source S2 located on the LBD side.

[0071] S502. Deposit metal in the source and drain regions and form ohmic contacts to form source S and drain D, respectively, to obtain the fabricated LBD-MOSFET; wherein, along the direction perpendicular to the plane where the SiC N+ substrate 11 is located, the orthogonal projections of the first gate G1 and the second gate G2 respectively cover the orthogonal projections of the channel in the first P-well region 2 and the N-base region in the second P-well region 3, the orthogonal projection of the first source S1 covers the orthogonal projection of the first P+ source region 4 and part of the orthogonal projection of the first N+ source region 6, the orthogonal projection of the second source S2 covers the orthogonal projection of the second P+ source region 5 and part of the orthogonal projection of the second N+ source region 7, and the drain is located on the side of the SiC N+ substrate 11 away from the N-epitaxial layer 12.

[0072] It should be noted that the present invention does not limit the dimensions of the first gate G1 and the second gate G2 in the horizontal direction. Figure 2g Used only to represent two split gates.

[0073] Optionally, in step S501, the temperature of chemical vapor deposition is 600°C and the thickness of the deposited polycrystalline silicon is 400 nm.

[0074] In this embodiment, the second gate G2 is shorted to the second source S2 to form an S-Gate. Finally, the metal is annealed at a temperature of 95°C for 90 seconds.

[0075] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0076] This invention provides a novel LBD-MOSFET fabrication method based on ion implantation. This method involves multiple Al ion implantations to create a first P-well region and a second P-well region on both the MOSFET and LBD sides of the current spread layer, respectively. Within a first depth range of the second P-well region, the concentration of P-type ions (Al ions) is lower than the concentration of N-type ions in the current spread layer. In other words, the second P-well region is N-type doped within the first depth range and uniformly doped with the same P-type doping concentration as the first P-well region within the second depth range. The doping concentration below this depth remains consistent with that of the first P-well region. Thus, after the second P+ source region and the second N+ source region are fabricated within the second P-well region, a natural N-base region can be formed within the second P-well region. This simplifies the process flow, reduces damage caused by ion implantation, thereby increasing production capacity and lowering production costs.

[0077] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0079] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0080] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A novel method for fabricating LBD-MOSFETs based on ion implantation, characterized in that, include: Provide a silicon carbide N-type epitaxial wafer; The silicon carbide N-type epitaxial wafer comprises, from bottom to top, a SiC N+ substrate, an N- epitaxial layer, and a current spreading layer; A first P-well region and a second P-well region are fabricated on the MOSFET side and LBD side of the current spreading layer, respectively, through multiple Al ion implantations; including: The steps of fabricating a first P-well region and a second P-well region on the MOSFET side and LBD side of the current spread layer through multiple Al ion implantations include: A uniformly doped first P-well region is formed on the MOSFET side of the current spreading layer through a first preset number of Al ion implantations; wherein the first preset number of implantations is seven, and the implantation energies of the first to seventh Al ion implantations are 70 keV, 130 keV, 200 keV, 300 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses of the first to seventh Al ion implantations are 1.17 × 10⁻⁶, respectively. 13 cm -3 1.55×10 13 cm -3 1.90×10 13 cm -3 2.40×10 13 cm -3 2.00×10 13 cm -3 1.60×10 13 cm -3 and 4.10×10 13 cm -3 ; A second P-well region is formed on the LBD side of the current-spreading layer by a second predetermined number of Al ion implantations; wherein... The first P-well region and the second P-well region have the same depth, both being 0.8 μm; A first P+ source region and a second P+ source region are fabricated in the first P-well region and the second P-well region, respectively. A first N+ source region is fabricated on the side of the first P+ source region near the second P-well region, and a second N+ source region is fabricated on the side of the second P+ source region near the first P-well region. The second P-well region is N-type doped in a first depth range and uniformly doped with P-type in a second depth range. The second depth range is greater than the first depth range. The first depth range is 0 to 0.15 μm. A gate oxide layer is grown on the surface of the silicon carbide N-type epitaxial wafer; A split polysilicon gate, source, and drain are fabricated on the surface of the gate oxide layer to form the LBD-MOSFET.

2. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 1, characterized in that, The step of forming a second P-well region on the LBD side of the current spread layer by a second predetermined number of Al ion implantations includes: A second P-well region is formed on the LBD side of the current spread layer through five Al ion implantations.

3. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 2, characterized in that, The implantation energies for the first to fifth Al ion implantations were 300 keV, 350 keV, 400 keV, 500 keV, and 600 keV, respectively, and the implantation doses for the first to fifth Al ion implantations were 1.39 × 10⁻⁶. 13 cm -3 6.55×10 12 cm -3 1.75×10 13 cm -3 1.60×10 13 cm -3 and 4.00×10 13 cm -3 .

4. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 1, characterized in that, The doping concentration within the second depth range of both the first and second P-well regions is the same, which is 2.1 × 10⁻⁶. 18 cm -3 .

5. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 4, characterized in that, In the direction from the first P-well region to the second P-well region, the length of the channel formed in the first P-well region is the same as the length of the N-base region formed in the second P-well region.

6. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 1, characterized in that, The step of forming the LBD-MOSFET by fabricating a split polysilicon gate, source, and drain on the surface of the gate oxide layer includes: Polysilicon is deposited and etched on the surface of the gate oxide layer by chemical vapor deposition to form a split polysilicon gate; the split polysilicon gate includes a first gate located on the MOSFET side and a second gate located on the LBD side. Metal is deposited in the source and drain regions to form ohmic contacts, forming the source and drain electrodes respectively, thus obtaining the fabricated LBD-MOSFET; wherein, along the direction perpendicular to the plane of the SiC N+ substrate, the orthogonal projections of the first gate and the second gate respectively cover the orthogonal projections of the first P-well channel and the N-base region in the second P-well, the orthogonal projection of the first source covers the orthogonal projection of the first P+ source region and part of the orthogonal projection of the first N+ source region, the orthogonal projection of the second source covers the orthogonal projection of the second P+ source region and part of the orthogonal projection of the second N+ source region, and the drain electrode is located on the side of the SiC N+ substrate away from the N-epitaxial layer.

7. The method for fabricating LBD-MOSFETs based on novel ion implantation according to claim 6, characterized in that, The second gate is shorted to the second source to form an S-Gate.

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