Thin film transistor and method of manufacturing the same

Abstract

The application provides a TFT and a preparation method thereof. The TFT comprises a wall structure, a circuit layout layer, and a buffer layer arranged between the wall structure and the circuit layout layer, wherein the buffer layer and the circuit layout layer are wrapped on the upper surface and the side surface of the wall structure, and the side surface is perpendicular to the thickness direction of the wall structure. Compared with the TFT with a planar structure, since the area of the circuit layout layer is extended from the upper surface of the wall structure to the side surface of the wall structure, the TFT occupies a smaller area on the plane, so as to meet the requirement of high pixel density, and the performance of the TFT is not affected due to the reduction of the total area of the circuit layout layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a thin film transistor (TFT) and a method for fabricating the same. Background Technology

[0002] In the display industry, especially in the fields of augmented reality (AR) and virtual reality (VR) display technologies, the demand for high pixel density (pixels per inch, PPI) continues to increase. Therefore, improving the structure of transistors in displays to increase the PPI has become a problem that needs to be solved. Summary of the Invention

[0003] This application provides a TFT and its fabrication method, which can improve the structure of transistors in a display to improve the display's PPI.

[0004] In a first aspect, a TFT is provided, including a wall structure, a circuit board layer, and a buffer layer disposed between the wall structure and the circuit board layer, wherein the buffer layer and the circuit board layer cover the upper surface and side surface of the wall structure, and the side surface is perpendicular to the thickness direction of the wall structure.

[0005] The TFT provided in this application includes a wall structure. By setting the circuit board layer to cover the upper surface and sides of the wall structure, a three-dimensional TFT structure is formed. Compared with a planar TFT structure, because the area of ​​the circuit board layer extends from the upper surface of the wall structure to the sides of the wall structure, the TFT occupies a smaller area on the plane, thereby meeting the requirements of high PPI, and the performance of the TFT is not affected by reducing the total area of ​​the circuit board layer.

[0006] In some possible implementations, along a direction away from the wall structure, the circuit board layer sequentially includes a semiconductor layer, an insulating layer, and an electrode layer, the semiconductor layer being formed of an oxide semiconductor material, the electrode layer including a gate, a source, and a drain, and the insulating layer used to isolate the gate and the semiconductor layer.

[0007] In this implementation, the upper surface and side surfaces of the wall structure are sequentially covered with a buffer layer, an oxide semiconductor layer, an insulating layer, and an electrode layer. The electrode layer includes the gate, source, and drain of the TFT, and the gate and the semiconductor layer are isolated by the insulating layer, thereby forming a three-dimensional TFT structure.

[0008] In some possible implementations, the semiconductor layer is further provided with conductive regions for connecting the gate and the source, and for connecting the gate and the drain.

[0009] Since both the source and drain are located on the upper surface of the semiconductor layer, conductive channels can be formed between the source and gate, and between the drain and gate, by setting a conductive region on the semiconductor layer. Otherwise, it would be equivalent to having two resistors connected in series in the TFT, which would reduce the on-state current by an order of magnitude and thus affect the performance of the TFT.

[0010] The material of the wall structure can be flexibly selected as a metallic material or a non-metallic material according to the actual situation. The non-metallic material includes, for example, at least one of Si, SiOx, parylene, and polyimide (PI).

[0011] In some possible implementations, the wall structure is made of a metallic material, and the source electrode in the circuit board layer is connected to the wall structure.

[0012] In this implementation, when the wall structure is made of a metallic material, it can be connected to the gate of the TFT to form a dual-gate device; or, it can be connected to the source of the TFT to form a BS structure device. This expands the application scenarios of the TFT in this application.

[0013] In some possible implementations, the planar size of the TFT is less than or equal to 3 μm.

[0014] The TFT with the three-dimensional structure of this application can effectively reduce its area on a plane. For example, the length and width dimensions occupied by the TFT on the plane are less than 3 μm, and the plane size of the TFT can even be reduced to the nanometer level, which is very beneficial to improving the PPI of the display screen.

[0015] In a second aspect, a method for fabricating a TFT is provided, the method comprising: fabricating a wall structure; and sequentially fabricating a buffer layer and a circuit board layer on the wall structure, such that the buffer layer and the circuit board layer cover the upper surface and side surface of the wall structure, the side surface being perpendicular to the thickness direction of the wall structure.

[0016] In this application, a wall structure is provided, and a buffer layer and a circuit board layer are sequentially fabricated on the wall structure, such that the buffer layer and the circuit board layer cover the upper surface and side surface of the wall structure. Compared to a planar TFT structure, because the area of ​​the circuit board layer extends from the upper surface of the wall structure to the side surface, the TFT can occupy a smaller area on the plane, thereby meeting the high PPI requirement, without reducing the total area of ​​the circuit board layer and affecting the performance of the TFT.

[0017] In some possible implementations, the step of sequentially fabricating a buffer layer and a circuit board layer on the wall structure includes: sequentially depositing a buffer layer, a semiconductor layer, and an insulating layer on the upper surface and side surface of the wall structure, wherein the semiconductor layer is formed of an oxide semiconductor material; etching the portion of the insulating layer corresponding to the upper surface of the wall structure to form a patterned insulating layer; depositing an electrode layer on the outer surface of the patterned insulating layer; etching the portion of the electrode layer corresponding to the upper surface of the wall structure to form a gate, a source, and a drain, wherein the insulating layer is used to isolate the gate and the semiconductor layer.

[0018] In this implementation, a buffer layer, an oxide semiconductor layer, and an insulating layer are sequentially deposited on the upper and side surfaces of the wall structure. A patterned insulating layer is then etched to form the insulating layer. An electrode layer is deposited on the outer surface of the insulating layer, and the gate, source, and drain of the TFT are formed on the electrode layer by etching, thereby obtaining a three-dimensional TFT structure.

[0019] In some possible implementations, the step of sequentially depositing a buffer layer, a semiconductor layer, and an insulating layer on the upper surface and side surface of the wall structure includes: sequentially depositing a buffer layer and a semiconductor layer on the upper surface and side surface of the wall structure; etching the portion of the semiconductor layer corresponding to the upper surface of the wall structure to form a patterned semiconductor layer; and depositing the insulating layer on the outer surface of the patterned semiconductor layer.

[0020] Depending on the actual situation, the semiconductor layer can be patterned to appropriately reduce its area, so that the entire surface does not need to be covered by the semiconductor layer.

[0021] In some possible implementations, the method further includes: performing a conductor-forming process on the semiconductor layer to form a conductor-forming region, the conductor-forming region being used to conduct the source and the drain.

[0022] Since both the source and drain are located on the upper surface of the semiconductor layer, conductive channels can be formed between the source and gate, and between the drain and gate, by setting a conductive region on the semiconductor layer. Otherwise, it would be equivalent to having two resistors connected in series in the TFT, which would reduce the on-state current by an order of magnitude and thus affect the performance of the TFT.

[0023] The material of the wall structure can be flexibly selected as a metallic material or a non-metallic material according to the actual situation. The non-metallic material includes, for example, at least one of Si, SiOx, parylene, and PI.

[0024] In some possible implementations, the wall structure is made of a metallic material, and the method further includes etching the buffer layer to form through-holes, so that the source in the circuit board layer is connected to the wall structure via the through-holes in the buffer layer.

[0025] In this implementation, when the wall structure is made of a metallic material, it can be connected to the gate of the TFT to form a dual-gate device; or, it can be connected to the source of the TFT to form a BS structure device. This expands the application scenarios of the TFT in this application.

[0026] In some possible implementations, the planar size of the TFT is less than or equal to 3 μm.

[0027] The TFT with the three-dimensional structure of this application can effectively reduce its area on a plane. For example, the length and width dimensions occupied by the TFT on the plane are less than 3 μm, and the plane size of the TFT can even be reduced to the nanometer level, which is very beneficial to improving the PPI of the display screen.

[0028] Thirdly, a display panel is provided, including the TFT described in the first aspect or any possible implementation thereof.

[0029] Fourthly, a display device is provided, comprising the display panel described in the third aspect or any possible implementation thereof. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the stacked structure of a traditional planar TFT.

[0031] Figure 2 This is a schematic diagram of the structure of the TFT according to an embodiment of this application.

[0032] Figure 3 yes Figure 2 The diagram shows a possible specific structure of a TFT.

[0033] Figure 4 This is a schematic diagram of a BS structure device according to an embodiment of this application.

[0034] Figure 5 This is a schematic diagram of a dual-gate device according to an embodiment of this application.

[0035] Figure 6 This is a schematic flowchart of a method for preparing a TFT according to an embodiment of this application.

[0036] Figure 7 yes Figure 6 A schematic flowchart illustrating one possible specific implementation of the method shown.

[0037] Figure 8 yes Figure 6 and Figure 7 The diagram shows a specific process flow of the method shown.

[0038] Figure 9 yes Figure 6 and Figure 7 The diagram shows a specific process flow of the method shown. Detailed Implementation

[0039] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application, that is, this application is not limited to the described embodiments.

[0040] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0042] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0043] Figure 1 The stacked structure of a conventional planar TFT is shown. For example... Figure 1The TFT 100 shown comprises, from bottom to top, a substrate 110, a buffer layer 120, a semiconductor layer 130, an insulating layer 140, and an electrode layer 150. The semiconductor layer 130, insulating layer 140, and electrode layer 150 can be referred to as layout layers. The electrode layer 150, also known as the gate layer, is used to form the electrodes of the TFT, such as the source, drain, and gate. The insulating layer 140, also called the gate insulator (GI) layer, serves to insulate the gate from the semiconductor layer 130.

[0044] In the display industry, increasing the pixel density (PPI) can improve a display's resolution, thereby enhancing its display performance. This can be achieved by reducing the size of the TFTs (Thinker Screens) within the display, allowing more TFTs to be placed within the same area. PPI, for example, refers to the number of pixels per inch of a display screen and is an important indicator of display sharpness. Generally, the higher the PPI, the better the display quality.

[0045] like Figure 1 As shown, reducing the planar size of a TFT necessitates a corresponding reduction in the planar area of ​​the circuit board layer. This can lead to abnormal TFT performance and increase the difficulty of TFT fabrication. Particularly for oxide-based TFTs, when their length or width on the plane is reduced to 3µm, significant abnormalities in TFT characteristics occur, such as a gate voltage V0. th In situations such as negative bias or high current, if the planar size of the TFT is further reduced, not only will the short-channel effect become more pronounced, but it will also place higher demands on the equipment and challenge the limits of the process.

[0046] Therefore, this application provides a TFT and its fabrication method. By setting a wall structure and setting the circuit board layer to cover the upper surface and side surface of the wall structure, a three-dimensional TFT structure is formed. This extends the area of ​​the circuit board layer of the TFT from the upper surface of the wall structure to the side surface of the wall structure, so that the TFT occupies a smaller area on the plane, thereby meeting the high PPI requirement, and without affecting the performance of the TFT by reducing the total area of ​​the circuit board layer.

[0047] It is understood that the TFT in the embodiments of this application can also be replaced with other types of field-effect transistor (FET) devices, such as FinFETs. That is, other types of FET devices besides TFTs can also be fabricated to form similar three-dimensional structures to reduce their planar area. Furthermore, the TFT in the embodiments of this application can be an oxide-based FET device or a silicon-based FET device; in particular, it can be an oxide-based FET device.

[0048] Figure 2 The structure of a TFT according to an embodiment of this application is shown. This TFT can be applied to a display. Figure 2 As shown, the TFT 200 of this embodiment includes a wall structure 210, a circuit board layer 220, and a buffer layer 230 disposed between the wall structure 210 and the circuit board layer 220. The buffer layer 230 and the circuit board layer 220 cover the upper surface and side surface of the wall structure 210. The side surface, for example, refers to a surface perpendicular to the thickness direction of the wall structure.

[0049] like Figure 2 As shown, the X direction is the wall thickness direction, the Y direction is the wall height direction, and the Z direction is the wall width direction. Figure 2 (a) in the figure is a planar schematic diagram of the TFT along the X direction. Figure 2 (b) is a planar schematic diagram of the TFT along the Z direction. Figure 2 The TFT 200 shown includes a wall structure 210. By setting the electrode layer 223 to cover the upper surface and side surface of the wall structure 210, a three-dimensional TFT 200 is formed. The side surface refers to the surface perpendicular to the X direction, that is, the surface with the largest area on the wall structure 210, so as to maximize the total area of ​​the circuit board layer 220.

[0050] Compared to Figure 1 The TFT 100 shown has a planar structure, because Figure 2 The area of ​​the circuit board layer 220 of the TFT 200 shown extends from the upper surface of the wall structure 210 to the side of the wall structure 210, making the planar area of ​​the TFT 200 smaller, thereby meeting the high PPI requirement, and without affecting the performance of the TFT 200 by reducing the total area of ​​the circuit board layer 220.

[0051] Here, the plane refers to the plane running on the surface of the display. Correspondingly, the planar area of ​​TFT 200 refers to the area occupied by TFT 200 on a plane parallel to the surface of the display, such as the projected area of ​​TFT 200 on a plane parallel to the surface of the display.

[0052] Specifically, by reducing the planar area of ​​TFT 200, more TFTs can be placed within the same area, increasing the PPI of the display screen and improving its display performance. At the same time, since the circuit board layer 220 in TFT 200 can extend from the plane to the side of the wall structure 210, the total area of ​​the circuit board layer 220 will not decrease, ensuring that the performance of TFT 200 is not affected.

[0053] Circuit layout layer 220 refers to the integrated circuit layout, such as the layer used to define and implement the layout of various components and lines in an integrated circuit.

[0054] In some embodiments, along the direction away from the wall structure 210, the circuit board layer 220 sequentially includes a semiconductor layer 221, an insulating layer 222, and an electrode layer 223. The semiconductor layer 221 may be formed of an oxide semiconductor material, for example, the electrode layer 223 includes a gate G, a source S, and a drain D, and the insulating layer 222 is used to isolate the gate G from the semiconductor layer 221.

[0055] For example, such as Figure 3 As shown, where, Figure 3 Image (a) is a front view of TFT 200, and images (b) and (c) are cross-sectional views of TFT 200 shown in image (a) along the B-B' and A-A' directions, respectively. Circuit board layer 220 includes a semiconductor layer 221, an insulating layer 222, and an electrode layer 223. The upper surface and sides of wall structure 210 are sequentially covered with a buffer layer 230, a semiconductor layer 221, an insulating layer 222, and an electrode layer 223, thereby forming a three-dimensional TFT 200.

[0056] The material of the buffer layer 230 can be, for example, SiOx or other dielectric materials, which can play a role in mechanical buffering, chemical buffering and electrical buffering, such as relieving mechanical stress caused by material mismatch between the wall structure 210 and the semiconductor layer 221, blocking impurities in the wall structure 210 from diffusing into the semiconductor layer 221, and thus protecting the semiconductor layer 221.

[0057] Semiconductor layer 221 can also be called active (ACT) layer. The material of semiconductor layer 221 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO). That is to say, the TFT 200 in the embodiments of this application can be an oxide-based TFT.

[0058] Optionally, a conductive region may also be provided on the semiconductor layer 221 to conduct the source S and gate G of the TFT 200, and to conduct the drain D and gate G. In this way, a conductive channel can be formed between the source S and gate G, and between the drain D and gate G. Otherwise, it would be equivalent to having two resistors connected in series in the TFT 200, which would reduce the on-state current (Ion) by an order of magnitude, thereby affecting the performance of the TFT 200.

[0059] Electrode layer 223, also known as metal layer or gate layer, forms the gate (G), source (S), and drain (D) of the TFT 200 through processes such as etching. As an example, Figure 3The source S and drain D shown can be located on both sides of the insulating layer 222 along the direction Z, respectively. The gate G is located on the upper surface of the insulating layer 222 and is isolated from the semiconductor layer 221 through the insulating layer 222. The planar shape of the gate G can be consistent with the planar shape of the insulating layer 222.

[0060] The insulating layer 222 is also called the gate insulating layer (GI layer). The material of the insulating layer 222 can be, for example, SiOx or other dielectric materials.

[0061] The material of the wall structure 210 can be flexibly selected as a metallic material or a non-metallic material according to the actual situation. Non-metallic materials may include at least one of Si, SiOx, parylene, PI and other materials.

[0062] In the case where the wall structure 210 is made of metal, the wall structure 210 may optionally be connected to the gate G or source S in the circuit board layer 220 to form a dual-gate device or a base source (BS) structure device, thereby expanding the application scenarios of the TFT 200 in this embodiment.

[0063] For example, such as Figure 4 As shown, the wall structure 210 is made of metal, and the wall structure 210 is connected to the source S of the TFT 200 to form a BS structure device. Among them, Figure 4 (a) is a front view of TFT 200, and (b) and (c) are cross-sectional views of TFT 200 shown in (a) along the D-D' and A-A' directions, respectively.

[0064] For example, such as Figure 5 As shown, Figure 5 This is a top view of TFT 200 perpendicular to the Y direction. The wall structure 210 is made of metal and is connected to the gate G of TFT 200 to form a dual-gate device.

[0065] The planar dimensions of the TFT 200 in this embodiment can be significantly reduced, for example, to less than or equal to 3 μm, or even to the nanometer scale. These planar dimensions include, for example, the length and width of the TFT 200 on a plane parallel to the display screen. Because the area occupied by the TFT 200 on the plane is reduced, the PPI of the display screen can be increased by increasing the number of TFTs 200 within the same display screen area.

[0066] This application also provides a method 300 for preparing the above-mentioned TFT 200, such as... Figure 6 As shown, method 300 includes some or all of the following process steps.

[0067] In step 310, wall structure 210 is constructed.

[0068] In step 320, a buffer layer 230 and a circuit board layer 220 are sequentially fabricated on the wall structure 210, such that the buffer layer 230 and the circuit board layer 220 cover the upper surface and side surface of the wall structure 210, wherein the side surface is perpendicular to the thickness direction X of the wall structure 210.

[0069] In this embodiment, a wall structure 210 is provided, and a buffer layer 230 and a circuit board layer 220 are sequentially fabricated on the wall structure 210, such that the buffer layer 230 and the circuit board layer 220 cover the upper surface and side surface of the wall structure 210. Compared to a planar TFT 200, because the area of ​​the circuit board layer 220 extends from the upper surface of the wall structure 210 to the side surface of the wall structure 210, the TFT 200 can occupy a smaller area on the plane, thereby meeting the high PPI requirement, without reducing the total area of ​​the circuit board layer 220 and affecting the performance of the TFT 200.

[0070] The following, combined with Figures 7 to 9 The preparation process of the TFT 200 according to the embodiments of this application is described in detail.

[0071] In some embodiments, such as Figure 7 As shown, step 320 above may include steps 321 to 324.

[0072] In step 321, a buffer layer 230, a semiconductor layer 221, and an insulating layer 222 are sequentially deposited on the upper surface and side surface of the wall structure 210.

[0073] In step 322, the portion of the insulating layer 222 corresponding to the upper surface of the wall structure 210 is etched to form a patterned insulating layer 222.

[0074] In step 323, an electrode layer 223 is deposited on the outer surface of the patterned insulating layer 222.

[0075] In step 324, the portion of the electrode layer 223 corresponding to the upper surface of the wall structure 210 is etched to form the gate G, source S and drain D. The gate G and the semiconductor layer 221 are insulated and isolated by the insulating layer 222.

[0076] Alternatively, the area of ​​the semiconductor layer can be appropriately reduced by patterning, so that the entire surface of the semiconductor layer is not required to be covered. For example, in step 321, a buffer layer 230 and a semiconductor layer 221 can be sequentially deposited on the upper surface and side surface of the wall structure 210, the portion of the semiconductor layer 221 corresponding to the upper surface of the wall structure 210 is etched to form a patterned semiconductor layer 221, and an insulating layer 222 is deposited on the outer surface of the patterned semiconductor layer 221.

[0077] As an example, Figure 8 and Figure 9 It shows Figure 6 and Figure 7 The diagram shows one possible specific process for the fabrication of the TFT 200. Figure 8 and Figure 9 In steps (a) to (g) shown, the right-hand figure is a sectional view corresponding to the section line in the left-hand figure.

[0078] exist Figure 8 In step (a), the wall structure 210 is first constructed.

[0079] exist Figure 8 In step (b), a buffer layer 230 is deposited on the upper surface and sides of the wall structure 210. The material of the buffer layer 230 may be, for example, SiOx or other dielectric materials.

[0080] After that, it can be based on Figure 9 Steps (c) to (g) shown in the figure are used to form a circuit board layer 220 on the outer surface of the buffer layer 230.

[0081] exist Figure 9 In step (c), a semiconductor layer 221 is deposited on the buffer layer 230 and etched to form a patterned semiconductor layer 221.

[0082] For example, the semiconductor layer 221 can be etched so that its dimension along the Z direction is smaller than that of the wall structure 210 in the Z direction, so as to appropriately reduce its area without having to cover the entire surface of the semiconductor layer 221.

[0083] exist Figure 9 In step (d), an insulating layer 222 is deposited on the patterned semiconductor layer 221.

[0084] exist Figure 9 In step (e), the insulating layer 222 is etched to form a patterned insulating layer 222.

[0085] For example, the insulating layer 222 can be etched so that its dimension along the Z direction is smaller than that of the semiconductor layer 221 in the Z direction, thereby facilitating the formation of the source S and drain D on the semiconductor layer 221, and the formation of the gate G on the upper surface of the insulating layer 222.

[0086] This etching process can be achieved, for example, by using dry etching. As an example, in dry etching, photoresist can be coated onto the surface of the material to be etched as a mask, and photolithography can be used to transfer the desired pattern to the photoresist. Finally, the photoresist is removed, leaving the desired pattern on the material to be etched.

[0087] exist Figure 9 In step (f), an electrode layer 223 is deposited to form an outer surface of a patterned semiconductor layer 221 and an insulating layer 222.

[0088] exist Figure 9 In step (g), the electrode layer 223 is etched to form the source S, drain D, and gate G of the TFT 200. During this process, the insulating layer 222 can be etched simultaneously so that the pattern of the insulating layer 222 is identical to that of the gate G.

[0089] Optionally, in Figure 9 Following step (g), a conductor-forming process can be performed on at least a portion of the semiconductor layer 221 to form a conductor-forming region. This conductor-forming region is used to conduct the source S and gate G of the TFT 200, and to conduct the drain D and gate G. This forms a conductive channel between the source S and gate G, and between the drain D and gate G. Otherwise, it would be equivalent to having two resistors connected in series in the TFT 200, reducing Ion by an order of magnitude and thus affecting the TFT's performance.

[0090] Conducting processes can include, for example, helium plasma, argon plasma, and doping.

[0091] Through the above process steps, a three-dimensional TFT 200 can be obtained, thereby extending the area of ​​the circuit board layer 223 of the TFT 200 from the upper surface of the wall structure 210 to the side of the wall structure 210, so that the TFT 200 occupies a smaller area on the plane, thereby meeting the requirement of high PPI, and without affecting the performance of the TFT 200 by reducing the total area of ​​the circuit board layer 223.

[0092] Understandable. Figures 6 to 9 For specific details regarding the various stacked structures in the TFT 200, please refer to the aforementioned section on... Figures 2 to 5For the sake of brevity, the relevant description of the TFT 200 will not be repeated here.

[0093] The material of the wall structure 210 can be flexibly selected as a metallic material or a non-metallic material according to the actual situation. Non-metallic materials include at least one of Si, SiOx, parylene, and PI.

[0094] In some embodiments, when the wall structure 210 is made of a metallic material, the wall structure 210 can also be connected to the gate G in the circuit board layer 220.

[0095] When the wall structure 210 is made of metal, the gate G of the TFT 200 can be connected to the wall structure 210 to form a dual-gate device, or the source S of the TFT 200 can be connected to the wall structure 210 to form a BS structure device, thereby expanding the application scenarios of the TFT 200 in this application embodiment.

[0096] For example, in Figure 8 After step (b), the buffer layer 230 can be etched to form a via. Thus, during the deposition of the electrode layer 223 and its etching to form the source S, gate G, and drain D, the source S can be connected to the wall structure 210 via the via in the buffer layer, thereby forming... Figure 4 The BS device shown.

[0097] For example, the connection between the gate G and the wall structure 210 can also be achieved by adding a wall structure 210 with redundant apertures on the outside, thereby forming Figure 5 The dual-gate device is shown. However, this may lead to an increase in the area of ​​the wall structure 210, thereby affecting the planar dimensions of the TFT 200.

[0098] The planar dimensions of the TFT 200 with a three-dimensional structure fabricated based on method 300 can be significantly reduced, for example, to less than or equal to 3 μm, or even down to the nanometer scale. These planar dimensions include the length and width of the TFT 200 in a plane parallel to the display screen. Because the area occupied by the TFT 200 on the plane is reduced, the PPI of the display screen can be increased by increasing the number of TFTs 200 within the same display screen area.

[0099] This application also provides a display panel that includes the TFT 200 described in any embodiment of this application.

[0100] This application also provides a display device, such as a display screen, which includes the display panel described in any embodiment of this application.

[0101] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0102] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A thin-film transistor, characterized in that, This includes a wall structure, a circuit board layer, and a buffer layer disposed between the wall structure and the circuit board layer. The buffer layer and the circuit board layer cover the upper surface and side surface of the wall structure, and the side surface is perpendicular to the thickness direction of the wall structure. Along a direction away from the wall structure, the circuit board layer sequentially includes a semiconductor layer, an insulating layer, and an electrode layer. The electrode layer includes a gate, a source, and a drain. The insulating layer is used to isolate the gate and the semiconductor layer. The semiconductor layer is further provided with a conductor region for connecting the source and the drain.

2. The thin-film transistor according to claim 1, characterized in that, The semiconductor layer is formed of an oxide semiconductor material or a silicon-based material.

3. The thin-film transistor according to claim 1 or 2, characterized in that, The wall structure is made of metallic or non-metallic materials, and the non-metallic materials include at least one of Si, SiOx, parylene, and polyimide.

4. The thin-film transistor according to claim 3, characterized in that, The wall structure is made of metal, and the source electrode in the circuit board layer is connected to the wall structure.

5. The thin-film transistor according to claim 3, characterized in that, The wall structure is made of metal, and the gate in the circuit board layer is connected to the wall structure.

6. The thin-film transistor according to claim 1 or 2, characterized in that, The planar dimension of the thin-film transistor is less than or equal to 3 μm.

7. A method for fabricating a thin-film transistor, characterized in that, The method includes: Constructing the wall structure; A buffer layer and a circuit board layer are sequentially fabricated on the wall structure, such that the buffer layer and the circuit board layer cover the upper surface and side surface of the wall structure, and the side surface is perpendicular to the thickness direction of the wall structure; The step of sequentially fabricating a buffer layer and a circuit board layer on the wall structure includes: A buffer layer and a semiconductor layer are sequentially deposited on the upper surface and side surface of the wall structure; The portion of the semiconductor layer corresponding to the upper surface of the wall structure is etched to form a patterned semiconductor layer. An insulating layer is deposited on the outer surface of the patterned semiconductor layer; The portion of the insulating layer corresponding to the upper surface of the wall structure is etched to form a patterned insulating layer. An electrode layer is deposited on the outer surface of the patterned insulating layer; The portion of the electrode layer corresponding to the upper surface of the wall structure is etched to form the gate, source, and drain. The insulating layer is used to isolate the gate and the semiconductor layer.

8. The method according to claim 7, characterized in that, The method further includes: performing a conductor-forming process on the semiconductor layer to form a conductor-forming region, the conductor-forming region being used to conduct the source and the drain.

9. A display panel, characterized in that, The thin-film transistor includes any one of claims 1 to 6.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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