Clock synchronization method, device, system and chip

Abstract

The application discloses a clock synchronization method, device, system and chip, and the method comprises the following steps: receiving a second pulse signal and a clock synchronization protocol message; obtaining timestamp information by analyzing the clock synchronization protocol message; using a fractional frequency phase-locked loop circuit to frequency-division a first reference clock signal, thereby obtaining a plurality of first sub-clock signals; using the plurality of first sub-clock signals to sample the second pulse signal, thereby obtaining a plurality of first sampling signals; determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking first jump edges of the first sampling signals as the sampling points; and realizing clock synchronization based on the timestamp information and the plurality of first sampling values. After the fractional frequency phase-locked loop circuit is used to frequency-division the first reference clock signal, the plurality of first sub-clock signals can be used to sample the second pulse signal with higher precision, the sampling precision can be improved, and the precision of clock synchronization can be improved.

Description

Technical Field

[0001] This application relates to the field of distributed network technology, and in particular to a clock synchronization method, device, system and chip. Background Technology

[0002] A clock synchronization system can precisely synchronize the real-time clocks of various nodes in a distributed network communication system. Taking a clock synchronization system using the precision clock synchronization protocol standard for networked measurement and control systems (IEEE 1588) as an example, each node in the distributed network is equipped with a clock module and a processing module. The processing module is used to perform relevant protocol processing of IEEE 1588 messages, collect timestamps, and send the timestamps to the clock module. The clock module is used to perform clock information calculations based on the timestamps sent by the processing module, thereby adjusting its local real-time clock to achieve clock synchronization among all nodes. The clock module periodically sends timestamp information and pulse per second (PPS) information to the processing module, thus synchronizing the real-time clock of the processing module with that of the clock module.

[0003] The IEEE 1588 synchronization system has extremely high requirements for sampling accuracy, currently demanding nanosecond-level precision. The sampling accuracy of the second pulse information is a crucial factor affecting the overall accuracy of the IEEE 1588 synchronization system. This sampling accuracy is entirely dependent on the clock frequency of the sampling clock; that is, the sampling accuracy can only be improved by increasing the clock frequency. For example, to meet the accuracy requirements of the IEEE 1588 synchronization system, a sampling clock with a frequency of 1 GHz is needed to achieve a sampling accuracy of 1 ns for the second pulse information. However, with current clock manufacturing processes, implementing a 1 GHz clock is prohibitively expensive, while lower-cost clocks often fail to meet the accuracy requirements of the IEEE 1588 synchronization system. Therefore, how to ensure high sampling accuracy at lower clock frequencies is a pressing issue for researchers in this field. Summary of the Invention

[0004] This application provides a clock synchronization method, apparatus, system, and chip that can ensure high-precision sampling when the sampling clock frequency is low.

[0005] In a first aspect, this application provides a clock synchronization method, comprising: receiving a second pulse signal and a clock synchronization protocol message, parsing the clock synchronization protocol message to obtain timestamp information; dividing a first reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; sampling the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; determining multiple first sampled values ​​of the multiple first sampled signals at the sampling point using the first edge of each first sampled signal as the sampling point; and performing clock synchronization based on the timestamp information and the multiple first sampled values.

[0006] This application provides a clock synchronization method that uses a fractional-frequency-divider phase-locked loop circuit to divide a first reference clock signal, resulting in N first sub-clock signals clk1 to clkN. These first sub-clock signals are then used to sample a second pulse signal, yielding first sample signals Q1 to QN. Based on the first edge of each of the different first sample signals Q1 to QN as a sampling point, multiple first sample values ​​are determined at each sampling point. These multiple first sample values ​​allow for a more accurate determination of the second pulse signal's edge position, thus enabling a more precise determination of the current time. Therefore, compared to existing technologies that use only one first reference clock signal to sample the second pulse signal, this application, by using N first sub-clock signals, can reduce the sampling accuracy to 1 / N of the clock cycles of the first reference clock signal, increasing the sampling accuracy to N times the original level.

[0007] In some possible implementations, sampling the second pulse signal using multiple first sub-clock signals includes: sampling the second pulse signal N times using multiple first sub-clock signals to determine N sets of sampling results; where N is a positive integer; each set of sampling results includes multiple first sampling signals.

[0008] In practical applications, the phases of multiple first sub-clock signals obtained by frequency division of the first reference clock signal may drift or become inaccurate. After sampling the second pulse signal N times, if the phases of the multiple first sub-clock signals do not drift, then each of the N sets of sampling results will be basically consistent. If the phases of the multiple first sub-clock signals drift, the average value of the sampling can be determined by the total number of sampling results N and the multiple sets of sampling results, thus avoiding the problem of the sampling accuracy of the second pulse information being affected by the drift or inaccuracy of the multiple first sub-clock signals obtained after frequency division.

[0009] As one possible implementation, the first reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals, including: dividing the first reference clock signal by four using the fractional frequency divider phase-locked loop circuit to obtain four first sub-clock signals; wherein the phase difference between two adjacent first sub-clock signals after frequency division is 90°.

[0010] As one possible implementation, the fractional-frequency-division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; the inverter is used to: generate a signal with the opposite phase to the first reference clock signal based on the first reference clock signal; the first frequency divider is used to: divide the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 0° and 180°, respectively; the second frequency divider is used to: divide the signal with the opposite phase to the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 90° and 270°, respectively.

[0011] In practical applications, after the first reference clock signal is input to the inverter in the fractional-frequency-locked loop, its 0° and 180° phase clock signals are obtained. These 0° and 180° phase clock signals are then divided by the first and second frequency dividers, respectively, to obtain first sub-clock signals with initial phases of 0°, 90°, 180°, and 270°. Furthermore, the structure of the fractional-frequency-locked loop circuit in this application is not limited to this. The inverter in the fractional-frequency-locked loop circuit can also be a phase separation circuit, which can also generate a signal with a phase opposite to the first reference clock signal based on the first reference clock signal.

[0012] As one possible implementation, the first jump edge is a rising edge transitioning from a low level to a high level and / or a falling edge transitioning from a high level to a low level. Sampling the second pulse signal using multiple first sub-clock signals includes: sampling the second pulse signal using the second jump edges of the multiple first sub-clock signals, where the second jump edges are rising edges transitioning from a low level to a high level and / or falling edges transitioning from a high level to a low level.

[0013] As one possible implementation, after obtaining multiple first sub-clock signals, the method further includes: generating a first multi-phase clock signal based on the multiple first sub-clock signals, and sampling the second pulse signal using the first multi-phase clock signal.

[0014] As one possible implementation, determining the timestamp information based on multiple second sample values ​​and the local time includes: when a sample value of a predetermined size first appears among the multiple second sample values, determining the timestamp information based on the pulse period of the second pulse signal and the local time.

[0015] In distributed networks where high precision is required, the sampling error specified in the clock synchronization protocol messages will also be relatively low. As one possible implementation, the sampling error specified in the clock synchronization protocol messages is no greater than ±0.5 ns.

[0016] To meet the accuracy requirements of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1 GHz is required to sample the second pulse signal. However, under the current clock manufacturing process, the cost of producing a 1 GHz clock is too high. Currently, clocks with a clock frequency of less than 500 MHz are more common. In this application, a clock with a clock frequency of less than 500 MHz, which is more common and has lower requirements for clock manufacturing process, can also be used to complete the clock synchronization method provided in this application. As one possible implementation, the clock frequency of the first reference clock signal is no higher than 500 MHz.

[0017] Secondly, this application provides a clock synchronization method applied to a master synchronization device. It utilizes a fractional-frequency-divider phase-locked loop circuit to divide a second reference clock signal, obtaining multiple second sub-clock signals; each second sub-clock signal has the same period; the multiple second sub-clock signals are used to sample a second pulse signal, obtaining multiple second sampled signals; using the first edge of each second sampled signal as a sampling point, multiple second sampled values ​​are determined at the sampling point; timestamp information is determined based on the multiple second sampled values ​​and the local time, and a clock synchronization protocol message is sent, carrying the timestamp information. The technical effects of the corresponding solution in the second aspect can be referenced from the technical effects obtainable by the corresponding solution in the first aspect; repetitions are not detailed here.

[0018] As one possible implementation, sampling the second pulse signal using multiple second sub-clock signals includes: sampling the second pulse signal N times using multiple second sub-clock signals to determine N sets of sampling results; where N is a positive integer; each set of sampling results includes multiple second sampling signals.

[0019] As one possible implementation, the second reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals, including: dividing the second reference clock signal by four using a fractional frequency divider phase-locked loop circuit to obtain four second sub-clock signals; wherein, the phase difference between two adjacent first sub-clock signals after frequency division is 90°.

[0020] As one possible implementation, the fractional-frequency-division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; the inverter is used to: generate a signal with an opposite phase to the second reference clock signal based on the second reference clock signal; the first frequency divider is used to: divide the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 0° and 180°, respectively; the second frequency divider is used to: divide the signal with an opposite phase to the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90° and 270°, respectively.

[0021] As one possible implementation, the first jump edge is a rising edge that transitions from a low level to a high level and / or a falling edge that transitions from a high level to a low level.

[0022] As one possible implementation, sampling the second pulse signal using multiple first sub-clock signals includes: sampling the second pulse signal using the second jumping edge of the multiple first sub-clock signals, wherein the second jumping edge is a rising edge that jumps from a low level to a high level, and / or a falling edge that jumps from a high level to a low level.

[0023] As one possible implementation, after obtaining multiple first sub-clock signals, the method further includes: generating a second multi-phase clock signal based on multiple second sub-clock signals, and sampling the second pulse signal using the second multi-phase clock signal.

[0024] As one possible implementation, determining the timestamp information based on multiple second sample values ​​and the local time includes: when a sample value of a predetermined size first appears among the multiple second sample values, determining the timestamp information based on the pulse period of the second pulse signal and the local time.

[0025] As one possible implementation, the sampling error specified in the clock synchronization protocol message is no greater than ±0.5ns.

[0026] As one possible implementation, the clock frequency of the first reference clock signal is no higher than 500MHz.

[0027] Thirdly, this application also provides a clock synchronization device, including a message and second pulse signal receiving module, used for: receiving a second pulse signal and a clock synchronization protocol message, and parsing the clock synchronization protocol message to obtain timestamp information; a frequency division module, used for: dividing a first reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; a sampling module, used for: sampling the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; a sampled value determination module, used for: using the first edge of each first sampled signal as a sampling point to determine multiple first sampled values ​​of the multiple first sampled signals at the sampling point; and a clock synchronization module, used for: clock synchronization based on the timestamp information and the multiple first sampled values. The technical effects of the corresponding solutions in the third aspect can be referred to the technical effects obtainable by the corresponding solutions in the first aspect, and repetitions will not be detailed.

[0028] Fourthly, this application also provides a clock synchronization device, including a frequency division module for: dividing a second reference clock signal using a fractional-frequency-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period; a sampling module for: sampling a second pulse signal using the multiple second sub-clock signals to obtain multiple second sampled signals; a sampled value determination module for: determining multiple second sampled values ​​of the multiple second sampled signals at the sampling point, using the first edge of each second sampled signal as the sampling point; and a message generation module for: determining timestamp information based on the multiple second sampled values ​​and the local time, and sending a clock synchronization protocol message, wherein the clock synchronization protocol message carries the timestamp information. The technical effects of the corresponding solution in the fourth aspect can be referred to the technical effects obtainable by the corresponding solution in the first aspect, and repetitions are not detailed here.

[0029] Fifthly, this application provides a chip, including: a processor and a memory, the processor being connected to the memory, the memory storing an instruction program, and the processor, under the control of the instruction program, performing the following steps: obtaining a second pulse signal and a clock synchronization protocol message; parsing the clock synchronization protocol message to obtain timestamp information; dividing a first reference clock signal using a fractional-order frequency-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; sampling the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; determining multiple first sampled values ​​of the multiple first sampled signals at the sampling point, using the first edge of each first sampled signal as the sampling point; and performing clock synchronization based on the timestamp information and the multiple first sampled values. The technical effects of the corresponding solution in the fifth aspect can be referred to the technical effects obtainable by the corresponding solution in the first aspect, and repetitions are not detailed here.

[0030] Sixthly, this application provides a chip, including: a processor and a memory, the processor being connected to the memory, the memory storing an instruction program, and the processor, under the control of the instruction program, executing the following steps: dividing a second reference clock signal using a fractional-order frequency-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period; sampling a second pulse signal using the multiple second sub-clock signals to obtain multiple second sampled signals; determining multiple second sampled values ​​of the multiple second sampled signals at the sampling point, using the first edge of each second sampled signal as the sampling point; determining timestamp information based on the multiple second sampled values ​​and the local time, and generating a clock synchronization protocol message, the clock synchronization protocol message carrying the timestamp information. The technical effects of the corresponding solution in the sixth aspect can be referred to the technical effects obtainable by the corresponding solution in the second aspect, and repetitions are not detailed here.

[0031] Seventhly, this application provides a clock synchronization system, comprising: a second frequency division module, used to divide a second reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period; a second sampling module, used to sample a second pulse signal using the multiple second sub-clock signals to obtain multiple second sampled signals; a second sampled value determination module, used to determine multiple second sampled values ​​of the multiple second sampled signals at the sampling point, taking the first edge of each second sampled signal as the sampling point; and a message generation module, used to determine timestamp information based on the multiple second sampled values ​​and local time, and send a clock synchronization protocol message to a message and second pulse signal receiving module, wherein the clock synchronization protocol message carries a time stamp. The system comprises the following modules: a timestamp information module; a message and second pulse signal receiving module, used to receive the second pulse signal and clock synchronization protocol message sent by the message generation module, and parse the clock synchronization protocol message to obtain timestamp information; a first frequency division module, used to divide the first reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; a first sampling module, used to sample the second pulse signal using multiple first sub-clock signals to obtain multiple first sampled signals; a first sampled value determination module, used to determine multiple first sampled values ​​of the multiple first sampled signals at the sampling point, taking the first edge of each first sampled signal as the sampling point; and a clock synchronization module, used to perform clock synchronization based on the timestamp information and multiple first sampled values. The technical effects of the corresponding solutions in the seventh aspect can be referred to the technical effects obtainable by the corresponding solutions in the first and second aspects, and repetitions will not be detailed.

[0032] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0033] Figure 1A flowchart illustrating a clock synchronization method. Figure 1 ;

[0034] Figure 2 This is a timing diagram corresponding to a clock synchronization method;

[0035] Figure 3 This is a schematic diagram of a fractional frequency division phase-locked loop circuit;

[0036] Figure 4 A flowchart illustrating a clock synchronization method. Figure 2 ;

[0037] Figure 5 This is a schematic diagram of a clock synchronization device;

[0038] Figure 6 This is a schematic diagram of another clock synchronization device. Detailed Implementation

[0039] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in further detail below with reference to the accompanying drawings. It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0041] In the description of the embodiments of this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "At least one" in this application refers to one or more; "multiple" refers to two or more. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0042] In a distributed network, one node acts as the master synchronizer, while the others act as slave synchronizers. The master synchronizer synchronizes the base time with all the slave synchronizers. The master synchronizer sends IEEE 1588 protocol messages. The slave synchronizers collect timestamp information from these messages and determine the time difference with the master. They then adjust their own real-time clocks to synchronize with the master's. Finally, the slave synchronizers send their timestamps and second pulses to the processing module, which adjusts its own real-time clock accordingly, ultimately achieving clock synchronization.

[0043] However, in some distributed networks with high precision requirements, the sampling error specified in the clock synchronization protocol messages used may be relatively low. For example, to meet the precision requirements of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1 GHz is needed to sample the second pulse signal to achieve a sampling accuracy of 1 ns. However, with current clock manufacturing processes, producing a 1 GHz clock is too costly. Clocks with clock frequencies below 500 MHz are more common, but the sampling accuracy of lower-cost clocks is insufficient to meet the precision requirements of the IEEE 1588 synchronization system. Therefore, how to ensure high-precision sampling when using a lower sampling clock frequency is a problem that urgently needs to be solved by those skilled in the art.

[0044] Figure 1 A flowchart of a clock synchronization method provided in an embodiment of this application. Figure 2 The timing diagram corresponding to the clock synchronization method provided for the implementation of this application, combined with Figure 1 and Figure 2 When the clock synchronization method in this application embodiment is applied to a slave synchronization device, it may include the following methods:

[0045] S101: Receives the second pulse signal and clock synchronization protocol message, and parses the clock synchronization protocol message to obtain the timestamp information.

[0046] The clock synchronization protocol messages may include: Precision Time Protocol (PTP) messages, Generalized Precision Time Protocol (802.1AS) messages, sync messages, follow-up messages, delay-req messages, or delay-resp messages. The sampling error specified for the clock synchronization protocol messages may not exceed ±0.5 ns. This example uses PTP messages but does not constitute a limitation of this application. Those skilled in the art should understand that any clock synchronization protocol with high precision requirements (not exceeding ±0.5 ns) can be used in this application, without further limitations. The second pulse signal can be generated by an external clock device or sent along with the master synchronization device.

[0047] The time stamp information master synchronization device is determined based on the current time, which is not limited to Universal Time Coordinated (UTC) time and Global Positioning System (GPS) time, etc., and is not specifically limited here.

[0048] S102: The first reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals. Each first sub-clock signal has the same period.

[0049] The first reference clock signal can be generated by an internal clock. Optionally, the internal clock may include: a crystal oscillator, a frequency multiplier circuit, a phase detector, a clock pulse circuit, an input digital-to-analog converter, a voltage-controlled oscillator, etc. For example, the crystal oscillator can generate a clock signal at a reference frequency, the reference frequency of which is related to the specific structure of the crystal oscillator; the frequency multiplier circuit is used to multiply the reference frequency clock signal; the phase detector is used to perform phase detection processing on the frequency multiplied signal; the clock pulse circuit converts the phase detection signal into a clock pulse signal; the input digital-to-analog converter is used to convert the clock pulse signal into an analog clock pulse signal; and the voltage-controlled oscillator outputs the first reference clock signal based on the analog clock pulse signal. The above processing of the reference frequency clock signal is only an example, and the connection relationship of the components in the internal clock is not limited. The purpose is to generate a clock signal of a specific frequency, and the specific generation method is not limited, as should be known to those skilled in the art.

[0050] Existing frequency divider circuits can use a time-to-digital converter (TDC) to divide the first reference clock signal. However, if a TDC is used, the timing after frequency division will be completely determined by the timing chip (cell). However, the timing chip (cell) has high jitter and uncertainty, and is greatly affected by process voltage temperature (PVT) conditions. Therefore, the frequency division reliability using TDC is low, and it will produce a maximum delay jitter of 1.68%. Furthermore, due to the structure of its delay loop, the delay jitter will accumulate, resulting in a larger error.

[0051] This application uses analog devices to construct a fractional frequency division phase-locked loop circuit, which is not affected by process angle deviation and temperature. The fractional frequency division phase-locked loop circuit is an open-loop structure, which is better suited for high-speed clock scenarios. Moreover, it does not require a complex closed-loop structure to meet the requirements of high-speed clock scenarios, and has the advantages of low delay and high accuracy.

[0052] Continue reading Figure 2 As shown, as one possible implementation, the first reference clock signal is divided by four using a fractional frequency divider phase-locked loop circuit to obtain four first sub-clock signals; wherein, the phase difference between two adjacent first sub-clock signals after frequency division is 90°. Figure 2 The first reference clock signal is divided by four using a fractional-order frequency-locked loop circuit to obtain four first sub-clock signals: first sub-clock signal clk1, first sub-clock signal clk2, first sub-clock signal clk3, and first sub-clock signal clk4; wherein the phase difference between each adjacent clock signal is 90°. It should be noted that in this embodiment, the 90° phase difference between adjacent clock signals means that, for example, the phase difference between first sub-clock signal clk1 and first sub-clock signal clk2 can have a certain deviation range, or in other words, the phase difference between first sub-clock signal clk1 and first sub-clock signal clk2 is approximately 90°, and all first sub-clocks need to remain synchronized. As one possible implementation, the clock frequency of the first reference clock signal is no higher than 500MHz. For example, to improve sampling accuracy, the number of first sub-clock signals generated can be related to the clock frequency of the first reference clock signal. For instance, when the clock frequency of the first reference clock signal is 500MHz, the fractional frequency divider phase-locked loop circuit can divide the first reference clock signal by four to obtain four first sub-clock signals. When the clock frequency of the first reference clock signal is 250MHz, the fractional frequency divider phase-locked loop circuit can divide the first reference clock signal by eight to obtain eight first sub-clock signals.

[0053] S103: The second pulse signal is sampled using multiple first sub-clock signals to obtain multiple first sampled signals.

[0054] It should be noted that, in the embodiments of this application, the first sub-clock signal can sample the second pulse signal using the second transition edge. For example, the second transition edge can be a rising edge, that is, a transition edge from low level (0) to high level (1). Of course, the second transition edge can also be a falling edge, that is, a transition edge from high level (1) to low level (0). For ease of explanation, this application will use the rising edge as the example for the second transition edge. For example, taking rising edge sampling as an example, after sampling the second pulse signal using the first sub-clock signal clk1, the first sampled signal Q1 can be obtained.

[0055] S104: Using the first edge of each first sampling signal as the sampling point, determine multiple first sampling values ​​of multiple first sampling signals at the sampling point.

[0056] The first sampling value of the first sampling signal Q1 at sampling point A is determined using the first transition edge of the first sampling signal Q1 as sampling point A. It should be noted that in the embodiments of this application, the sampling point refers to the first transition edge of the first sampling signal. The first transition edge is the transition edge from the first value to the second value. For example, the first transition edge can be a rising edge, that is, the transition edge from low level (0) to high level (1). Of course, the first transition edge can also be a falling edge, that is, the transition edge from high level (1) to low level (0). For ease of explanation, the first transition edge is always described as a rising edge in this application.

[0057] S105: Perform clock synchronization based on timestamp information and multiple first sample values.

[0058] After obtaining multiple first sample values, the current time is determined based on the sample value of the earliest time of update among the multiple first sample values ​​and the timestamp information, thereby achieving clock synchronization.

[0059] In a distributed network, each device may include a clock synchronization module and a processing module. Steps S101 to S105 described above can be executed in the processing module. That is, the clock synchronization module periodically receives timestamp information and second pulse information from the master synchronization device and periodically sends timestamp information and second pulse information to the processing module. After receiving the timestamp information and second pulse information, the processing module executes steps S101 to S105 described above, thereby enabling the master synchronization device and the slave synchronization device to achieve clock synchronization.

[0060] As one possible implementation, clock synchronization based on timestamp information and multiple first sample values ​​can be achieved by: when a sample value of a predetermined size first appears among the multiple first sample values, determining the current time based on the pulse period of the second pulse signal and the timestamp information. For an example, please continue reading... Figure 2 As shown, in this embodiment, the first reference clock can be divided by four to obtain four first sub-clock signals clk1 to clk4. By sampling the second pulse signal using these four first sub-clock signals, first sampling signals Q1 to Q4 can be obtained. Multiple first sample values ​​are obtained based on the first transition edges of the first sampling signals Q1 to Q4. For example, if the pulse period of the second pulse signal is 1 second and the time indicated by the timestamp information is 10:00:00, when a sample value of 1 appears among the multiple first sample values, the current time is determined to be 10:00:01 from the synchronization device. Using the above method, the transition edge position of the second pulse signal can be determined more accurately, thereby determining the current time more precisely.

[0061] Furthermore, since it takes a certain amount of time for clock synchronization protocol messages to travel from the master synchronization device to the slave synchronization device, this application embodiment can use the transmission time as a compensation time when calculating the real-time time, and add it to the time carried by the timestamp in advance, so as to perform clock synchronization after compensating for the transmission time; and, since the transmission method of sending clock synchronization protocol messages is different, or the distance between the master synchronization device and the slave synchronization device is different, the corresponding transmission time is also different.

[0062] For example, the clock synchronization method provided in this application uses a fractional-order frequency-locked loop circuit to divide the first reference clock signal to obtain first sub-clock signals clk1 to clk4; wherein the phase difference between each adjacent clock signal is 90°, and the second pulse signal is sampled using the above-mentioned first sub-clock signals to obtain first sampling signals Q1 to Q4. According to the first sampling values ​​corresponding to different first sampling signals Q1 to Q4, compared with the prior art which only uses one first reference clock signal to sample the second pulse signal, this application can reduce the sampling accuracy to 1 / N of the clock cycles of the first reference clock signal by using N first sub-clock signals, thus increasing the sampling accuracy to N times the original.

[0063] In real-world scenarios, the phases of the multiple first sub-clock signals obtained by frequency division of the first reference clock signal may drift or become inaccurate. As a possible implementation method, the clock synchronization method provided in this application embodiment may further include: sampling the second pulse signal N times using multiple first sub-clock signals to determine N sets of sampling results; where N is a positive integer; each set of sampling results includes multiple first sampling signals.

[0064] In other words, in this embodiment of the application, by executing the above steps S103 to S105 N times, that is, by sampling the second pulse signal N times using multiple first sub-clock signals, if the phases of the multiple first sub-clock signals do not drift, then each of the N sets of sampling results is basically consistent. If the phases of the multiple first sub-clock signals drift, the average value of the sampling can be determined by the total number of sampling results N and the multiple sets of sampling results, thus avoiding the problem that the sampling accuracy of the second pulse information is affected by the drift or inaccuracy of the multiple first sub-clock signals obtained after frequency division.

[0065] As one possible implementation, the fractional-frequency-division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; the inverter is used to: generate a signal with the opposite phase to the first reference clock signal based on the first reference clock signal; the first frequency divider is used to: divide the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 0° and 180°, respectively; the second frequency divider is used to: divide the signal with the opposite phase to the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 90° and 270°, respectively.

[0066] Figure 3 This is a schematic diagram of a fractional frequency division phase-locked loop circuit; see reference. Figure 3 As shown, the first reference clock signal is first input into the inverter in the fractional frequency division phase-locked loop to obtain its 0° and 180° phase clocks CLK0 and CLK1. CLK0 passes through the first frequency divider to obtain CLK00 and CLK01 with a frequency of 1 / 2 and a phase of 0° and 180°. CLK1 passes through the second frequency divider to obtain CLK10 and CLK11 with a frequency of 1 / 2 and a phase of 90° and 270°.

[0067] Furthermore, the structure of the fractional frequency division phase-locked loop circuit in this application is not limited to this. The inverter in the fractional frequency division phase-locked loop circuit can also be a phase separation circuit. The phase separation circuit can also generate 0° and 180° phase clocks CLK0 and CLK1 according to the first reference clock signal. The phase separation circuit has a smaller delay error than the inverter, and its value is generally less than 3ps, which is more suitable for the high-precision clock synchronization protocol scenario of this application.

[0068] As one possible implementation, after obtaining the plurality of first sub-clock signals, the method further includes:

[0069] A first multi-phase clock signal is generated based on the plurality of first sub-clock signals, and the second pulse signal is sampled using the first multi-phase clock signal.

[0070] The fractional-order frequency-locked loop circuit may further include an AND gate circuit for synthesizing multiple first sub-clock signals into a first multi-phase clock. For example, if CLK00, CLK01, CLK10, and CLK11 from the above embodiment are input into the AND gate circuit, the AND gate circuit obtains a four-phase clock with a frequency half that of the first reference clock signal, a duty cycle of 25%, and initial phases of 0°, 90°, 180°, and 270°.

[0071] Figure 4 This is a flowchart of a clock synchronization method provided in an embodiment of this application. The clock synchronization method in this embodiment is applied to a master synchronization device and may include:

[0072] S401: The second reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals; wherein, each second sub-clock signal has the same period;

[0073] S402: The second pulse signal is sampled using the plurality of second sub-clock signals to obtain a plurality of second sampled signals;

[0074] S403: Using the first edge of each second sampling signal as a sampling point, determine multiple second sampling values ​​of the multiple second sampling signals at the sampling point;

[0075] S404: Determine the timestamp information based on the plurality of second sampled values ​​and the local time, and send a clock synchronization protocol message, the clock synchronization protocol message carrying the timestamp information. For possible implementation methods and beneficial effects of this application embodiment, please refer to steps S101 to S105 of the above embodiment; repeated details will not be elaborated upon, and those skilled in the art should understand them.

[0076] See Figure 5 As shown, this application provides a clock synchronization device 500, which includes: a message and second pulse signal receiving module 501, used to: receive a second pulse signal and a clock synchronization protocol message, and parse the clock synchronization protocol message to obtain timestamp information; a frequency division module 502, used to: divide a first reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; a sampling module 503, used to: sample the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; a sampling value determination module 504, used to: determine multiple first sampled values ​​of the multiple first sampled signals at the sampling point, taking the first edge of each first sampled signal as the sampling point; and a clock synchronization module 505, used to: perform clock synchronization based on the timestamp information and the multiple first sampled values.

[0077] See Figure 6As shown, this application also provides a clock synchronization device 600, which includes: a frequency division module 601, used to: divide a second reference clock signal using a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein each second sub-clock signal has the same period; a sampling module 602, used to: sample the second pulse signal using the plurality of second sub-clock signals to obtain a plurality of second sampled signals; a sampling value determination module 603, used to: determine a plurality of second sampled values ​​of the plurality of second sampled signals at the sampling point, taking the first edge of each second sampled signal as the sampling point; and a message generation module 604, used to: determine timestamp information based on the plurality of second sampled values ​​and local time, and send a clock synchronization protocol message, wherein the clock synchronization protocol message carries the timestamp information.

[0078] It should be noted that the module division in this embodiment is illustrative and represents only one possible division of turbine functions. In actual implementation, other division methods may be used. The functional modules in this example can be integrated into one processing module, or each module can exist as a separate physical entity, or two or more units can be integrated into one unit. The integrated modules described above can be implemented in hardware or as software functional modules.

[0079] This application also provides a clock synchronization system, comprising: a second frequency division module, used to divide a second reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period; a second sampling module, used to sample the second pulse signal using the multiple second sub-clock signals to obtain multiple second sampled signals; a second sampled value determination module, used to determine multiple second sampled values ​​of the multiple second sampled signals at the sampling point, taking the first edge of each second sampled signal as the sampling point; and a message generation module, used to determine timestamp information based on the multiple second sampled values ​​and local time, and send a clock synchronization protocol message to the message and second pulse signal receiving module, wherein the clock synchronization protocol message carries the timestamp. The system includes: an information module for receiving a message and a second pulse signal, used to receive a second pulse signal and a clock synchronization protocol message sent by the message generation module, and to parse the clock synchronization protocol message to obtain timestamp information; a second frequency division module, used to divide the first reference clock signal using a fractional frequency division phase-locked loop circuit to obtain multiple first sub-clock signals, wherein each first sub-clock signal has the same period; a second sampling module, used to sample the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; a second sampled value determination module, used to determine multiple first sampled values ​​of the multiple first sampled signals at the sampling point, with the first edge of each first sampled signal as the sampling point; and a clock synchronization module, used to perform clock synchronization based on the timestamp information and the multiple first sampled values.

[0080] This application also provides a chip, a processor, and a memory. The processor is connected to the memory, which stores an instruction program. Under the control of the instruction program, the processor performs the following steps: obtaining a second pulse signal and a clock synchronization protocol message; parsing the clock synchronization protocol message to obtain timestamp information; dividing a first reference clock signal using a fractional-order frequency-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; sampling the second pulse signal using the multiple first sub-clock signals to obtain multiple first sampled signals; using the first edge of each first sampled signal as a sampling point, determining multiple first sampled values ​​of the multiple first sampled signals at the sampling point; and performing clock synchronization based on the timestamp information and the multiple first sampled values.

[0081] This application also provides a chip, including: a processor and a memory, wherein the processor is connected to the memory, the memory stores an instruction program, and the processor, under the control of the instruction program, is used to perform the following steps: dividing a second reference clock signal using a fractional-order frequency-locked loop circuit to obtain a plurality of second sub-clock signals; wherein each second sub-clock signal has the same period; sampling the second pulse signal using the plurality of second sub-clock signals to obtain a plurality of second sampled signals; determining a plurality of second sampled values ​​of the plurality of second sampled signals at the sampling point using the first edge of each second sampled signal as the sampling point; determining timestamp information based on the plurality of second sampled values ​​and the local time, and generating a clock synchronization protocol message, wherein the clock synchronization protocol message carries the timestamp information.

[0082] Based on the above embodiments, this application also provides a computer program that, when run on a computer, causes the computer to execute the clock synchronization method provided in the above embodiments.

[0083] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a computer, causes the computer to perform the clock synchronization method provided in the above embodiments.

[0084] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0085] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0086] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0087] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0088] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A clock synchronization method, applied to a synchronization device, characterized in that, The method includes: Receive the second pulse signal and the clock synchronization protocol message, and parse the clock synchronization protocol message to obtain the timestamp information; The first reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period. The second pulse signal is sampled using the plurality of first sub-clock signals to obtain a plurality of first sample signals; Using the first edge of each first sampling signal as a sampling point, determine multiple first sampling values ​​of the multiple first sampling signals at the sampling point; Clock synchronization is performed based on the timestamp information and the plurality of first sample values.

2. The method according to claim 1, characterized in that, The sampling of the second pulse signal using the plurality of first sub-clock signals includes: The second pulse signal is sampled N times using the plurality of first sub-clock signals to determine N sets of sampling results; wherein, N is a positive integer; each set of sampling results includes the plurality of first sampling signals.

3. The method according to claim 1 or 2, characterized in that, The first reference clock signal is divided by a fractional-frequency-locked loop circuit to obtain multiple first sub-clock signals, including: The first reference clock signal is divided into four by a fractional frequency divider phase-locked loop circuit to obtain four first sub-clock signals; the phase difference between two adjacent first sub-clock signals after frequency division is 90°.

4. The method according to claim 3, characterized in that, The fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; The inverter is used to: generate a signal with a phase opposite to the first reference clock signal based on the first reference clock signal; The first frequency divider is used to divide the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 0° and 180°, respectively. The second frequency divider is used to divide the signal that is out of phase with the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 90° and 270°, respectively.

5. The method according to any one of claims 1-2 or 4, characterized in that, The first jump edge is a rising edge that transitions from a low level to a high level and / or a falling edge that transitions from a high level to a low level.

6. The method according to any one of claims 1-2 or 4, characterized in that, The step of sampling the second pulse signal using the plurality of first sub-clock signals includes: The second pulse signal is sampled using the second edge of the plurality of first sub-clock signals, wherein the second edge is a rising edge that transitions from a low level to a high level, and / or a falling edge that transitions from a high level to a low level.

7. The method according to any one of claims 1-2 or 4, characterized in that, After obtaining multiple first sub-clock signals, the method further includes: A first multi-phase clock signal is generated based on the plurality of first sub-clock signals, and the second pulse signal is sampled using the first multi-phase clock signal.

8. The method according to any one of claims 1-2 or 4, characterized in that, The clock synchronization based on the timestamp information and the plurality of first sample values ​​includes: When a sample value of a set size first appears among the plurality of first sample values, the current time is determined based on the pulse period of the second pulse signal and the timestamp information.

9. The method according to any one of claims 1-2 or 4, characterized in that, The sampling error specified in the clock synchronization protocol message is no greater than ±0.5ns.

10. The method according to any one of claims 1-2 or 4, characterized in that, The clock frequency of the first reference clock signal is no higher than 500MHz.

11. A clock synchronization method, applied to a master synchronization device, characterized in that, The method includes: The second reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals; each second sub-clock signal has the same period. The second pulse signal is sampled using the multiple second sub-clock signals to obtain multiple second sampled signals; Using the first edge of each second sampling signal as a sampling point, determine multiple second sampling values ​​of the multiple second sampling signals at the sampling point; Based on the plurality of second sampled values ​​and the local time, timestamp information is determined, and a clock synchronization protocol message is sent, the clock synchronization protocol message carrying the timestamp information.

12. The method according to claim 11, characterized in that, The sampling of the second pulse signal using the plurality of second sub-clock signals includes: The second pulse signal is sampled N times using the plurality of second sub-clock signals to determine N sets of sampling results; wherein, N is a positive integer; each set of sampling results includes the plurality of second sampling signals.

13. The method according to claim 11 or 12, characterized in that, The second reference clock signal is divided by a fractional-frequency-locked loop circuit to obtain multiple second sub-clock signals, including: The second reference clock signal is divided by four using a fractional frequency divider phase-locked loop circuit to obtain four second sub-clock signals; the phase difference between two adjacent second sub-clock signals after frequency division is 90°.

14. The method according to claim 13, characterized in that, The fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; The inverter is used to: generate a signal with a phase opposite to the second reference clock signal based on the second reference clock signal; The first frequency divider is used to divide the second reference clock signal by two to obtain two second sub-clock signals, wherein the starting phases of the two second sub-clock signals are 0° and 180°, respectively. The second frequency divider is used to divide the signal that is out of phase with the second reference clock signal by two to obtain two second sub-clock signals, wherein the starting phases of the two second sub-clock signals are 90° and 270°, respectively.

15. The method according to any one of claims 11-12 or 14, characterized in that, The first jump edge is a rising edge that transitions from a low level to a high level and / or a falling edge that transitions from a high level to a low level.

16. The method according to any one of claims 11-12 or 14, characterized in that, The step of sampling the second pulse signal using the plurality of second sub-clock signals includes: The second pulse signal is sampled using the second jumping edge of the plurality of second sub-clock signals, wherein the second jumping edge is a rising edge that jumps from low level to high level, and / or a falling edge that jumps from high level to low level.

17. The method according to any one of claims 11-12 or 14, characterized in that, After obtaining multiple second sub-clock signals, the method further includes: A second multi-phase clock signal is generated based on the plurality of second sub-clock signals, and the second multi-phase clock signal is used to sample the second pulse signal.

18. The method according to any one of claims 11-12 or 14, characterized in that, The step of determining the timestamp information based on the plurality of second sample values ​​and the local time includes: When a sample value of a set size first appears among the plurality of second sample values, the timestamp information is determined based on the pulse period of the second pulse signal and the local time.

19. The method according to any one of claims 11-12 or 14, characterized in that, The sampling error specified in the clock synchronization protocol message is no greater than ±0.5ns.

20. The method according to any one of claims 11-12 or 14, characterized in that, The clock frequency of the second reference clock signal is no higher than 500MHz.

21. A clock synchronization device, characterized in that, The device includes: The message and second pulse signal receiving module is used to: receive the second pulse signal and the clock synchronization protocol message, and parse the clock synchronization protocol message to obtain the timestamp information; The frequency divider module is used to: divide the first reference clock signal using a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period; The sampling module is used to: sample the second pulse signal using the plurality of first sub-clock signals to obtain a plurality of first sample signals; The sampling value determination module is used to: determine multiple first sampling values ​​of the multiple first sampling signals at the sampling point, taking the first edge of each first sampling signal as the sampling point; A clock synchronization module is used to: synchronize the clock based on the timestamp information and the plurality of first sample values.

22. The apparatus according to claim 21, characterized in that, The device includes: The sampling module is specifically used to: sample the second pulse signal N times using the plurality of first sub-clock signals to determine N sets of sampling results; wherein, N is a positive integer; each set of sampling results includes the plurality of first sampling signals.

23. The apparatus according to claim 21 or 22, characterized in that, The frequency division module is specifically used for: The first reference clock signal is divided into four by a fractional frequency divider phase-locked loop circuit to obtain four first sub-clock signals; the phase difference between two adjacent first sub-clock signals after frequency division is 90°.

24. The apparatus according to claim 23, characterized in that, The fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; The inverter is used to: generate a signal with a phase opposite to the first reference clock signal based on the first reference clock signal; The first frequency divider is used to divide the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 0° and 180°, respectively. The second frequency divider is used to divide the signal that is out of phase with the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting phases of the two first sub-clock signals are 90° and 270°, respectively.

25. The apparatus according to any one of claims 21-22 or 24, characterized in that, The first jump edge is a rising edge that transitions from a low level to a high level and / or a falling edge that transitions from a high level to a low level.

26. The apparatus according to any one of claims 21-22 or 24, characterized in that, The sampling module is specifically used for: The second pulse signal is sampled using the second edge of the plurality of first sub-clock signals, wherein the second edge is a rising edge that transitions from a low level to a high level, and / or a falling edge that transitions from a high level to a low level.

27. The apparatus according to any one of claims 21-22 or 24, characterized in that, The clock synchronization device further includes a signal synthesis module, which is used to generate a first multi-phase clock signal based on the plurality of first sub-clock signals, and to sample the second pulse signal using the first multi-phase clock signal.

28. The apparatus according to any one of claims 21-22 or 24, characterized in that, The clock synchronization module is specifically used for: When a sample value of a set size first appears among the plurality of first sample values, the current time is determined based on the pulse period of the second pulse signal and the timestamp information.

29. A clock synchronization device, characterized in that, The device includes: The frequency divider module is used to divide the second reference clock signal using a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period. The sampling module is used to: sample the second pulse signal using the plurality of second sub-clock signals to obtain a plurality of second sampling signals; The sampling value determination module is used to: determine multiple second sampling values ​​of the multiple second sampling signals at the sampling point, taking the first edge of each second sampling signal as the sampling point; The message generation module is used to: determine timestamp information based on the plurality of second sampled values ​​and the local time, and send a clock synchronization protocol message, wherein the clock synchronization protocol message carries the timestamp information.

30. The apparatus according to claim 29, characterized in that, The sampling module is specifically used to: sample the second pulse signal N times using the plurality of second sub-clock signals to determine N sets of sampling results; wherein, N is a positive integer; each set of sampling results includes the plurality of second sampling signals.

31. The apparatus according to claim 29 or 30, characterized in that, The frequency division module is specifically used for: The second reference clock signal is divided by four using a fractional frequency divider phase-locked loop circuit to obtain four second sub-clock signals; the phase difference between two adjacent second sub-clock signals after frequency division is 90°.

32. The apparatus according to claim 31, characterized in that, The fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider, and a second frequency divider; The inverter is used to: generate a signal with a phase opposite to the second reference clock signal based on the second reference clock signal; The first frequency divider is used to divide the second reference clock signal by two to obtain two second sub-clock signals, wherein the starting phases of the two second sub-clock signals are 0° and 180°, respectively. The second frequency divider is used to divide the signal that is out of phase with the second reference clock signal by two to obtain two second sub-clock signals, wherein the starting phases of the two second sub-clock signals are 90° and 270°, respectively.

33. The apparatus according to any one of claims 29-30 or 32, characterized in that, The first jump edge is a rising edge that transitions from a low level to a high level and / or a falling edge that transitions from a high level to a low level.

34. The apparatus according to any one of claims 29-30 or 32, characterized in that, The sampling module is specifically used for: The second pulse signal is sampled using the second jumping edge of the plurality of second sub-clock signals, wherein the second jumping edge is a rising edge that jumps from low level to high level, and / or a falling edge that jumps from high level to low level.

35. The apparatus according to any one of claims 29-30 or 32, characterized in that, The clock synchronization device further includes a signal synthesis module, which is used to generate a second multi-phase clock signal based on the plurality of second sub-clock signals, and to sample the second pulse signal using the second multi-phase clock signal.

36. The apparatus according to any one of claims 29-30 or 32, characterized in that, The message generation module is specifically used for: When a sample value of a set size first appears among the plurality of second sample values, the timestamp information is determined based on the pulse period of the second pulse signal and the local time.

37. A chip, characterized in that, include: A processor and a memory, the processor being connected to the memory, the memory storing an instruction program, the processor, under the control of the instruction program, performing the following steps: Obtain the second pulse signal and clock synchronization protocol message, and parse the clock synchronization protocol message to obtain the timestamp information; The first reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period. The second pulse signal is sampled using the plurality of first sub-clock signals to obtain a plurality of first sample signals; Using the first edge of each first sampling signal as a sampling point, determine multiple first sampling values ​​of the multiple first sampling signals at the sampling point; Clock synchronization is performed based on the timestamp information and the plurality of first sample values.

38. A chip, characterized in that, include: A processor and a memory, the processor being connected to the memory, the memory storing an instruction program, the processor, under the control of the instruction program, performing the following steps: The second reference clock signal is divided by a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals; each second sub-clock signal has the same period. The second pulse signal is sampled using the multiple second sub-clock signals to obtain multiple second sampled signals; Using the first edge of each second sampling signal as a sampling point, determine multiple second sampling values ​​of the multiple second sampling signals at the sampling point; Based on the plurality of second sampled values ​​and the local time, timestamp information is determined, and a clock synchronization protocol message is generated, wherein the clock synchronization protocol message carries the timestamp information.

39. A clock synchronization system, characterized in that, The clock synchronization system includes: The second frequency divider module is used to divide the second reference clock signal using a fractional frequency divider phase-locked loop circuit to obtain multiple second sub-clock signals; wherein each second sub-clock signal has the same period. The second sampling module is used to sample the second pulse signal using the multiple second sub-clock signals to obtain multiple second sampling signals; The second sampling value determination module is used to determine multiple second sampling values ​​of the multiple second sampling signals at the sampling point, taking the first jumping edge of each second sampling signal as the sampling point; The message generation module is used to determine the timestamp information based on the plurality of second sample values ​​and the local time, and send a clock synchronization protocol message to the message and second pulse signal receiving module, wherein the clock synchronization protocol message carries the timestamp information; The message and second pulse signal receiving module is used to receive the second pulse signal and clock synchronization protocol message sent by the message generation module, and parse the clock synchronization protocol message to obtain timestamp information; The first frequency divider module is used to divide the first reference clock signal using a fractional frequency divider phase-locked loop circuit to obtain multiple first sub-clock signals; wherein each first sub-clock signal has the same period. The first sampling module is used to sample the second pulse signal using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; The first sample value determination module is used to determine multiple first sample values ​​of the multiple first sample signals at the sampling point, taking the first edge of each first sample signal as the sampling point; A clock synchronization module is used to synchronize the clock based on the timestamp information and the plurality of first sample values.

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