Bandgap reference circuit and in-situ background calibration method

Abstract

The application provides a band gap reference source circuit and an in-situ background calibration method. The band gap reference source circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first triode, a second triode, a third triode, a first resistor, a second resistor, an error amplifier, a resistor unit, a bias correction unit, a voltage comparison unit and a correction code adjusting unit. The voltage comparison unit is used for comparing the magnitudes of the voltages on the source terminal input lines of the first PMOS tube, the second PMOS tube and the third PMOS tube, and comparing the magnitudes of the drain voltages of the first PMOS tube and the second PMOS tube. The correction code adjusting unit is used for adjusting the resistance value of the resistor unit or adjusting the width-length ratio of the second PMOS tube and the third PMOS tube according to the comparison result of the voltage comparison unit. The correction code adjusting unit is also used for adjusting the bias correction unit according to the comparison result of the voltage comparison unit, so that the voltage error output by the band gap reference source circuit is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bandgap reference source circuit and an in-situ background calibration method. Background Technology

[0002] A bandgap voltage reference is a fundamental building block in analog integrated circuits used to generate a stable reference voltage. Its output voltage must not only remain relatively stable under temperature variations but also possess high absolute accuracy, as it directly impacts the performance of the circuit system. For example, in voltage regulator applications, the regulator's output voltage is determined by the formula Vreg = VBG * (1 + α), where VBG is the bandgap reference voltage and α is a proportionality constant. Therefore, the accuracy of VBG directly determines the accuracy of the regulator's output voltage.

[0003] Figure 1 This is a bandgap reference source circuit in the prior art. Figure 1 In the bandgap reference source circuit shown, the input offset voltage of the error amplifier A11 causes voltage error between node VDP11 and node VDN11, and the current mirror mismatch error causes current error between currents I11, I12 and I13, etc.

[0004] Figure 2 This is yet another bandgap reference source circuit in the existing technology. Figure 2 The bandgap reference circuit shown utilizes three choppers, CH21, CH22, and CH23. Chopping technology can improve the accuracy of the bandgap reference voltage, but it requires a continuously operating clock signal CLK, increasing circuit power consumption. Furthermore, it generates additional noise, which can interfere with other modules in the system. For example, noise from the clock signal and the choppers propagates through the power supply, ground, and bandgap reference voltage output. While a filter can be added to the bandgap reference voltage output to reduce noise, this increases circuit area and startup time. Moreover, it does not eliminate noise interference to the power supply and ground. Additionally, Figure 2 Although the matching error between PMOS transistors MP21 and MP22 can be eliminated, the matching error between PMOS transistor MP23 and PMOS transistors MP21 and MP22 is not eliminated, resulting in a certain error remaining in the bandgap reference source voltage.

[0005] Therefore, it is necessary to provide a novel bandgap reference source circuit and an in-situ background calibration method to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0006] The purpose of this invention is to provide a bandgap reference source circuit and an in-situ background calibration method to reduce the voltage error output by the bandgap reference source circuit.

[0007] To achieve the above objectives, the bandgap reference source circuit of the present invention includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, an error amplifier, a resistor unit, an offset correction unit, a voltage comparator unit, and a correction code adjustment unit. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the resistor unit. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the output terminal of the error amplifier. The drain of the first PMOS transistor is connected to the emitter of the first transistor. The base and collector of the first transistor are both grounded. The drain of the second PMOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the emitter of the second transistor. The base and collector of the second transistor are both grounded. The drain of the third PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the emitter of the third PMOS transistor. The base and collector of the third PMOS transistor are both grounded. The offset correction unit is used to adjust the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor. The voltage comparison unit is used to compare the magnitudes of the voltages on the source input lines of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, as well as the magnitudes of the drain voltages of the first PMOS transistor and the second PMOS transistor. The correction code adjustment unit is used to adjust the resistance value of the resistor unit or adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit. The correction code adjustment unit is also used to adjust the offset correction unit according to the comparison result of the voltage comparison unit.

[0008] Optionally, the resistor unit includes a first degradation resistor, a second degradation resistor, and a third degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to the source of the first PMOS transistor, the other end of the second degradation resistor is connected to the source of the second PMOS transistor, and the other end of the third degradation resistor is connected to the source of the third PMOS transistor.

[0009] Optionally, the voltage comparison unit includes a multiplexing circuit and a comparison module. The first input terminal of the multiplexing circuit is connected to the source of the first PMOS transistor, the second input terminal of the multiplexing circuit is connected to the drain of the first PMOS transistor, the third input terminal of the multiplexing circuit is connected to the drain of the second PMOS transistor, the fourth input terminal of the multiplexing circuit is connected to the source of the second PMOS transistor, the fifth input terminal of the multiplexing circuit is connected to the source of the third PMOS transistor, the first output terminal of the multiplexing circuit is connected to the first input terminal of the comparison module, and the second output terminal of the multiplexing circuit is connected to the second input terminal of the comparison module.

[0010] Optionally, the correction code adjustment unit is used to adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

[0011] Optionally, the resistor unit includes a first degradation resistor, a second degradation resistor, a third degradation resistor, a first adjustable degradation resistor, a second adjustable degradation resistor, and a third adjustable degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to one end of the first adjustable degradation resistor, and the other end of the first adjustable degradation resistor is connected to the source of the first PMOS transistor. The other end of the second degradation resistor is connected to one end of the second adjustable degradation resistor, and the other end of the second adjustable degradation resistor is connected to the source of the second PMOS transistor. The other end of the third degradation resistor is connected to one end of the third adjustable degradation resistor, and the other end of the third adjustable degradation resistor is connected to the source of the third PMOS transistor.

[0012] Optionally, the voltage comparison unit includes a multiplexing circuit and a comparison module. The first input terminal of the multiplexing circuit is connected to the other end of the first degradation resistor. The second input terminal of the multiplexing circuit is connected to the drain of the first PMOS transistor. The third input terminal of the multiplexing circuit is connected to the drain of the second PMOS transistor. The fourth input terminal of the multiplexing circuit is connected to the other end of the second degradation resistor. The fifth input terminal of the multiplexing circuit is connected to the other end of the third degradation resistor. The first output terminal of the multiplexing circuit is connected to the first input terminal of the comparison module. The second output terminal of the multiplexing circuit is connected to the second input terminal of the comparison module.

[0013] Optionally, the correction code adjustment unit is used to adjust the resistance values ​​of the first adjustable degradation resistor, the second adjustable degradation resistor, and the third adjustable degradation resistor according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

[0014] Optionally, the comparison module is an auto-zero comparator.

[0015] The present invention also provides an in-situ background calibration method for the bandgap reference source circuit, comprising the following steps:

[0016] S1: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor are compared by the voltage comparison unit to obtain a first comparison result;

[0017] S2: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result, and then executes step S1 until the first comparison result output by the voltage comparison unit is flipped.

[0018] S3: The voltage comparison unit compares the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor to obtain a second comparison result;

[0019] S4: The correction code adjustment unit adjusts the offset correction unit according to the second comparison result, and then step S3 is executed until the second comparison result output by the voltage comparison unit is flipped.

[0020] S5: Repeat steps S1 to S4 several times;

[0021] S6: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor are compared by the voltage comparison unit to obtain a third comparison result;

[0022] S7: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result, and then executes step S6 until the third comparison result output by the voltage comparison unit flips.

[0023] Optionally, the resistor unit includes a first degradation resistor, a second degradation resistor, and a third degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to the source of the first PMOS transistor, the other end of the second degradation resistor is connected to the source of the second PMOS transistor, and the other end of the third degradation resistor is connected to the source of the third PMOS transistor.

[0024] The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor, including:

[0025] The voltage comparison unit compares the source voltage of the first PMOS transistor and the source voltage of the second PMOS transistor.

[0026] Optionally, comparing the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor using the voltage comparison unit includes:

[0027] The voltage comparison unit compares the source voltage of the first PMOS transistor with the source voltage of the third PMOS transistor.

[0028] Optionally, the calibration code adjustment unit adjusts the resistance value of the resistor unit or adjusts the width-to-length ratio of the second PMOS transistor according to the first comparison result, including:

[0029] The correction code adjustment unit adjusts the width-to-length ratio of the second PMOS transistor according to the first comparison result.

[0030] Optionally, the calibration code adjustment unit adjusts the resistance value of the resistor unit or adjusts the width-to-length ratio of the third PMOS transistor according to the third comparison result, including:

[0031] The correction code adjustment unit adjusts the width-to-length ratio of the third PMOS transistor according to the third comparison result.

[0032] Optionally, the resistor unit includes a first degradation resistor, a second degradation resistor, a third degradation resistor, a first adjustable degradation resistor, a second adjustable degradation resistor, and a third adjustable degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to one end of the first adjustable degradation resistor, and the other end of the first adjustable degradation resistor is connected to the source of the first PMOS transistor. The other end of the second degradation resistor is connected to one end of the second adjustable degradation resistor, and the other end of the second adjustable degradation resistor is connected to the source of the second PMOS transistor. The other end of the third degradation resistor is connected to one end of the third adjustable degradation resistor, and the other end of the third adjustable degradation resistor is connected to the source of the third PMOS transistor.

[0033] The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor, including:

[0034] The voltage comparison unit compares the voltage at one end of the first adjustable degradation resistor with the voltage at one end of the second adjustable degradation resistor.

[0035] Optionally, comparing the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor using the voltage comparison unit includes:

[0036] The voltage comparison unit compares the voltage at one end of the first adjustable degradation resistor with the voltage at one end of the third adjustable degradation resistor.

[0037] Optionally, the calibration code adjustment unit adjusts the resistance value of the resistor unit or adjusts the width-to-length ratio of the second PMOS transistor according to the first comparison result, including:

[0038] The correction code adjustment unit adjusts the resistance value of the second adjustable degradation resistor based on the first comparison result.

[0039] Optionally, the calibration code adjustment unit adjusts the resistance value of the resistor unit or adjusts the width-to-length ratio of the third PMOS transistor according to the third comparison result, including:

[0040] The correction code adjustment unit adjusts the resistance value of the third adjustable degradation resistor based on the third comparison result.

[0041] The beneficial effects of this invention are as follows: the voltage comparison unit is used to compare the magnitudes of the voltages on the source input lines of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, as well as the magnitudes of the drain voltages of the first PMOS transistor and the second PMOS transistor; the correction code adjustment unit is used to adjust the resistance value of the resistor unit or adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit; the correction code adjustment unit is also used to adjust the offset correction unit according to the comparison result of the voltage comparison unit, thereby reducing the voltage error output by the bandgap reference source circuit. Attached Figure Description

[0042] Figure 1 This is a bandgap reference source circuit in the prior art;

[0043] Figure 2 This is yet another bandgap reference source circuit in the prior art;

[0044] Figure 3 This is a circuit diagram of a bandgap reference source circuit in some embodiments of the present invention;

[0045] Figure 4 This is a circuit diagram of a bandgap reference source circuit in some other embodiments of the present invention;

[0046] Figure 5 This is a circuit diagram of a voltage comparison unit in some embodiments of the present invention;

[0047] Figure 6 This is a flowchart of an in-situ background calibration method for a bandgap reference source circuit in some embodiments of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0049] To address the problems existing in the prior art, embodiments of the present invention provide a bandgap reference source circuit. (Refer to...) Figure 3 and Figure 4 The bandgap reference source circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1, a second resistor R2, an error amplifier, a resistor unit, an offset correction unit, a voltage comparator unit, and a correction code adjustment unit. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the resistor unit. The gates of the first PMOS transistor and the second PMOS transistor MP2, the third PMOS transistor MP3, and the resistor unit are connected to the resistor unit. The output of the error amplifier is connected as follows: the drain of the first PMOS transistor MP1 is connected to the emitter of the first transistor Q1, and the base and collector of the first transistor Q1 are both grounded; the drain of the second PMOS transistor MP2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the emitter of the second transistor Q2, and the base and collector of the second transistor Q2 are both grounded; the drain of the third PMOS transistor MP3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the emitter of the third transistor Q3, and the base and collector of the third transistor Q3 are both grounded.

[0050] The offset correction unit is used to adjust the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor. The voltage comparison unit is used to compare the magnitudes of the voltages on the source input lines of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, as well as the magnitudes of the drain voltages of the first PMOS transistor and the second PMOS transistor. The correction code adjustment unit is used to adjust the resistance value of the resistor unit or adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit. The correction code adjustment unit is also used to adjust the offset correction unit according to the comparison result of the voltage comparison unit.

[0051] Figure 5 This is a circuit diagram of a voltage comparison unit in some embodiments of the present invention. (Refer to...) Figure 5 The voltage comparison unit includes a multiplexer circuit (MUX) and a comparator module (AZC). The first output terminal of the multiplexer circuit (MUX) is connected to the first input terminal of the comparator module (AZC), and the second output terminal of the multiplexer circuit (MUX) is connected to the second input terminal of the comparator module (AZC). Specifically, the comparator module (AZC) is an automatic zero-return comparator.

[0052] Reference Figure 3 The resistor unit includes a first degradation resistor RD1, a second degradation resistor RD2, and a third degradation resistor RD3. One end of the first degradation resistor RD1, one end of the second degradation resistor RD2, and one end of the third degradation resistor RD3 are all connected to the power supply voltage. The other end of the first degradation resistor RD1 is connected to the source of the first PMOS transistor MP1, the other end of the second degradation resistor RD2 is connected to the source of the second PMOS transistor MP2, and the other end of the third degradation resistor RD3 is connected to the source of the third PMOS transistor MP3. The first input terminal of the multiplexing circuit is connected to the source VS1 of the first PMOS transistor MP1, the second input terminal of the multiplexing circuit is connected to the drain VDP of the first PMOS transistor MP1, the third input terminal of the multiplexing circuit is connected to the drain VDN of the second PMOS transistor MP2, the fourth input terminal of the multiplexing circuit is connected to the source VS2 of the second PMOS transistor MP2, and the fifth input terminal of the multiplexing circuit is connected to the source VS3 of the third PMOS transistor MP3. The correction code adjustment unit is used to adjust the width-to-length ratio of the second PMOS transistor MP2 and the third PMOS transistor MP3 according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

[0053] Reference Figure 4The resistor unit includes a first degradation resistor RD1, a second degradation resistor RD2, a third degradation resistor RD3, a first adjustable degradation resistor RD1b, a second adjustable degradation resistor RD2b, and a third adjustable degradation resistor RD3b. One end of the first degradation resistor RD1, one end of the second degradation resistor RD2, and one end of the third degradation resistor RD3 are all connected to the power supply voltage. The other end of the first degradation resistor RD1 is connected to one end of the first adjustable degradation resistor RD1b, and the other end of the first adjustable degradation resistor RD1b is connected to the source of the first PMOS transistor MP1. The other end of the second degradation resistor RD2 is connected to one end of the second adjustable degradation resistor RD2b, and the other end of the second adjustable degradation resistor RD2b is connected to the source of the second PMOS transistor MP2. The other end of the third degradation resistor RD3 is connected to one end of the third adjustable degradation resistor RD3b, and the other end of the third adjustable degradation resistor RD3b is connected to the source of the third PMOS transistor MP3. The first input terminal of the multiplexing circuit is connected to the other end VS11 of the first degradation resistor RD1. The second input terminal of the multiplexing circuit is connected to the drain VDP of the first PMOS transistor MP1. The third input terminal of the multiplexing circuit is connected to the drain VDN of the second PMOS transistor MP2. The fourth input terminal of the multiplexing circuit is connected to the other end VS21 of the second degradation resistor RD2. The fifth input terminal of the multiplexing circuit is connected to the other end VS31 of the third degradation resistor RD3. The correction code adjustment unit is used to adjust the resistance values ​​of the first adjustable degradation resistor RD1b, the second adjustable degradation resistor RD2b, and the third adjustable degradation resistor RD3b according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

[0054] Figure 6 This is a flowchart illustrating the in-situ background calibration method for a bandgap reference source circuit in some embodiments of the present invention. (Refer to...) Figure 6 The in-situ background calibration method for the bandgap reference source circuit includes the following steps:

[0055] S1: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor are compared by the voltage comparison unit to obtain a first comparison result;

[0056] S2: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result, and then executes step S1 until the first comparison result output by the voltage comparison unit is flipped.

[0057] S3: The voltage comparison unit compares the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor to obtain a second comparison result;

[0058] S4: The correction code adjustment unit adjusts the offset correction unit according to the second comparison result, and then step S3 is executed until the second comparison result output by the voltage comparison unit is flipped.

[0059] S5: Repeat steps S1 to S4 several times;

[0060] S6: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor are compared by the voltage comparison unit to obtain a third comparison result;

[0061] S7: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result, and then executes step S6 until the third comparison result output by the voltage comparison unit flips.

[0062] Reference Figure 3 The resistor unit includes a first degradation resistor RD1, a second degradation resistor RD2, and a third degradation resistor RD3. One end of the first degradation resistor RD1, one end of the second degradation resistor RD2, and one end of the third degradation resistor RD3 are all connected to the power supply voltage. The other end of the first degradation resistor RD1 is connected to the source of the first PMOS transistor MP1, the other end of the second degradation resistor RD2 is connected to the source of the second PMOS transistor MP2, and the other end of the third degradation resistor RD3 is connected to the source of the third PMOS transistor MP3.

[0063] Comparing the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor using the voltage comparison unit includes: comparing the source voltage of the first PMOS transistor and the source voltage of the second PMOS transistor using the voltage comparison unit.

[0064] The voltage comparison method of the voltage comparison unit includes comparing the source voltage of the first PMOS transistor and the source voltage of the third PMOS transistor.

[0065] The method of adjusting the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result includes: adjusting the width-to-length ratio of the second PMOS transistor according to the first comparison result so that the current I2 approaches the current I1.

[0066] The method of adjusting the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result includes: adjusting the width-to-length ratio of the third PMOS transistor according to the third comparison result so that the current I3 approaches the current I1.

[0067] Reference Figure 3 The second PMOS transistor MP2 has a first correction code, and the aspect ratio of the second PMOS transistor MP2 can be adjusted by adjusting the first correction code. For example, the first correction code is a 6-bit correction code, corresponding to 64 aspect ratios of the second PMOS transistor MP2.

[0068] In some embodiments, reference is made to Figure 3 The first correction code is a 6-bit correction code, and its initial value is set to 000000. At this time, the width-to-length ratio of the second PMOS transistor MP2 is n0, which is the initial state of the second PMOS transistor MP2. However, there is no specific restriction on the initial value of the first correction code. The source voltage of the first PMOS transistor MP1 and the source voltage of the second PMOS transistor MP2 are compared by the voltage comparison unit to obtain a first comparison result. If the first comparison result is 1, the correction code adjustment unit increments the first correction code by 1, that is, the first correction code becomes 000001, and the width-to-length ratio of the second PMOS transistor MP2 is n1. The first comparison result is also obtained by comparing the source voltage of the first PMOS transistor MP1 and the source voltage of the second PMOS transistor MP2 by the voltage comparison unit. If the first comparison result is 1, the correction code adjustment unit increments the first correction code by 1, that is, the first correction code becomes 000010, and the width-to-length ratio of the second PMOS transistor MP2 is n2. This process continues until the first comparison result becomes 0, or the first correction code becomes 111111.

[0069] In some other embodiments, reference is made to Figure 3The first correction code is a 6-bit correction code. The initial value of the first correction code is set to 111000. At this time, the width-to-length ratio of the second PMOS transistor MP2 is n56, which is the initial state of the second PMOS transistor MP2. However, there is no specific restriction on the initial value of the first correction code. The voltage comparison unit compares the source voltage of the first PMOS transistor MP1 and the source voltage of the second PMOS transistor MP2 to obtain a first comparison result. If the first comparison result is 0, the correction code adjustment unit decrements the first correction code by 1, i.e., the first correction code becomes 110111. At this time, the width-to-length ratio of the second PMOS transistor MP2 is n55. The voltage comparison unit then compares the source voltage of the first PMOS transistor MP1 and the source voltage of the second PMOS transistor MP2 to obtain a first comparison result. If the first comparison result is 0, the correction code adjustment unit decrements the first correction code by 1, i.e., the first correction code becomes 110110. At this time, the width-to-length ratio of the second PMOS transistor MP2 is n54. This process continues until the first comparison result becomes 1, or the first correction code becomes 000000.

[0070] Reference Figure 3 The third PMOS transistor MP3 has a second correction code, which adjusts the aspect ratio of the third PMOS transistor MP3. For example, the second correction code is a 6-bit correction code, corresponding to 64 aspect ratios of the third PMOS transistor MP3. The adjustment process of the second correction code is the same as that of the first correction code, and will not be repeated here.

[0071] Reference Figure 3 and Figure 4 The offset correction unit has a third correction code. By adjusting the third correction code, the offset correction unit can be adjusted, thereby regulating the drain voltage of the first PMOS transistor MP1 and the drain voltage of the second PMOS transistor MP2. For example, the third correction code is a 6-bit correction code, corresponding to 64 adjustment modes of the offset correction unit. The specific circuits of the offset correction unit and the correction code adjustment unit are well-known technologies in the art and will not be described in detail here.

[0072] Reference Figure 4The resistor unit includes a first degradation resistor RD1, a second degradation resistor RD2, a third degradation resistor RD3, a first adjustable degradation resistor RD1b, a second adjustable degradation resistor RD2b, and a third adjustable degradation resistor RD3b. One end of the first degradation resistor RD1, one end of the second degradation resistor RD2, and one end of the third degradation resistor RD3 are all connected to the power supply voltage. The other end of the first degradation resistor RD1 is connected to one end of the first adjustable degradation resistor RD1b, and the other end of the first adjustable degradation resistor RD1b is connected to the source of the first PMOS transistor MP1. The other end of the second degradation resistor RD2 is connected to one end of the second adjustable degradation resistor RD2b, and the other end of the second adjustable degradation resistor RD2b is connected to the source of the second PMOS transistor MP2. The other end of the third degradation resistor RD3 is connected to one end of the third adjustable degradation resistor RD3b, and the other end of the third adjustable degradation resistor RD3b is connected to the source of the third PMOS transistor MP3.

[0073] The voltage comparison method of the voltage comparison unit includes comparing the voltage at one end of the first adjustable degradation resistor and the voltage at one end of the second adjustable degradation resistor.

[0074] The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor, including: comparing the voltage at one end of the first adjustable degradation resistor and the voltage at one end of the third adjustable degradation resistor.

[0075] The method of adjusting the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result includes: adjusting the resistance value of the second adjustable degradation resistor according to the first comparison result so that the current I2 approaches the current I1.

[0076] The method of adjusting the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result includes: adjusting the resistance value of the third adjustable degradation resistor according to the third comparison result so that the current I3 approaches the current I1.

[0077] Reference Figure 4The second adjustable degradation resistor RD2b has a fourth correction code, and the resistance value of the second adjustable degradation resistor RD2b can be adjusted by adjusting the fourth correction code. For example, the fourth correction code is a 6-bit correction code, corresponding to 64 resistance values ​​of the second adjustable degradation resistor RD2b. The adjustment process of the fourth correction code is the same as that of the first correction code, and will not be repeated here.

[0078] Reference Figure 4 The third adjustable degradation resistor RD3b has a fifth correction code, and the resistance value of the third adjustable degradation resistor RD3b can be adjusted by adjusting the fifth correction code. For example, the fifth correction code is a 6-bit correction code, corresponding to 64 resistance values ​​of the third adjustable degradation resistor RD3b. The adjustment process of the fifth correction code is the same as that of the first correction code, and will not be repeated here.

[0079] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A bandgap reference source circuit, characterized in that, This system includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, an error amplifier, a resistor unit, an offset correction unit, a voltage comparator unit, and a correction code adjustment unit. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the resistor unit. The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to the output of the error amplifier. The drain of the first PMOS transistor is connected to the emitter of the first transistor. The base and collector of the first transistor are both grounded. The drain of the second PMOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the emitter of the second transistor. The base and collector of the second transistor are both grounded. The drain of the third PMOS transistor is connected to the... One end of the second resistor is connected, and the other end of the second resistor is connected to the emitter of the third transistor. The base and collector of the third transistor are both grounded. The offset correction unit is used to adjust the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor. The voltage comparison unit is used to compare the magnitudes of the voltages on the source input lines of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, as well as the magnitudes of the drain voltages of the first PMOS transistor and the second PMOS transistor. The correction code adjustment unit is used to adjust the resistance value of the resistor unit or adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit. The correction code adjustment unit is also used to adjust the offset correction unit according to the comparison result of the voltage comparison unit.

2. The bandgap reference source circuit according to claim 1, characterized in that, The resistor unit includes a first degradation resistor, a second degradation resistor, and a third degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to the source of the first PMOS transistor, the other end of the second degradation resistor is connected to the source of the second PMOS transistor, and the other end of the third degradation resistor is connected to the source of the third PMOS transistor.

3. The bandgap reference source circuit according to claim 2, characterized in that, The voltage comparison unit includes a multiplexing circuit and a comparison module. The first input terminal of the multiplexing circuit is connected to the source of the first PMOS transistor, the second input terminal of the multiplexing circuit is connected to the drain of the first PMOS transistor, the third input terminal of the multiplexing circuit is connected to the drain of the second PMOS transistor, the fourth input terminal of the multiplexing circuit is connected to the source of the second PMOS transistor, the fifth input terminal of the multiplexing circuit is connected to the source of the third PMOS transistor, the first output terminal of the multiplexing circuit is connected to the first input terminal of the comparison module, and the second output terminal of the multiplexing circuit is connected to the second input terminal of the comparison module.

4. The bandgap reference source circuit according to claim 3, characterized in that, The correction code adjustment unit is used to adjust the width-to-length ratio of the second PMOS transistor and the third PMOS transistor according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

5. The bandgap reference source circuit according to claim 1, characterized in that, The resistor unit includes a first degradation resistor, a second degradation resistor, a third degradation resistor, a first adjustable degradation resistor, a second adjustable degradation resistor, and a third adjustable degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to one end of the first adjustable degradation resistor, and the other end of the first adjustable degradation resistor is connected to the source of the first PMOS transistor. The other end of the second degradation resistor is connected to one end of the second adjustable degradation resistor, and the other end of the second adjustable degradation resistor is connected to the source of the second PMOS transistor. The other end of the third degradation resistor is connected to one end of the third adjustable degradation resistor, and the other end of the third adjustable degradation resistor is connected to the source of the third PMOS transistor.

6. The bandgap reference source circuit according to claim 5, characterized in that, The voltage comparison unit includes a multiplexing circuit and a comparison module. The first input terminal of the multiplexing circuit is connected to the other end of the first degradation resistor. The second input terminal of the multiplexing circuit is connected to the drain of the first PMOS transistor. The third input terminal of the multiplexing circuit is connected to the drain of the second PMOS transistor. The fourth input terminal of the multiplexing circuit is connected to the other end of the second degradation resistor. The fifth input terminal of the multiplexing circuit is connected to the other end of the third degradation resistor. The first output terminal of the multiplexing circuit is connected to the first input terminal of the comparison module. The second output terminal of the multiplexing circuit is connected to the second input terminal of the comparison module.

7. The bandgap reference source circuit according to claim 6, characterized in that, The correction code adjustment unit is used to adjust the resistance values ​​of the first adjustable degradation resistor, the second adjustable degradation resistor, and the third adjustable degradation resistor according to the comparison result of the voltage comparison unit, and to adjust the offset correction unit.

8. The bandgap reference source circuit according to claim 3 or 6, characterized in that, The comparison module is an automatic zeroing comparator.

9. An in-situ background calibration method for a bandgap reference source circuit as described in claim 1, characterized in that, Includes the following steps: S1: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor are compared by the voltage comparison unit to obtain a first comparison result; S2: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result, and then executes step S1 until the first comparison result output by the voltage comparison unit is flipped. S3: The voltage comparison unit compares the drain voltage of the first PMOS transistor and the drain voltage of the second PMOS transistor to obtain a second comparison result; S4: The correction code adjustment unit adjusts the offset correction unit according to the second comparison result, and then step S3 is executed until the second comparison result output by the voltage comparison unit is flipped. S5: Repeat steps S1 to S4 several times; S6: The voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the third PMOS transistor are compared by the voltage comparison unit to obtain a third comparison result; S7: The correction code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result, and then executes step S6 until the third comparison result output by the voltage comparison unit flips.

10. The in-situ background calibration method for the bandgap reference source circuit according to claim 9, characterized in that, The resistor unit includes a first degradation resistor, a second degradation resistor, and a third degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to the source of the first PMOS transistor, the other end of the second degradation resistor is connected to the source of the second PMOS transistor, and the other end of the third degradation resistor is connected to the source of the third PMOS transistor. The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor, including: The voltage comparison unit compares the source voltage of the first PMOS transistor and the source voltage of the second PMOS transistor.

11. The in-situ background calibration method for the bandgap reference source circuit according to claim 10, characterized in that, The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor with the voltage on the source input line of the third PMOS transistor, including: The voltage comparison unit compares the source voltage of the first PMOS transistor with the source voltage of the third PMOS transistor.

12. The in-situ background calibration method for the bandgap reference source circuit according to claim 10, characterized in that, The calibration code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result, including: The correction code adjustment unit adjusts the width-to-length ratio of the second PMOS transistor according to the first comparison result.

13. The in-situ background calibration method for the bandgap reference source circuit according to claim 11, characterized in that, The calibration code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result, including: The correction code adjustment unit adjusts the width-to-length ratio of the third PMOS transistor according to the third comparison result.

14. The in-situ background calibration method for the bandgap reference source circuit according to claim 9, characterized in that, The resistor unit includes a first degradation resistor, a second degradation resistor, a third degradation resistor, a first adjustable degradation resistor, a second adjustable degradation resistor, and a third adjustable degradation resistor. One end of the first degradation resistor, one end of the second degradation resistor, and one end of the third degradation resistor are all connected to the power supply voltage. The other end of the first degradation resistor is connected to one end of the first adjustable degradation resistor, and the other end of the first adjustable degradation resistor is connected to the source of the first PMOS transistor. The other end of the second degradation resistor is connected to one end of the second adjustable degradation resistor, and the other end of the second adjustable degradation resistor is connected to the source of the second PMOS transistor. The other end of the third degradation resistor is connected to one end of the third adjustable degradation resistor, and the other end of the third adjustable degradation resistor is connected to the source of the third PMOS transistor. The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor and the voltage on the source input line of the second PMOS transistor, including: The voltage comparison unit compares the voltage at one end of the first adjustable degradation resistor with the voltage at one end of the second adjustable degradation resistor.

15. The in-situ background calibration method for the bandgap reference source circuit according to claim 14, characterized in that, The voltage comparison unit compares the voltage on the source input line of the first PMOS transistor with the voltage on the source input line of the third PMOS transistor, including: The voltage comparison unit compares the voltage at one end of the first adjustable degradation resistor with the voltage at one end of the third adjustable degradation resistor.

16. The in-situ background calibration method for the bandgap reference source circuit according to claim 14, characterized in that, The calibration code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the second PMOS transistor according to the first comparison result, including: The correction code adjustment unit adjusts the resistance value of the second adjustable degradation resistor based on the first comparison result.

17. The in-situ background calibration method for the bandgap reference source circuit according to claim 15, characterized in that, The calibration code adjustment unit adjusts the resistance value of the resistor unit or the width-to-length ratio of the third PMOS transistor according to the third comparison result, including: The correction code adjustment unit adjusts the resistance value of the third adjustable degradation resistor based on the third comparison result.

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