Command decoding circuit and method thereof, semiconductor memory

Abstract

Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module configured to receive an initial clock signal, perform frequency division and phase division processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; a command sampling module configured to receive a command address signal, and sample the command address signal using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal respectively, and output a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; and a decoding module configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal, and output a target decoding signal. Embodiments of the present disclosure can realize correct decoding of a command signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a command decoding circuit and method thereof, and a semiconductor memory. Background Technology

[0002] With the continuous development of semiconductor technology, the design principles and operating details of memory are also being updated. Various circuits inside the memory need to be improved according to new requirements in order to meet design requirements and achieve better storage performance. Summary of the Invention

[0003] This disclosure provides a command decoding circuit and method, and a semiconductor memory, which can correctly decode command address signals.

[0004] In a first aspect, embodiments of this disclosure provide a command decoding circuit, the command decoding circuit comprising:

[0005] The clock processing module is configured to receive an initial clock signal, perform frequency division and phase division processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees sequentially, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal;

[0006] The command sampling module, connected to the clock processing module, is configured to receive the command address signal; and to sample the command address signal using the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, and output the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal.

[0007] The decoding module is connected to the clock processing module and the command sampling module, and is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal, and output the target decoded signal.

[0008] In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in an odd-numbered clock cycle, the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in an odd-numbered clock cycle, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in an even-numbered clock cycle, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in an even-numbered clock cycle.

[0009] In some embodiments, the command decoding circuit further includes: a chip select sampling module connected to the clock processing module, configured to receive a chip select signal; sample the chip select signal using the first clock signal and the third clock signal respectively, and output a first chip select sampling signal and a second chip select sampling signal; wherein the chip select signal is used to indicate whether the command address signal is valid or invalid.

[0010] In some embodiments, the command address signal, the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal each include N sub-signals, and the command sampling module includes N command sampling units; the i-th command sampling unit is connected to the clock processing module and configured to delay the i-th sub-signal of the command address signal to obtain a signal to be processed; sample the signal to be processed using the first clock signal and output the i-th sub-signal of the first sampling signal; sample the signal to be processed using the second clock signal and output the i-th sub-signal of the second sampling signal; sample the signal to be processed using the third clock signal and output the i-th sub-signal of the third sampling signal; and sample the signal to be processed using the fourth clock signal and output the i-th sub-signal of the fourth sampling signal, wherein i and N are positive integers, and i is less than or equal to N.

[0011] In some embodiments, the i-th command sampling unit includes a first delay unit, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; wherein, the input terminal of the first delay unit receives the i-th sub-signal of the command address signal, and the output terminal of the first delay unit outputs the signal to be processed; the input terminal of the first flip-flop receives the signal to be processed, the clock terminal of the first flip-flop receives the first clock signal, and the output terminal of the first flip-flop outputs the i-th sub-signal of the first sampled signal; the input terminal of the second flip-flop receives the signal to be processed, the clock terminal of the second flip-flop receives the second clock signal, and the output terminal of the second flip-flop outputs the i-th sub-signal of the second sampled signal; the input terminal of the third flip-flop receives the signal to be processed, the clock terminal of the third flip-flop receives the third clock signal, and the output terminal of the third flip-flop outputs the i-th sub-signal of the third sampled signal; the input terminal of the fourth flip-flop receives the signal to be processed, the clock terminal of the fourth flip-flop receives the fourth clock signal, and the output terminal of the fourth flip-flop outputs the i-th sub-signal of the fourth sampled signal.

[0012] In some embodiments, the decoding module includes: a second delay unit connected to the clock processing module, configured to receive the first clock signal, delay the first clock signal, and output a first delayed clock signal; a third delay unit connected to the clock processing module, configured to receive the third clock signal, delay the third clock signal, and output a third delayed clock signal; and a decoding processing unit connected to the command sampling module, the second delay unit, and the third delay unit, configured to decode and sample N-bit sub-signals of the first sampled signal and the second sampled signal based on the third delayed clock signal, and output a first decoded signal; and to decode and sample N-bit sub-signals of the third sampled signal and the fourth sampled signal based on the first delayed clock signal, and output a second decoded signal; wherein the first decoded signal and the second decoded signal constitute the target decoded signal, the first decoded signal indicating the content of the command address signal in the first initial clock cycle; and the second decoded signal indicating the content of the command address signal in the second initial clock cycle, wherein the initial clock cycle refers to the clock cycle of the initial clock signal.

[0013] In some embodiments, the decoding processing unit includes: a first decoding unit connected to the command sampling module and the third delay unit, configured to perform logical operations on N-bit sub-signals of the first sampled signal and N-bit sub-signals of the second sampled signal to output a first intermediate signal; and to sample the first intermediate signal using the third delayed clock signal to output the first decoded signal; and a second decoding unit connected to the command sampling module and the second delay unit, configured to perform logical operations on N-bit sub-signals of the third sampled signal and N-bit sub-signals of the fourth sampled signal to output a second intermediate signal; and to sample the second intermediate signal using the first delayed clock signal to output the second decoded signal.

[0014] In some embodiments, N = 4; the first decoding unit includes a first logic unit and a fifth flip-flop; wherein, the input terminal of the first logic unit receives a 4-bit sub-signal of the first sampled signal and a 4-bit sub-signal of the second sampled signal, and the output terminal of the first logic unit outputs a first intermediate signal; the input terminal of the fifth flip-flop receives the first intermediate signal, the clock terminal of the fifth flip-flop receives the third delayed clock signal, and the output terminal of the fifth flip-flop outputs the first decoded signal.

[0015] In some embodiments, N = 4; the second decoding unit includes a second logic unit and a sixth flip-flop; the input of the second logic unit receives a 4-bit sub-signal of the third sampled signal and a 4-bit sub-signal of the fourth sampled signal, and the output of the second logic unit outputs a second intermediate signal; the input of the sixth flip-flop receives the second intermediate signal, the clock terminal of the sixth flip-flop receives the first delayed clock signal, and the output of the sixth flip-flop outputs the second decoding signal.

[0016] In some embodiments, the chip select sampling module includes a fourth delay unit, a seventh flip-flop, and an eighth flip-flop; wherein, the input of the fourth delay unit receives the chip select signal, and the output of the fourth delay unit outputs a chip select delay signal; the input of the seventh flip-flop receives the chip select delay signal, the clock terminal of the seventh flip-flop receives the first clock signal, and the output of the seventh flip-flop outputs the first chip select sampling signal; the input of the eighth flip-flop receives the chip select delay signal, the clock terminal of the eighth flip-flop receives the third clock signal, and the output of the eighth flip-flop outputs the second chip select sampling signal.

[0017] Secondly, embodiments of this disclosure provide a command decoding method, the method comprising:

[0018] The initial clock signal is divided by frequency and phase to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees sequentially, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal;

[0019] The command address signal is sampled using the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, and the first sampled signal, the second sampled signal, the third sampled signal, and the fourth sampled signal are output.

[0020] Based on the first clock signal and the third clock signal, the first sampled signal, the second sampled signal, the third sampled signal and the fourth sampled signal are decoded and sampled to output the target decoded signal.

[0021] In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in an odd-numbered period, the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in an odd-numbered period, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in an even-numbered period, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in an even-numbered period.

[0022] In some embodiments, the method further includes: sampling the chip select signal using the first clock signal and the third clock signal respectively, and outputting a first chip select sampling signal and a second chip select sampling signal; wherein the chip select signal is used to indicate whether the command address signal is valid or invalid.

[0023] Thirdly, embodiments of this disclosure provide a semiconductor memory including a command decoding circuit as described in any one of the first aspects.

[0024] In some embodiments, the semiconductor memory is dynamic random access memory (DRAM), and the semiconductor memory conforms to the LPDDR6 memory specification.

[0025] This disclosure provides a command decoding circuit and method, and a semiconductor memory. The initial clock signal is divided into frequency and phase to generate a first clock signal to a fourth clock signal. The first clock signal to the fourth clock signal are used to sample and decode the command address signal, thereby enabling the correct decoding of the command address signal. Attached Figure Description

[0026] Figure 1 A schematic diagram of the composition structure of a command decoding circuit provided in an embodiment of this disclosure;

[0027] Figure 2 A partial structural diagram of a command decoding circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0028] Figure 3 A partial structural diagram of a command decoding circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0029] Figure 4 A partial structural diagram of a command decoding circuit provided in an embodiment of this disclosure. Figure 3 ;

[0030] Figure 5 A schematic diagram of the composition structure of another command decoding circuit provided in an embodiment of this disclosure;

[0031] Figure 6 A partial structural diagram of a command decoding circuit provided in an embodiment of this disclosure. Figure 4 ;

[0032] Figure 7 A signal timing diagram provided in an embodiment of this disclosure;

[0033] Figure 8 A flowchart illustrating a command decoding method provided in an embodiment of this disclosure;

[0034] Figure 9 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0035] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0037] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0039] The following are explanations of the technical terms used in the embodiments of this disclosure, as well as the correspondences of some terms:

[0040] Dynamic Random Access Memory (DRAM);

[0041] Synchronous Dynamic Random Access Memory (SDRAM);

[0042] Double Data Rate (DDR);

[0043] Low-power DDR (LPDDR)

[0044] 6th generation LPDDR (LPDDR6)

[0045] D-type triggers (Data Flip-Flop or Delay Flip-Flop, DFF)

[0046] Command address input (Command / Address, CMD / ADD, or simply CA)

[0047] Chip Select Input (CS)

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0049] During memory operation, the CA and CS inputs need to be sampled and decoded based on the initial clock signal Clk. According to LPDDR6 specifications, the command portion of the CA input (hereinafter referred to as CA Command) lasts for two initial clock cycles. The CA Command needs to be sampled at the rising and falling edges of the first and second initial clock cycles. Similarly, the CS input also lasts for two initial clock cycles, and the CS input needs to be sampled at the rising edge of the first and second initial clock cycles. Here, the initial clock cycle refers to the clock cycle of the initial clock signal Clk.

[0050] Specifically, the CA Command is a group of signals consisting of four sub-signals, denoted as CA0, CA1, CA2, and CA3. See Table 1, which shows a partial truth table of LPDDR6 commands. In Table 1, both the CA Command and the CS input last for two initial clock cycles. R1 refers to the rising edge of the first initial clock cycle, F1 refers to the falling edge of the first initial clock cycle, R2 refers to the rising edge of the second initial clock cycle, and F2 refers to the falling edge of the first two initial clock cycles. For CS and CA0-CA3, "H" indicates a high-level state, "L" indicates a low-level state, and "X" indicates that the level is irrelevant. It should be understood that Table 1 is derived from the industry standard document LPDDR6 SPEC. Those skilled in the art can refer to LPDDR6 SPEC to understand the meaning of the terms and abbreviations involved, and this part does not affect the understanding of the embodiments of this disclosure, so it will not be described in detail here.

[0051] Table 1

[0052]

[0053]

[0054] As shown in Table 1, the command decoding circuit in the semiconductor memory needs to perform decoding processing based on the R1 sampling result of the CS input, the R2 sampling result of the CS input, the R1 sampling result of the CA Command, the F1 sampling result of the CA Command, the R2 sampling result of the CA Command, and the F2 sampling result of the CA Command to obtain the specific command of this CA Command (e.g., DES, NOP, PDE, SRE, ACT-1, ACT-2, etc.).

[0055] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the composition of a command decoding circuit 10 provided in an embodiment of this disclosure. Figure 1 As shown, the command decoding circuit 10 includes:

[0056] The clock processing module 11 is configured to receive an initial clock signal Clk, perform frequency division and phase division processing on the initial clock signal Clk, and output a first clock signal Clk_R0, a second clock signal Clk_F0, a third clock signal Clk_R1, and a fourth clock signal Clk_F1; wherein the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1, and the fourth clock signal Clk_F1 are a group of signals with the same clock period and phases that differ by 90 degrees sequentially, the rising edge of the first clock signal Clk_R0 is aligned with the rising edge of the initial clock signal Clk, and the clock period of the first clock signal Clk_R0 is twice the clock period of the initial clock signal Clk;

[0057] Command sampling module 12, connected to clock processing module 11, is configured to receive command address signal CA Command, and sample the command address signal CA Command using first clock signal Clk_R0, second clock signal Clk_F0, third clock signal Clk_R1, and fourth clock signal Clk_F1 respectively, and output first sampled signal CA. <n:0>_R0, second sampled signal CA <n:0>_F0, Third Sampling Signal CA <n:0>_R1 and the fourth sampled signal CA <n:0>_F1;

[0058] Decoding module 13, connected to clock processing module 11 and command sampling module 12, is configured to process the first sampled signal CA based on the first clock signal Clk_R0 and the third clock signal Clk_R1. <n:0>_R0, second sampled signal CA <n:0>_F0, Third Sampling Signal CA <n:0>_R1 and the fourth sampled signal CA <n:0>_F1 performs decoding and sampling processing, and outputs the target decoded signal.

[0059] It should be noted that the command decoding circuit 10 in this embodiment is applied to a semiconductor memory to fulfill the decoding requirement of the command address signal CA Command in LPDDR6. Furthermore, the command decoding circuit 10 can also be applied to various circuit scenarios with similar requirements. This embodiment will subsequently be explained and described using the decoding of the command address signal CA Command, but this does not constitute a limitation.

[0060] As mentioned earlier, the command address signal CA Command lasts for two initial clock cycles, where the initial clock cycle refers to the clock cycle of the initial clock signal Clk. Note that for... Figures 1 to 7 The corresponding text portion is as follows: the rising edge of the first initial clock cycle is represented by R0, the falling edge of the first initial clock cycle is represented by F0, the rising edge of the second initial clock cycle is represented by R1, and the falling edge of the second initial clock cycle is represented by F1. This part is different from Table 1.

[0061] It should be noted that the rising edge of the first clock signal Clk_R0 is aligned with the rising edge of the initial clock signal Clk in odd-numbered clock cycles, the rising edge of the second clock signal Clk_F0 is aligned with the falling edge of the initial clock signal Clk in odd-numbered clock cycles, the rising edge of the third clock signal Clk_R1 is aligned with the rising edge of the initial clock signal Clk in even-numbered clock cycles, and the rising edge of the fourth clock signal Clk_F1 is aligned with the falling edge of the initial clock signal Clk in even-numbered clock cycles.

[0062] In this way, the rising edges of the first clock signal Clk_R0 and the third clock signal Clk_R1 are alternately aligned with the rising edge of the initial clock signal Clk, and the rising edges of the second clock signal Clk_F0 and the fourth clock signal Clk_F1 are alternately aligned with the falling edge of the initial clock signal Clk. Therefore, the first sampling signal can indicate the sampling result of the command address signal CACommand at the rising edge of the first initial clock cycle, the second sampling signal can indicate the sampling result of the command address signal CACommand at the falling edge of the first initial clock cycle, the third sampling signal can indicate the sampling result of the command address signal CACommand at the rising edge of the second initial clock cycle, and the fourth sampling signal can indicate the sampling result of the command address signal CACommand at the falling edge of the second initial clock cycle. These results are then used for decoding, meeting the decoding requirements of LPDDR6 and enabling the semiconductor memory to operate correctly.

[0063] It should be noted that the clock processing module 11 may include a frequency division module and a phase division module; wherein,

[0064] The frequency divider module is configured to receive the initial clock signal Clk, divide the initial clock signal Clk by frequency, and output the divided clock signal; the clock period of the divided clock signal is twice the clock period of the initial clock signal Clk.

[0065] The phase-splitting module is connected to the frequency-splitting module and is configured to receive the frequency-splitting clock signal, perform phase-splitting processing on the frequency-splitting clock signal, and output the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1, and the fourth clock signal Clk_F1.

[0066] It should be noted that the frequency divider module can be implemented using a frequency divider component composed of NOT gates and D flip-flops; the phase divider module can be implemented using multiple D flip-flops and delay devices.

[0067] In some embodiments, the command address signal CA Command and the first sampling signal CA <n:0>_R0, second sampled signal CA <n:0>_F0, Third Sampling Signal CA <n:0>_R1 and the fourth sampled signal CA <n:0>_F1 includes N-bit sub-signals.

[0068] Taking N=4 as an example, the command address signal CA Command can include four sub-signals: CA0, CA1, CA2, and CA3. The first sampled signal CA... <n:0>_R0 can include four sub-signals: CA0_R0, CA1_R0, CA2_R0, and CA3_R0; the second sampled signal CA <n:0>_F0 can include four sub-signals: CA0_F0, CA1_F0, CA2_F0, and CA3_F0; the third sampled signal CA <n:0>_R1 can include four sub-signals: CA0_R1, CA1_R1, CA2_R1, and CA3_R1; the fourth sampling signal can include four sub-signals: CA0_F1, CA1_F1, CA2_F1, and CA3_F1. This embodiment will be explained using N=4 as an example, but the value of N can be adjusted according to the needs of the actual scenario.

[0069] Accordingly, see Figure 2 It shows a partial structural diagram of a command decoding circuit 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 2 As shown, the command sampling module 12 includes N command sampling units ( Figure 2 (Taking N=4 as an example). The i-th command sampling unit is connected to the clock processing module 11 and is configured to delay the i-th sub-signal of the command address signal CA Command to obtain the signal to be processed; it uses the first clock signal Clk_R0 to sample the signal to be processed and outputs the first sampled signal CA. <n:0>The i-th sub-signal of _R0; the signal to be processed is sampled using the second clock signal Clk_F0, and the second sampled signal CA is output. <n:0>The i-th sub-signal of _F0 is sampled using the third clock signal Clk_R1, and the third sampled signal CA is output. <n:0>The i-th sub-signal of _R1 is sampled using the fourth clock signal Clk_F1 to process the signal to be processed, and the fourth sampled signal CA is output. <n:0>The i-th sub-signal of _F1, where i and N are positive integers, and i is less than or equal to N.

[0070] In some embodiments, such as Figure 2 As shown, the i-th command sampling unit includes a first delay unit 121, a first flip-flop 122, a second flip-flop 123, a third flip-flop 124, and a fourth flip-flop 125. Figure 2 Only the devices in the first command sampling unit are labeled; the others can be understood by referring to the label.

[0071] The input of the first delay unit 121 receives the i-th sub-signal CAi of the command address signal, and the output of the first delay unit 121 outputs the signal to be processed CAi_D; the input of the first flip-flop 122 receives the signal to be processed CAi_D, the clock terminal of the first flip-flop 122 receives the first clock signal Clk_R0, and the output of the first flip-flop 122 outputs the i-th sub-signal CAi_R0 of the first sampled signal; the input of the second flip-flop 123 receives the signal to be processed CAi_D, the clock terminal of the second flip-flop 123 receives the second clock signal Clk_F0, and the second flip-flop... The output of flip-flop 123 outputs the i-th sub-signal CAi_F0 of the second sampled signal; the input of the third flip-flop 124 receives the signal to be processed CAi_D, the clock terminal of the third flip-flop 124 receives the third clock signal Clk_R1, and the output of the third flip-flop 124 outputs the i-th sub-signal CAi_R1 of the third sampled signal; the input of the fourth flip-flop 125 receives the signal to be processed CAi_D, the clock terminal of the fourth flip-flop 125 receives the fourth clock signal Clk_F1, and the output of the fourth flip-flop 125 outputs the i-th sub-signal CAi_F1 of the fourth sampled signal.

[0072] It should be noted that each command sampling unit has its own first delay unit, first flip-flop, second flip-flop, third flip-flop, and fourth flip-flop.

[0073] Taking N=4 as an example, for the first command sampling unit, the first delay unit 121 delays CA0 to output CA0_D, the first flip-flop 122 samples CA0_D using the first clock signal Clk_R0 to output CA0_R0, the second flip-flop 123 samples CA0_D using the second clock signal Clk_F0 to output CA0_F0, the third flip-flop 124 samples CA0_D using the third clock signal Clk_R1 to output CA0_R1, and the fourth flip-flop 125 samples CA0_D using the fourth clock signal Clk_F1 to output CA0_F1.

[0074] For the second command sampling unit, the first delay unit delays CA1 to output CA1_D, samples CA1_D using the first clock signal Clk_R0 through the first flip-flop to output CA1_R0, samples CA1_D using the second clock signal Clk_F0 through the second flip-flop to output CA1_F0, samples CA1_D using the third clock signal Clk_R1 through the third flip-flop to output CA1_R1, and samples CA1_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA1_F1.

[0075] For the third command sampling unit, the first delay unit delays CA2 to output CA2_D, samples CA2_D using the first clock signal Clk_R0 through the first flip-flop to output CA2_R0, samples CA2_D using the second clock signal Clk_F0 through the second flip-flop to output CA2_F0, samples CA2_D using the third clock signal Clk_R1 through the third flip-flop to output CA2_R1, and samples CA2_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA2_F1.

[0076] For the fourth command sampling unit, the first delay unit delays CA3 to output CA3_D, samples CA3_D using the first clock signal Clk_R0 through the first flip-flop to output CA3_R0, samples CA3_D using the second clock signal Clk_F0 through the second flip-flop to output CA3_F0, samples CA3_D using the third clock signal Clk_R1 through the third flip-flop to output CA3_R1, and samples CA3_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA3_F1.

[0077] Thus, CA0_R0, CA1_R0, CA2_R0, and CA3_R0 together constitute the aforementioned first sampling signal CA. <n:0>_R0, CA0_F0, CA1_F0, CA2_F0, and CA3_F0 together constitute the aforementioned second sampling signal CA. <n:0>_F0, CA0_R1, CA1_R1, CA2_R1, and CA3_R1 together constitute the aforementioned third sampling signal CA. <n:0>_R1, CA0_F1, CA1_F1, CA2_F1, and CA3_F1 together constitute the aforementioned fourth sampling signal CA. <n:0>_F1.

[0078] Here, the aforementioned first delay unit (or DlyTrim) can be constructed using conventional delay devices. Furthermore, the first delay unit can be designed as a circuit with adjustable delay parameters or a circuit with non-adjustable delay parameters; its function is to delay the command address signal to achieve delay matching between the command address signal and the four clock signals (the first clock signal to the fourth clock signal).

[0079] In some embodiments, such as Figure 3 ( Figure 3 (Taking N=4 as an example) As shown, the decoding module 13 includes:

[0080] The second delay unit 131 is connected to the clock processing module 11 and is configured to receive the first clock signal Clk_R0, delay the first clock signal Clk_R0, and output the first delayed clock signal Clk_R0d.

[0081] The third delay unit 132 is connected to the clock processing module 11 and is configured to receive the third clock signal Clk_R1, delay the third clock signal Clk_R1, and output the third delayed clock signal Clk_R1d.

[0082] The decoding processing unit 133 is connected to the command sampling module 12, the second delay unit 131, and the third delay unit 132, and is configured to process the first sampled signal CA based on the third delayed clock signal Clk_R1d. <n:0>The N-bit sub-signal and the second sampled signal CA of _R0 <n:0>The N-bit sub-signal of _F0 is decoded and sampled to output the first decoded signal CmdR1; the third sampled signal CA is processed based on the first delayed clock signal Clk_R0d. <n:0>The N-bit sub-signal of _R1 and the N-bit sub-signal of the fourth sampled signal are decoded and sampled to output the second decoded signal CmdR0.

[0083] It should be noted that the first decoding signal CmdR1 and the second decoding signal CmdR0 constitute the target decoding signal. The first decoding signal CmdR1 indicates the content of the command address signal CA Command in the first initial clock cycle; the second decoding signal CmdR0 indicates the content of the command address signal CA Command in the second initial clock cycle. As mentioned above, the initial clock cycle refers to the clock cycle of the initial clock signal Clk.

[0084] It should be noted that the second delay unit 131 and the third delay unit 132 may have the same or different principles as the first delay unit. Specifically, the second delay unit 131 and the third delay unit 132 can also be referred to as ClkDly, and are also constructed using conventional delay devices. Furthermore, the second delay unit 131 (or the third delay unit 132) can be designed as a circuit with adjustable delay parameters, or it can be designed as a circuit with non-adjustable delay parameters. The function of the second delay unit 131 is to delay the first clock signal Clk_R0 to achieve delay matching between the first clock signal Clk_R0 and the first intermediate signal. The function of the second delay unit 131 is to delay the third clock signal Clk_R1 to achieve delay matching between the third clock signal Clk_R1 and the second intermediate signal.

[0085] In some embodiments, such as Figure 4 ( Figure 4 (Taking N=4 as an example) As shown, the decoding processing unit 133 includes:

[0086] The first decoding unit 21 is connected to the command sampling module 12 and the third delay unit 132, and is configured to process the first sampled signal CA. <n:0>The N-bit sub-signal and the second sampled signal CA of _R0 <n:0>The N-bit sub-signal of _F0 is used for logical operations to output the first intermediate signal; the first intermediate signal is sampled and processed using the third delayed clock signal Clk_R1d to output the first decoded signal CmdR1.

[0087] The second decoding unit 22 is connected to the command sampling module 12 and the second delay unit 131, and is configured to process the third sampling signal CA. <n:0>The N-bit sub-signal of _R1 and the fourth sampled signal CA <n:0>The N-bit sub-signal of _F1 is used for logical operation to output the second intermediate signal; the second intermediate signal is sampled and processed using the first delayed clock signal Clk_R0d to output the second decoded signal CmdR0.

[0088] In one specific embodiment, taking N=4 as an example, such as... Figure 5 As shown, the first decoding unit 21 includes a first logic unit 211 and a fifth flip-flop 212; wherein, the input terminal of the first logic unit 211 receives 4-bit sub-signals of the first sampled signal (i.e., CA0_R0, CA1_R0, CA2_R0, CA3_R0) and 4-bit sub-signals of the second sampled signal (i.e., CA0_F0, CA1_F0, CA2_F0, CA3_F0), and the output terminal of the first logic unit 211 outputs a first intermediate signal; the input terminal of the fifth flip-flop 212 receives the first intermediate signal, the clock terminal of the fifth flip-flop 212 receives a third delayed clock signal Clk_R1d, and the output terminal of the fifth flip-flop 212 outputs a first decoding signal CmdR1.

[0089] Similarly, such as Figure 4 As shown, the second decoding unit 22 includes a second logic unit 221 and a sixth flip-flop 222; the input terminal of the second logic unit 221 receives 4-bit sub-signals of the third sampled signal (i.e., CA0_R1, CA1_R1, CA2_R1, CA3_R1) and 4-bit sub-signals of the fourth sampled signal (i.e., CA0_F1, CA1_F1, CA2_F1, CA3_F1), and the output terminal of the second logic unit 221 outputs a second intermediate signal; the input terminal of the sixth flip-flop 222 receives the second intermediate signal, the clock terminal of the sixth flip-flop 222 receives the first delayed clock signal Clk_R1d, and the output terminal of the sixth flip-flop 222 outputs the second decoding signal CmdR0.

[0090] It should be noted that the first logic unit 211 (or the second logic unit 221) can be implemented by various logic devices, such as NAND gates, NOT gates, XOR gates, etc. The specific implementation needs to be determined according to the specific decoding rules (or decoding rules), and this disclosure does not limit it.

[0091] In this way, the command address signal CA Command is sampled using the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1, and the fourth clock signal Clk_F1. The sampling results of the command address signal CA Command at the rising edge of the first initial clock cycle, the falling edge of the command address signal CA Command at the falling edge of the first initial clock cycle, the rising edge of the command address signal CA Command at the second initial clock cycle, and the falling edge of the command address signal CA Command at the second initial clock cycle are obtained respectively. This allows for subsequent decoding processing, enabling correct decoding of the command address signal in LPDDR6 and ensuring the normal operation of the memory.

[0092] In addition, according to the LPDDR6 specification, the chip select signal CS also lasts for two initial clock cycles, and the chip select signal CS needs to be sampled at the rising edge of the first initial clock cycle and the rising edge of the second initial clock cycle.

[0093] Therefore, in some embodiments, such as Figure 5 As shown, the command decoding circuit 10 also includes:

[0094] The chip select sampling module 14 is connected to the clock processing module 11 and is configured to receive the chip select signal CS; and to sample the chip select signal CS using the first clock signal Clk_R0 and the third clock signal Clk_R1 respectively, and output the first chip select sampling signal CS_R0 and the second chip select sampling signal CS_R1.

[0095] It should be noted that the chip select signal CS is used to indicate whether the command address signal CA Command is valid or invalid. Here, the command decoding circuit 10 is applied to the semiconductor memory. If the semiconductor memory is selected, the waveform of the chip select signal CS meets the first condition, and the command address signal CA Command is valid; if the memory is not selected, the waveform of the chip select signal CS does not meet the first condition, and the command address signal CA Command is invalid.

[0096] For example, in Figure 2 On the basis of, such as Figure 6 As shown, the chip select sampling module 14 includes a fourth delay unit 141, a seventh flip-flop 142, and an eighth flip-flop 143. The input of the fourth delay unit 141 receives the chip select signal CS, and the output of the fourth delay unit 141 outputs a chip select delay signal CS_D. The input of the seventh flip-flop 142 receives the chip select delay signal CS_D, the clock terminal of the seventh flip-flop 142 receives the first clock signal Clk_R0, and the output of the seventh flip-flop 142 outputs the first chip select sampling signal CS_R0. The input of the eighth flip-flop 143 receives the chip select delay signal CS_D, the clock terminal of the eighth flip-flop 143 receives the third clock signal Clk_R1, and the output of the eighth flip-flop 143 outputs the second chip select sampling signal CS_R1.

[0097] It should be noted that the fourth delay unit 141 has the same structure as the first delay unit 121, meaning that the fourth delay unit 141 can also be implemented using various delay devices.

[0098] The aforementioned first to eighth flip-flops can all be implemented using D-type flip-flops, which can sample the input signal (i.e., the signal received at the input terminal) using the rising edge of the clock signal (i.e., the signal received at the clock terminal) to obtain the output signal (i.e., the signal at the output terminal). In addition, the first to sixth flip-flops 222 each have a reset terminal to receive the corresponding reset signal to realize the reset process.

[0099] Specifically, taking the command address signal CA Command, which includes 4 sub-signals, as an example, we will provide a detailed explanation of the signal timing changes. Please refer to [link to relevant documentation]. Figure 7 This illustrates a signal timing diagram provided in an embodiment of the present disclosure. Figure 7 In this context, the command address signal is represented as CA<3:0>, the first sampled signal is represented as CA<3:0>_R0, the second sampled signal is represented as CA<3:0>_F0, the third sampled signal is represented as CA<3:0>_R1, and the fourth sampled signal is represented as CA<3:0>_F1. For example... Figure 7 As shown, the initial clock signal Clk, after frequency division and phase splitting, generates a first clock signal Clk_R0, a second clock signal Clk_F0, a third clock signal Clk_R1, and a fourth clock signal Clk_F1. The first clock signal Clk_R0 generates the first sampling signal CA<3:0>_R0 from the sampling command address signal CA<3:0>. The second clock signal Clk_F0 generates the second sampling signal CA<3:0>_F0 from the sampling command address signal CA<3:0>. The third clock signal Clk_R1 generates the sampling command... The address signal CA<3:0> generates the third sampling signal CA<3:0>_R1, and the fourth clock signal Clk_F1 samples the command address signal CA<3:0> to generate the fourth sampling signal CA<3:0>_F1. Then, the first sampling signal CA<3:0>_R0, the second sampling signal CA<3:0>_F0, the third sampling signal CA<3:0>_R1, and the fourth sampling signal CA<3:0>_F1 are decoded to obtain the first decoded signal Cmd_R1 and the second decoded signal Cmd_R0. Figure 7 (Not shown); simultaneously, the first clock signal Clk_R0 samples the initial chip select signal CS to generate the first chip select sampling signal CS_R0, and the second clock signal Clk_R1 samples the initial chip select signal CS to generate the first chip select sampling signal CS_R1. Figure 7 (Not shown); Finally, the first decoding signal Cmd_R0, the second decoding signal Cmd_R1, the first chip select sampling signal CS_R0, and the second chip select sampling signal CS_R1 are jointly decoded, and the decoding result is sampled by the command sampling clock signal ClkCmd_R1 to obtain the final target command signal Command. Here, the target command signal Command can indicate the specific content of this CA Command, such as PDE, SRE, ACT-1, ACT-2, etc. in Table 1.

[0100] In addition, such as Figure 7 As shown, the initial state of the initial chip select signal CS is low. When the initial chip select signal CS generates two consecutive pulses, it indicates that the semiconductor memory is selected, that is, the CA Command is valid.

[0101] This disclosure provides a command decoding circuit that divides and phases an initial clock signal to generate four clock signals (i.e., the first clock signal to the fourth clock signal). These four clock signals are used to sample the command address signal, and the first and third clock signals are used to sample the chip select signal, so that the target command signal (Command) can be subsequently decoded. In this way, the command decoding circuit can sample and decode the command address signal and the chip select signal for two consecutive initial clock cycles, achieving correct command parsing.

[0102] In another embodiment of this disclosure, see Figure 8 This illustrates a flowchart of a command decoding method provided in an embodiment of this disclosure. Figure 8 As shown, the method includes:

[0103] S301: Perform frequency division and phase division processing on the initial clock signal to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees in sequence, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal.

[0104] S302: The command address signal is sampled using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal respectively, and the first sampled signal, the second sampled signal, the third sampled signal and the fourth sampled signal are output.

[0105] S303: Based on the first clock signal and the third clock signal, decode and sample the first sample signal, the second sample signal, the third sample signal and the fourth sample signal, and output the target decoded signal.

[0106] In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in an odd-numbered period, the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in an odd-numbered period, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in an even-numbered period, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in an even-numbered period.

[0107] In some embodiments, the chip select signal is sampled using a first clock signal and a third clock signal, respectively, and a first chip select sampled signal and a second chip select sampled signal are output; wherein, the chip select signal is used to indicate whether the command address signal is valid or invalid.

[0108] This disclosure provides a command decoding circuit that divides and phases an initial clock signal to generate four clock signals (i.e., the first clock signal to the fourth clock signal). These four clock signals are used to sample the command address signal, and the first and third clock signals are used to sample the chip select signal, so that the target command signal (Command) can be subsequently decoded. In this way, the command decoding circuit can sample and decode the command address signal and the chip select signal for two consecutive initial clock cycles, achieving correct command parsing.

[0109] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 9 This illustrates a schematic diagram of the structural composition of a semiconductor memory 40 provided in an embodiment of this disclosure. For example... Figure 9 As shown, the semiconductor memory 40 may include the command decoding circuit 10 described in any of the foregoing embodiments.

[0110] In this embodiment of the disclosure, the semiconductor memory 40 can be a dynamic random access memory (DRAM), and the semiconductor memory conforms to the LPDDR6 specification.

[0111] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0112] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A command decoding circuit, characterized in that, The command decoding circuit includes: The clock processing module is configured to receive an initial clock signal, perform frequency division and phase division processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees sequentially, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal; The command sampling module, connected to the clock processing module, is configured to receive the command address signal; and to sample the command address signal using the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, and output the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal. The decoding module, connected to the clock processing module and the command sampling module, is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal, and output the target decoded signal; The command address signal, the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal each include N sub-signals, and the command sampling module includes N command sampling units; The i-th command sampling unit is connected to the clock processing module and configured to delay the i-th sub-signal of the command address signal to obtain a signal to be processed; sample the signal to be processed using the first clock signal and output the i-th sub-signal of the first sampled signal; sample the signal to be processed using the second clock signal and output the i-th sub-signal of the second sampled signal; sample the signal to be processed using the third clock signal and output the i-th sub-signal of the third sampled signal; and sample the signal to be processed using the fourth clock signal and output the i-th sub-signal of the fourth sampled signal. Where i and N are positive integers, and i is less than or equal to N.

2. The command decoding circuit according to claim 1, characterized in that, The rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in an odd-numbered clock cycle, the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in an odd-numbered clock cycle, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in an even-numbered clock cycle, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in an even-numbered clock cycle.

3. The command decoding circuit according to any one of claims 1-2, characterized in that, The command decoding circuit also includes: A chip select sampling module, connected to the clock processing module, is configured to receive a chip select signal; sample the chip select signal using the first clock signal and the third clock signal respectively, and output a first chip select sampling signal and a second chip select sampling signal; The chip select signal is used to indicate whether the command address signal is valid or invalid.

4. The command decoding circuit according to claim 1, characterized in that, The i-th command sampling unit includes a first delay unit, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; wherein, The input terminal of the first delay unit receives the i-th sub-signal of the command address signal, and the output terminal of the first delay unit outputs the signal to be processed; The input terminal of the first flip-flop receives the signal to be processed, the clock terminal of the first flip-flop receives the first clock signal, and the output terminal of the first flip-flop outputs the i-th sub-signal of the first sampled signal. The input terminal of the second flip-flop receives the signal to be processed, the clock terminal of the second flip-flop receives the second clock signal, and the output terminal of the second flip-flop outputs the i-th sub-signal of the second sampled signal; The input terminal of the third flip-flop receives the signal to be processed, the clock terminal of the third flip-flop receives the third clock signal, and the output terminal of the third flip-flop outputs the i-th sub-signal of the third sampled signal. The input terminal of the fourth flip-flop receives the signal to be processed, the clock terminal of the fourth flip-flop receives the fourth clock signal, and the output terminal of the fourth flip-flop outputs the i-th sub-signal of the fourth sampled signal.

5. The command decoding circuit according to claim 1, characterized in that, The decoding module includes: The second delay unit is connected to the clock processing module and is configured to receive the first clock signal, delay the first clock signal, and output the first delayed clock signal. The third delay unit is connected to the clock processing module and is configured to receive the third clock signal, delay the third clock signal, and output the third delayed clock signal. The decoding processing unit is connected to the command sampling module, the second delay unit, and the third delay unit. It is configured to decode and sample the N-bit sub-signals of the first sampled signal and the second sampled signal based on the third delay clock signal, and output a first decoded signal; and to decode and sample the N-bit sub-signals of the third sampled signal and the fourth sampled signal based on the first delay clock signal, and output a second decoded signal. The first decoding signal and the second decoding signal constitute the target decoding signal. The first decoding signal indicates the content of the command address signal in the first initial clock cycle. The second decoding signal indicates the content of the command address signal in the second initial clock cycle. The initial clock cycle refers to the clock cycle of the initial clock signal.

6. The command decoding circuit according to claim 5, characterized in that, The decoding processing unit includes: The first decoding unit, connected to the command sampling module and the third delay unit, is configured to perform logical operations on the N-bit sub-signals of the first sampled signal and the N-bit sub-signals of the second sampled signal to output a first intermediate signal; and to sample the first intermediate signal using the third delayed clock signal to output the first decoded signal. The second decoding unit, connected to the command sampling module and the second delay unit, is configured to perform logical operations on the N-bit sub-signals of the third sampled signal and the N-bit sub-signals of the fourth sampled signal to output a second intermediate signal; and to sample the second intermediate signal using the first delayed clock signal to output the second decoded signal.

7. The command decoding circuit according to claim 6, characterized in that, N=4; the first decoding unit includes a first logic unit and a fifth flip-flop; wherein... The input terminal of the first logic unit receives a 4-bit sub-signal of the first sampled signal and a 4-bit sub-signal of the second sampled signal, and the output terminal of the first logic unit outputs a first intermediate signal; the input terminal of the fifth flip-flop receives the first intermediate signal, the clock terminal of the fifth flip-flop receives the third delayed clock signal, and the output terminal of the fifth flip-flop outputs the first decoded signal.

8. The command decoding circuit according to claim 6, characterized in that, N=4; the second decoding unit includes a second logic unit and a sixth flip-flop; The input terminal of the second logic unit receives the 4-bit sub-signal of the third sampling signal and the 4-bit sub-signal of the fourth sampling signal, and the output terminal of the second logic unit outputs the second intermediate signal; the input terminal of the sixth flip-flop receives the second intermediate signal, the clock terminal of the sixth flip-flop receives the first delayed clock signal, and the output terminal of the sixth flip-flop outputs the second decoded signal.

9. The command decoding circuit according to claim 3, characterized in that, The chip select sampling module includes a fourth delay unit, a seventh flip-flop, and an eighth flip-flop; wherein... The input terminal of the fourth delay unit receives the chip select signal, and the output terminal of the fourth delay unit outputs the chip select delay signal; The input of the seventh flip-flop receives the chip select delay signal, the clock terminal of the seventh flip-flop receives the first clock signal, and the output of the seventh flip-flop outputs the first chip select sampling signal. The input of the eighth flip-flop receives the chip select delay signal, the clock terminal of the eighth flip-flop receives the third clock signal, and the output terminal of the eighth flip-flop outputs the second chip select sampling signal.

10. A command decoding method, characterized in that, The method includes: The initial clock signal is divided by frequency and phase to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees sequentially, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal; The command address signal is sampled using the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, and the first sampled signal, the second sampled signal, the third sampled signal, and the fourth sampled signal are output. Based on the first clock signal and the third clock signal, the first sample signal, the second sample signal, the third sample signal and the fourth sample signal are decoded and sampled to output the target decoded signal; The command address signal, the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal all include N-bit sub-signals; The i-th sub-signal of the command address signal is delayed to obtain the signal to be processed; the signal to be processed is sampled using the first clock signal to output the i-th sub-signal of the first sampled signal; the signal to be processed is sampled using the second clock signal to output the i-th sub-signal of the second sampled signal; the signal to be processed is sampled using the third clock signal to output the i-th sub-signal of the third sampled signal; and the signal to be processed is sampled using the fourth clock signal to output the i-th sub-signal of the fourth sampled signal. Where i and N are positive integers, and i is less than or equal to N.

11. The command decoding method according to claim 10, characterized in that, The rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in an odd-numbered period; the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in an odd-numbered period; the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in an even-numbered period; and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in an even-numbered period.

12. The command decoding method according to claim 11, characterized in that, The method further includes: The chip select signal is sampled using the first clock signal and the third clock signal respectively, and the first chip select sampling signal and the second chip select sampling signal are output. The chip select signal is used to indicate whether the command address signal is valid or invalid.

13. A semiconductor memory, characterized in that, Includes the command decoding circuit as described in any one of claims 1 to 10.

14. The semiconductor memory according to claim 13, characterized in that, The semiconductor memory is a dynamic random access memory (DRAM), and the semiconductor memory conforms to the LPDDR6 memory specification.

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