Noise Mitigation in Single-Ended Links

Abstract

A data transmission system includes a first circuit, a second circuit, and a reference voltage generating circuit. The first circuit includes a transmitter, which is powered by a first power supply voltage and has an output terminal and an input terminal for receiving a data output signal. The second circuit includes a receiver, which is powered by a second power supply voltage and has a first input terminal coupled to the output terminal of the transmitter, a second input terminal for receiving a reference voltage, and an output terminal for providing a data input signal. The reference voltage generating circuit forms a reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.

Description

[0001] This application claims priority to provisional application US63 / 232,343 filed on August 12, 2021, the entire contents of which are incorporated herein by reference. Background Art

[0002] Modern single-ended data transmission systems offer density benefits that are critical at the system level compared to differential signaling. As we move to higher speeds and modulations, systems will continue to push single-ended schemes to maintain that benefit. The challenges to link performance (e.g., meeting bit error targets, power, area) also increase dramatically with the need for higher speeds.

[0003] Many of these systems are burst mode in nature. In other words, they remain in a low power state (called an idle state) when not in use, and transition to an active state (i.e., normal transmission or reception of data) when needed. The power delivery network (PDN) is burdened with handling this sudden change in load when the physical interface circuit (PHY) goes from an idle state to an active mode. The sudden demand for power looks like a step excitation to the PDN and causes typical networks to resonate at their natural frequencies. This resonant noise becomes a large source of error that the link must handle. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A data transmission system known in the prior art is shown in block diagram form;

[0005] Figure 2 shows, in partial block diagram and partial schematic form, a data transmission system according to some embodiments;

[0006] Figure 3 It helps to understand Figure 2 A set of timing diagrams for the operation of a data transmission system;

[0007] Figure 4 Shows when Figure 2 a graph of examples of heights and widths of data eyes measured at various data noise frequencies for a data transmission system of the invention; and

[0008] Figure 5 A data transmission system useful in a multi-stage data transmission system according to some embodiments is shown in partial block diagram and partial schematic form.

[0009] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0010] A data transmission system includes a first circuit, a second circuit, and a reference voltage generating circuit. The first circuit includes a transmitter, which is powered by a first power supply voltage and has an output terminal and an input terminal for receiving a data output signal. The second circuit includes a receiver, which is powered by a second power supply voltage and has a first input terminal coupled to the output terminal of the transmitter, a second input terminal for receiving a reference voltage, and an output terminal for providing a data input signal. The reference voltage generating circuit forms a reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.

[0011] A data transmission system includes a transmitter, a receiver and a reference voltage generating circuit. The transmitter is powered by a first power supply voltage and has an output terminal and an input terminal for receiving a data output signal. The receiver is powered by a second power supply voltage and has a first input terminal coupled to the output terminal of the transmitter, a second input terminal for receiving a reference voltage, and an output terminal for providing a data input signal. The reference voltage generating circuit includes a driver and a voltage divider. The driver is powered by the first power supply voltage and has an output terminal and an input terminal for receiving a predetermined signal. The voltage divider is powered by the second power supply voltage and is coupled to the output terminal of the driver and to the second input terminal of the receiver for providing a reference voltage thereto.

[0012] A method includes transmitting a data signal from a transmitter of a first integrated circuit operating at a first power supply voltage, the first integrated circuit having a first voltage reference terminal. Receiving the data signal in a receiver of a second integrated circuit operating at a second power supply voltage. The second integrated circuit has a second voltage reference terminal. The receiving includes comparing the data signal with a voltage on the second voltage reference terminal to provide a received data signal. A shared reference voltage is generated on the first voltage reference terminal and the second voltage reference terminal based on noise in both the first power supply voltage and the second power supply voltage.

[0013] Figure 1 A data transmission system 100 known in the art is shown in block diagram form. The data transmission system 100 is a single-ended system and includes an integrated circuit 110, an integrated circuit 120, and a transmission medium 130.

[0014] Integrated circuit 110 includes driver 111 and comparator 112. Driver 111 has a function of receiving a data signal labeled "DATA OUTA ”, an input terminal of a signal to be output, an output terminal connected to a terminal of the integrated circuit 110, and a terminal for receiving a signal marked “V DDA ” The power supply input terminal of the corrected supply voltage, which is the same as the corrected supply voltage specified as “V SSA "But not in Figure 1 The more negative supply voltage shown in FIG. 1 and FIG. 2 together form the total supply voltage of the integrated circuit 110. The comparator 112 has a positive input terminal connected to an integrated circuit terminal of the integrated circuit 110, a positive input terminal for receiving a positive input terminal labeled “V REFA "The negative input terminal of the reference voltage and the negative input terminal marked "DATA INA " signal output terminal.

[0015] Integrated circuit 120 includes driver 121 and comparator 122. Driver 121 has a function of receiving a data signal labeled "DATA OUTB ”, an input terminal of a signal to be output, an output terminal connected to a terminal of the integrated circuit 120, and a terminal for receiving a signal marked “V DDB ” The power supply input terminal of the corrected supply voltage, which is the same as the corrected supply voltage specified as “V SSB "But not in Figure 1 The more negative supply voltage shown in FIG. 1 and FIG. 2 together form the total supply voltage of integrated circuit 120. Comparator 122 has a positive input terminal connected to an integrated circuit terminal of integrated circuit 120, a positive input terminal for receiving a positive input terminal labeled “V REFB "The negative input terminal of the reference voltage and the negative input terminal marked "DATA INB " signal output terminal.

[0016] Transmission medium 130 has a left end connected to terminals of integrated circuit 110 and a right end connected to terminals of integrated circuit 120. Transmission medium 130 may be, for example, integrated circuit traces along a bus in a computer motherboard that connects a microprocessor with its associated memory.

[0017] Each of drivers 111 and 121 is shown with a resistor having a drive strength indicating that these drivers have a characteristic impedance matching the transmission medium 130 and a termination resistor ( Figure 110). In addition, the link is bidirectional such that data is sometimes transferred from integrated circuit 110 to integrated circuit 120, and data is sometimes transferred from integrated circuit 120 to integrated circuit 110. A typical implementation of data transfer system 100 is a physical interface of a graphics double data rate version 6 (gDDR6) synchronous dynamic random access memory (SDRAM) and a graphics processor having a gDDR6 memory controller. As technology has advanced, the operating speeds of gDDR memories have increased, such that typical gDDR6 data transfer speeds at the low-to-high transition and high-to-low transition of the memory clock have frequencies of several GHz. At such high speeds, it is necessary for the memory controller to train the link by providing precise timing delays so that data can be captured near the center of the "data eye," i.e., the time period and voltage range over which data can be reliably captured at high clock speeds.

[0018] The reference voltage at each end of the transmission medium 130 can be calibrated to provide the largest possible data eye. Each end of the communication link is susceptible to the voltage at V REFA and V REFB However, the noise sources at the ends of the transmission medium 130 are independent of each other because the power distribution networks are also independent. These independent noise sources tend to have different effects on the driver and receiver, resulting in a reduction in the data eye by reducing the eye height and reducing both.

[0019] Figure 2 A data transmission system 200 is shown in partial block diagram and partial schematic form according to some embodiments. The data transmission system 200 generally includes an integrated circuit 210, an integrated circuit 230, and a transmission medium 250.

[0020] Integrated circuit 210 includes transceiver 211, data strobe receiver 214, latch 217, data strobe driver 218, voltage divider 220 and buffer 223. Transceiver 211 includes transmitter 212 and receiver 213. Transmitter 212 has a D OUTA The input terminal of the signal, the output terminal connected to the first terminal of the integrated circuit 210, and the output terminal for receiving the first terminal of the integrated circuit 210 are marked as “V PHY-A The positive supply voltage is the power supply input terminal of the more negative supply voltage V SSA Together they form the total supply voltage for the integrated circuit 210. The receiver 213 has a positive input terminal connected to the first integrated circuit terminal, a positive input terminal for receiving a reference voltage V REFA The negative input terminal, output terminal, and the PHY-A The data strobe receiver 214 includes a resistor 215 and a comparator 216. The resistor 215 has a voltage for receiving V PHY-AThe comparator 216 operates as a data strobe receiver and has a positive input terminal connected to the second integrated circuit terminal for receiving a reference voltage V REFA The negative input terminal, output terminal, and the PHY-A The latch 217 is a clock-controlled D-type latch having a D input terminal connected to the output terminal of the receiver 213, a clock input terminal connected to the output terminal of the comparator 216, and a D input terminal for providing a D INA The Q input terminal of the signal. Transmitter 218 has an input terminal for receiving the alternating pattern of 1s and 0s labeled "1010" and an output terminal connected to the second integrated circuit terminal.

[0021] The voltage divider 220 includes a resistor 221 and a circuit element 222. The resistor 221 has a voltage for receiving V PHY-A The first terminal and the third terminal connected to the integrated circuit 210 and forming a voltage V REFA The second terminal of the circuit element 222 is connected to the second terminal of the resistor 221. The circuit element 222 has a first terminal connected to the second terminal of the resistor 221 and a second terminal connected to the ground. In some embodiments, the circuit element 222 is implemented by a tunable current source 224, which has a first terminal connected to the second terminal of the resistor 221 and a second terminal connected to the ground. In other embodiments, the circuit element 222 is implemented by a tunable resistor 225, which has a first terminal connected to the second terminal of the resistor 221 and a second terminal connected to the ground. In other embodiments, the circuit element 222 is implemented by a combination of a tunable current source and a tunable resistor. Buffer 223 is an optional buffer shown in dotted lines and has an input connected to the second terminal of the resistor 221 and an output connected to the negative input of the receivers 213 and 216.

[0022] Integrated circuit 230 includes transceiver 231, data strobe receiver 234, latch 237, data strobe transmitter 238 and driver 239. Transceiver 231 includes transmitter 232 and receiver 233. Transmitter 232 has a D OUTB The first terminal of the integrated circuit 230 has an input terminal for receiving a signal, an output terminal connected to the first terminal of the integrated circuit 230, and has a PHY-B The positive supply voltage is the power supply input terminal of the more negative supply voltage V SSB The receiver 233 has a positive input terminal connected to the first terminal of the integrated circuit 230, a positive input terminal for receiving a reference voltage V REFBThe data strobe receiver 234 includes a resistor 235 and a comparator 236. The resistor 235 has a voltage for receiving V PHY-B The first terminal and the second terminal connected to the integrated circuit 230 form a reference voltage V REFB The receiver 236 has a positive input terminal connected to the second terminal of the integrated circuit 230, and is used to receive a reference voltage V REFB The latch 237 is a clock-controlled D-type latch having a D input terminal connected to the output terminal of the receiver 233, a clock input terminal connected to the output terminal of the comparator 236, and a D input terminal for providing a D INB The Q output terminal of the signal. Transmitter 238 has an input terminal for receiving an alternating pattern of 1s and 0s labeled "1010" and an output terminal connected to the second terminal of integrated circuit 230. Driver 239 has an input terminal for receiving a logic high voltage labeled "1", connected to the third terminal of integrated circuit 230 and the negative input terminals of receivers 233 and 236 and forms a voltage V REFB The output terminal, and the PHY-B The power input terminal.

[0023] The transmission medium 250 interconnects the integrated circuit 210 and the integrated circuit 230, and includes a group of conductors 251 to 253. The conductor 251 has a first end connected to a first terminal of the integrated circuit 210 and a second end connected to a first terminal of the integrated circuit 230. The conductor 252 has a first end connected to a second terminal of the integrated circuit 210 and a second end connected to a second terminal of the integrated circuit 230. The conductor 253 has a first end connected to a third terminal of the integrated circuit 210 and a second end connected to a third terminal of the integrated circuit 230.

[0024] As will be described more fully below, driver 239 and voltage divider 220 are connected together via conductor 253 to form reference voltage generation circuit 260 .

[0025] The data transmission system 200 interconnects the integrated circuit 210 and the integrated circuit 230 bidirectionally via the transmission medium 250. Figure 2 In the example shown, integrated circuit 230 is a data processor with an integrated DDRx memory controller and physical layer interface circuits, and integrated circuit 210 is a DDRx memory. The design of data transmission system 200 will vary based on the type of DDRx memory used. For DDR1, such as Figure 1As shown, the integrated circuit 230 uses the data (DQ) signal to send and receive data from the integrated circuit 210 based on the transition of the single-ended data strobe signal (DQS). Other generations of DDRx memory will contain modifications of the data transmission system 200. In another example, the integrated circuit 230 is a graphics processing unit (GPU) with an integrated gDDR memory controller and physical layer interface circuit, and the integrated circuit 210 is a gDDR memory, such as a gDDR6 SDRAM or a subsequent gDDR version. According to the gDDR6 standard, the data (DQ) terminal is a bidirectional terminal, but the clock signal is a unidirectional differential signal, where the processor provides a differential write clock signal (WCK_t and WCK_c) during both the read cycle and the write cycle. In yet another example, the integrated circuit 230 is a central processing unit (CPU) with an integrated DDR memory controller and physical layer interface circuit, and the integrated circuit 210 is a DDR5 SDRAM. According to the DDR5 standard, the data (DQ) terminal is a bidirectional terminal captured based on a bidirectional differential data strobe signal. At the high speeds at which gDDR6 memory devices and DDR5 memory devices are capable of operating, a data processor (GPU or CPU) performs "data eye training" in which the data processor delays the DQ signal relative to the corresponding clock signal so that the clock signal arrives at the data processor aligned with the center of the data eye of the DQS signal. However, as described above, integrated circuit 210 and integrated circuit 230 receive power from separate PDNs such that V in the first power domain PHY-A The noise on the power supply is independent of the V PHY-B Noise on the power supply. These changes close the data eye, that is, they make the height and / or width of the data eye smaller.

[0026] However, according to various embodiments disclosed herein, the data transmission system 200 includes a reference voltage generation circuit 260, which generates a reference voltage by mixing a first circuit based on a first power supply voltage (eg, V PHY-A ) generated by the voltage divider 220 (eg, V REFA ) and a second circuit based on a second power supply voltage (eg, V PHY-B ) generated by the second signal (eg, V generated by the driver 239) REFB ) to form a reference voltage used in the receiver (e.g., V used in receivers 213 and 216) REFA ). The reference voltage generating circuit 260 generates a voltage carrying V PHY-A and V PHY-B The noise characteristics of both reference voltages V REFA Then, in receivers 213 and 216, V REFATo receive the DQ signal and DQS signal in integrated circuit 210, respectively. Mixing the power supply noise from the opposite ends of the communication link to form the reference voltage for receiving data on a given side of the communication link has the significant property of widening the DQ data eye to make data reception more robust. In other embodiments, V SS Noise to form V REF In this case, driver 239 will receive at its input a voltage representing V SSB The voltage is logically "0", and the voltage divider 220 can form V by reversing the order of the resistor 221 and the circuit element 222. REFA and V REFB In addition, driver 239 will have a pull-down drive strength that matches the resistance of resistor 221 .

[0027] In addition, as will be further described below, significantly more robust data reception can achieve higher overall data transfer rates by allowing a multi-level data transmission and reception system to be implemented instead of a conventional two-level system. For example, instead of the conventional binary data transmission used in existing versions of the DDR and Graphics DDR standards, a four-level pulse amplitude modulation (PAM4) system can be created that allows two binary bits to be transmitted and received for each clock transition instead of just two. Thus, for a given clock speed, the data transmission bandwidth can be doubled.

[0028] Figure 3 It helps to understand Figure 2 300 for the operation of the data transmission system 200 of the integrated circuit 210. The timing diagram 300 includes data eye diagrams 310, 320, 330, and 340. Each data eye diagram has a corresponding horizontal axis representing time in picoseconds (ps) and a corresponding vertical axis representing amplitude in volts. The data eye diagrams 310, 320, 330, and 340 show the waveform clouds generated by the superposition of both low-to-high transitions and high-to-low transitions with a group of data signals (e.g., bytes) for which the memory controller sets a capture delay. The left column of the figure (i.e., data eye diagrams 311 and 331) shows the data signals received at the integrated circuit 210, where the data eye diagram 311 shows the generation of V REF , and a data eye diagram 331 illustrates the generation of V according to various embodiments described herein. REF Similarly, the right column of the figure (ie, data eye diagrams 321 and 341) shows the data signal received at the integrated circuit 230, where the data eye diagram 321 shows the generation of V REF , and a data eye diagram 341 illustrates the generation of V according to various embodiments described herein. REFIt can be clearly seen that the data eye diagram formed using the hybrid technique described herein presents a clearer data eye with a larger eye height and a larger eye width.

[0029] Figure 3 These experimental observations shown in the graph of demonstrate significant improvements in data transmission fidelity using the hybrid techniques disclosed herein compared to existing data transmission systems.

[0030] Figure 4 Shows when Figure 2 Graph 400 of an example of the height and width of the data eye measured at various data noise frequencies by the data transmission system 200. Figure 4 4, the horizontal axis represents frequency in Hz, the left vertical axis represents eye height in millivolts (mV), and the right vertical axis represents eye width in ps. Shown in graph 400 are four waveforms of interest, including: waveform 410, which shows the use of V REF The eye height of the data eye of the hybrid technology; waveform 420, shows the use of conventional V REF Waveform 430 shows the eye height of the data eye generated by the disclosed V REF The eye width of the data eye of the hybrid technology; waveform 440, shows the use of conventional V REF The eye height of the data eye of the generation technique. As can be seen from waveforms 410 and 420, for a 0.8 volt supply, the eye height is improved by up to about 37 mV through voltage noise frequencies up to about 500 MHz, and then gradually decreases until reaching a crossover point at about 950 MHz. The eye width shows a consistent but less dramatic improvement at all voltage noise frequencies. At the voltage noise frequency of particular interest (i.e., 100 MHz), the eye height is improved by 24 mV and the eye width is improved by 0.8 ps.

[0031] Figure 5 A data transmission system 500 useful in a multi-stage data transmission system according to some embodiments is shown in partial block diagram and partial schematic form. The data transmission system 500 includes an integrated circuit 510, an integrated circuit 530, and a transmission medium 550.

[0032] Integrated circuit 510 includes a four-level pulse amplitude modulation (PAM4) receiver 511, a slice level generator 512, and a voltage divider 520. PAM4 receiver 511 has a signal input terminal connected to the pad of integrated circuit 510, a reference input terminal, and a voltage divider 520 for providing a reference signal. INA [1:0]” decoded voltage signal output terminal, and for receiving V PHY-A The limit level generator 512 has a power supply input terminal for receiving V REFAThe input terminal is used to receive V PHY-A The voltage divider 520 includes a resistor 521 and a circuit element 522. The resistor 521 has a voltage for receiving V PHY-A The first terminal and V REFA and a second terminal connected to the second terminal of the integrated circuit 510. Circuit element 522 has a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. As in voltage divider 220, in some embodiments, circuit element 522 is implemented by a tunable current source having a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. In other embodiments, circuit element 522 is implemented by a tunable resistor having a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. In other embodiments, circuit element 522 is implemented by a combination of a tunable current source and a tunable resistor.

[0033] Integrated circuit 530 includes a PAM4 transmitter 531 and a driver 535. PAM4 transmitter 531 has a PAM4 input for receiving a PAM4 signal. OUTB [1:0]”, the input terminal of the two-bit output signal, used to receive V PHY-B The power input terminal is used to receive V REFB The driver 535 has an input terminal for receiving a logic high voltage level marked as "1", an output terminal connected to the first terminal of the integrated circuit 230, and an output terminal for receiving V PHY-B The power input terminal.

[0034] Transmission medium 550 includes conductor 551 and conductor 552. Conductor 551 has a first end connected to a first terminal of integrated circuit 530 and a second end connected to a first terminal of integrated circuit 510. Conductor 552 has a first end connected to a second terminal of integrated circuit 530 and a second end connected to a second terminal of integrated circuit 510. Driver 535 and voltage divider 520 are connected together through conductor 552 to form reference voltage generation circuit 560.

[0035] The data transmission system 500 is used with Figure 2 The data transmission system 200 operates in much the same manner as described above, but implements PAM4 encoding and decoding. PAM4 effectively doubles the data transmission throughput for a given clock frequency by encoding two bits of data into one of four voltage levels transmitted on each clock edge. According to PAM4, the voltage levels are encoded into four levels as shown in Table 1 below:

[0036] Table I

[0037] symbol D[1:0] Voltage level V 0

[00] <![CDATA[V INA <1 / 4V PHY-A ]]> 1

[01] <![CDATA[1 / 4V PHY-A <V INA <1 / 2V PHY-A ]]> 2

[10] <![CDATA[1 / 2V PHY-A <V INA <3 / 4V PHY-A ]]> 3

[11] <![CDATA[V INA >3 / 4V PHY-A ]]>

[0038] In order to decode the voltage into the appropriate symbol and its corresponding data, the slice level generator 512 generates a value equal to 1 / 4V PHY-A , 1 / 2V PHY-A and 3 / 4V PHY-A The clipping level generator 512 can generate three clipping levels based on V REFA The power supply noise mixed from the integrated circuit 510 and the integrated circuit 530 is injected in various ways. In one example, the integrated circuit 510 and the integrated circuit 530 are respectively V PHY-A and V PHY-B Half of the voltage generated V REFA and V REFB In this case, the limit level generator 512 is at V PHY-A A series of four equal value resistors are included between power and ground, where the slice level generator generates a 3 / 4V at the connection point between the top resistor and the top-middle resistor. PHY-A value, and 1 / 4V is generated at the connection point between the bottom-middle resistor and the bottom resistor PHY-A In this example, the buffer has a REFA The input terminal and the output terminal for driving the connection point between the top-middle resistor and the bottom-middle resistor. REFA The noise from the PDNs of both integrated circuit 510 and integrated circuit 530 is mixed, so the slice level generator 512 outputs a slice level with these two noise components. By using a reference voltage with power supply noise mixed from both ends of the communication link, the data eye diagram will also show an improved eye opening, as described above for binary signal transmission.

[0039] In some embodiments, the resistors in the resistor string can be made programmable and can be trained to set the slice levels at the intersections of the levels in the data eye. For example, sometimes the data eye exhibits an asymmetry that tilts the center of the data eye up or down. A calibration process can be used to make these adjustments for even more robust data transmission and reception.

[0040] Thus, the techniques disclosed herein can be used to improve data transmission bandwidth by transmitting non-binary symbols (i.e., symbols with more than two states per clock edge). It is believed that the noise mitigation techniques can allow PAM4 reception in systems that would otherwise not be robust enough to decode the four voltage levels used in PAM4 symbols at existing clock speeds.

[0041] One or more integrated circuits containing the reference voltage generation circuit described herein or any portion thereof may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or register transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to generate a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as required) or a graphic data system (GDS) II data.

[0042] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, although the present application describes in detail a binary (i.e., 2-level) data transmission and reception system, in some embodiments, noise mitigation can be used in a data transmission system that transmits more than one bit per clock edge, such as PAM4. In addition, reference voltage generation circuits of different blocks can be implemented in different parts of an integrated circuit. The reference voltage generation circuit can also have a voltage divider and / or a driver at both ends of the transmission medium or only at one end. The disclosed technology is applicable to various integrated circuits using high-speed data transmission. In a specific example, one integrated circuit can be a data processor, a system on a chip (SOC), or a graphics processing unit (GPU), while another integrated circuit is a DDR or gDDR SDRAM, but the technology described herein can be used with many other types of integrated circuits. The transmission medium can also vary between embodiments and can include printed circuit board traces, bonding wires, through silicon vias (TSVs), etc.

[0043] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A data transmission system, comprising: The first circuit includes a transmitter, the transmitter is connected to the ground by powered by a first power supply voltage and having an output terminal and an input terminal for receiving a data output signal; a second circuit comprising a receiver powered by a second supply voltage relative to ground and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal; and a reference voltage generating circuit that forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage, The second circuit comprises: a slice level generator having an input terminal for receiving the reference voltage and an output terminal for providing a plurality of slice levels; as well as a receiver having a first input coupled to the output of the transmitter, a second input for receiving the plurality of slice levels, and an output for providing a multi-bit digital signal as the data input signal, wherein the receiver decodes the multi-bit digital signal using the plurality of slice levels.

2. A data transmission system, comprising: The first circuit includes a transmitter, the transmitter is connected to the ground by powered by a first power supply voltage and having an output terminal and an input terminal for receiving a data output signal; a second circuit comprising a receiver powered by a second supply voltage relative to ground and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal; and a reference voltage generating circuit that forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage, wherein the reference voltage generating circuit The device comprises: a driver having an input terminal for receiving a predetermined signal and an output terminal for providing the first signal referenced to the first power supply voltage; and a voltage divider powered by a second power supply voltage terminal and coupled to the output terminal of the driver and to the second input terminal of the receiver for providing the reference voltage thereto, wherein the voltage divider comprises: a resistor having a first terminal for receiving the second supply voltage and a second terminal coupled to the output of the driver and forming the reference voltage; and A second circuit element has a first terminal coupled to the second terminal of the resistor and a second terminal connected to ground.

3. The data transmission system according to claim 2, wherein: The transmitter and the driver are on a first integrated circuit; and The receiver and the voltage divider are on a second integrated circuit.

4. The data transmission system according to claim 2, wherein the second circuit element comprises: A variable current source has a first terminal coupled to the second terminal of the resistor and a second terminal connected to ground.

5. The data transmission system according to claim 2, wherein the second circuit element comprises: A variable resistor has a first terminal coupled to the second terminal of the resistor and a second terminal connected to ground.

6. A data transmission system, comprising: a transmitter powered by a first supply voltage and having an output terminal and an input terminal for receiving a data output signal; a receiver powered by a second power supply voltage and having a first input terminal coupled to the output terminal of the transmitter, a second input terminal for receiving a reference voltage, and an output terminal for providing a data input signal; and A reference voltage generating circuit, the reference voltage generating circuit comprising: a driver powered by the first power supply voltage and having an output terminal and an input terminal for receiving a predetermined signal; and a voltage divider powered by the second supply voltage and coupled to the output terminal of the driver and to the second input terminal of the receiver for providing the reference voltage thereto, in: the receiver further having an input for receiving at least one additional voltage level, wherein the output of the receiver is a multi-bit digital signal, and the receiving uses the at least one additional voltage level to decode the multi-bit digital signal; and The data transmission system further comprises a slice level generator having an input for receiving the reference voltage and an output coupled to the second input of the receiver for providing the at least one additional voltage level as a plurality of slice levels.

7. The data transmission system according to claim 6, wherein: The transmitter is on a first integrated circuit; The receiver is on a second integrated circuit; and The output of the transmitter is coupled to the first input of the receiver through a conductor.

8. The data transmission system according to claim 6, further comprising: a data strobe driver, the data strobe driver being powered by the first power supply voltage and having an output terminal for providing a data strobe signal; a data strobe receiver powered by the second power supply voltage and having an output terminal, a first input terminal coupled to the output terminal of the data strobe driver, and a second input terminal for receiving the reference voltage; and A latch having a data input coupled to the output of the receiver, a clock input coupled to the output of the data strobe receiver, and an output for providing a latched data signal.

9. A data transmission method, the method comprising: transmitting a data signal from a transmitter of a first integrated circuit operating at a first supply voltage, the first integrated circuit having a first voltage reference terminal for use in a receiver of the first integrated circuit; receiving the data signal in a receiver of a second integrated circuit operating at a second supply voltage, the second integrated circuit having a second voltage reference terminal, the receiving comprising comparing the data signal to a voltage on the second voltage reference terminal to provide a received data signal; as well as generating a shared reference voltage at the first voltage reference terminal and the second voltage reference terminal based on noise in both the first power supply voltage and the second power supply voltage, wherein the receiving comprises: providing a plurality of slice levels in response to the shared reference voltage; and A multi-bit digital signal is decoded using the plurality of slice levels and provided as the data signal.

10. The method of claim 9, wherein said generating said shared reference voltage comprises: coupling the first voltage reference terminal to the second voltage reference terminal; driving the first voltage reference terminal and the second voltage reference terminal from one of the first integrated circuit and the second integrated circuit using a driver circuit in response to a predetermined logic level; as well as The voltage on the second voltage reference terminal is divided using a reference circuit, and the shared reference voltage is formed on the other of the first integrated circuit and the second integrated circuit in response to the divided voltage.

11. The method according to claim 10, wherein the partial pressure comprises: The voltage on the second voltage reference terminal is divided using a resistor and a second circuit element, wherein the resistor has a first terminal for receiving the second power supply voltage and a second terminal coupled to the second voltage reference terminal, and the second circuit element has a first terminal coupled to the second voltage reference terminal and a second terminal connected to ground.

12. The method according to claim 9, wherein: The transmission further comprises: transmitting a strobe signal from the first integrated circuit to the second integrated circuit using the first power supply voltage; and wherein the receiving further comprises: receiving the strobe signal in the second integrated circuit using the second power supply voltage and the shared reference voltage to form a received strobe signal; and The received data signal is latched using the received strobe signal.

13. The method according to claim 9, further comprising: transmitting a second data signal from a transmitter of the second integrated circuit; as well as The second data signal is received in a receiver of the first integrated circuit, the receiving comprising comparing the second data signal to a voltage on the first voltage reference terminal to provide a received second data signal.

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