Matrix operation circuits, processors, integrated circuit systems, electronic components and equipment

By designing M×N calculation units and compression buffer units in the matrix calculation circuit, the compression and matrix multiplication and addition operations of sparse matrix are realized, and the efficiency problem of sparse matrix in the high-speed multiplication and addition circuit in the prior art is solved, which improves the calculation rate and reduces power consumption.

CN117851744BActive Publication Date: 2025-03-18BEIJING XIANGDIXIAN COMPUTING TECH CO LTD
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Patent Information

Application Number
CN202410257138.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-03-07
Publication Date
2025-03-18
Estimated Expiration
2044-03-07

AI Technical Summary

Technical Problem

The prior art is difficult to effectively compress sparse matrixes in two-dimensional and three-dimensional high-speed multiplication and addition circuits, especially in the matrix multiplication or matrix multiplication and addition operation, and it is impossible to effectively utilize sparseness to improve the calculation rate and reduce power consumption.

Method used

A matrix calculation circuit is designed, including M×N calculation units and M×N compression buffer units. Sparse compression is achieved by discarding 0-value data pairs, and the compressed data is output to the calculation unit within one clock cycle, supporting the point multiplication and multiplication operations of the matrix.

Benefits of technology

It realizes sparse compression during the two-dimensional and three-dimensional hardware point multiplication operation, improves the utilization rate of matrix multiplication or matrix multiplication calculation unit, improves the calculation rate and effectively reduces power consumption.

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Abstract

The present disclosure provides a matrix operation circuit, processor, integrated circuit system, electronic component and equipment, which are intended to support two-dimensional and three-dimensional hardware point multiplication (or multiplication and addition) operations while achieving sparse compression. Among them, the matrix operation circuit implements the point multiplication operation (or multiplication and addition operation) of the A matrix (M×K1 matrix) and the B matrix (K1×N matrix) through M×N operation units, and realizes sparse matrix compression through M×N compression cache units. It has strong versatility and can be applied to chips such as GPU, NPU and ASIC. The circuit implementation is simple, and does not require complex data compression and decompression, nor does it require input and output indexes and complex data movement. In addition, without pre-training and data processing, the A matrix and the B matrix involved in the operation can be simultaneously subjected to hardware-level matrix sparse compression.
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