Display panel, driving method thereof, and display device

Abstract

This invention discloses a display panel, its driving method, and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a light-emitting control module, a driving module, and a compensation module. The light-emitting control module includes a first light-emitting control module, which selectively provides a first power signal to the driving module. The driving module provides a driving current to the light-emitting element and includes a driving transistor. The compensation module compensates for the threshold voltage of the driving transistor. The operation of the pixel circuit includes a light-emitting stage and a biasing stage. In the biasing stage, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The driving transistor is disconnected from the light-emitting element, and the first power signal is written from the source of the driving transistor to its drain to adjust the bias state of the driving transistor. This invention reduces the threshold voltage drift of the driving transistor.

Description

[0001] This application is a divisional application of application number 202011105592.5, filed on October 15, 2020, entitled "Display Panel and Driving Method Thereof and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel, its driving method, and a display device. Background Technology

[0003] In a display panel, the pixel circuit provides the driving current required for the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable component in most self-emissive display panels.

[0004] However, in existing display panels, as the usage time increases, the internal characteristics of the driving transistors in the pixel circuits change slowly, causing the threshold voltage of the driving transistors to drift, thereby affecting the overall characteristics of the driving transistors and consequently affecting display uniformity. Summary of the Invention

[0005] This invention provides a display panel, a driving method thereof, and a display device to improve the threshold voltage drift problem of existing driving transistors.

[0006] This invention provides a display panel, comprising:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a light emission control module, a driving module, and a compensation module;

[0009] The light emission control module includes a first light emission control module, which is used to selectively provide a first power signal to the driving module;

[0010] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0011] The compensation module is used to compensate the threshold voltage of the driving transistor;

[0012] The operation of the pixel circuit includes a light-emitting stage and a biasing stage, wherein...

[0013] During the light-emitting stage, the first light-emitting control module is turned on, and the driving transistor and the light-emitting element are connected.

[0014] During the biasing phase, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The driving transistor is disconnected from the light-emitting element, and the first power signal is written to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0015] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel.

[0016] The display panel includes pixel circuitry and light-emitting elements;

[0017] The pixel circuit includes a light emission control module, a driving module, and a compensation module;

[0018] The light emission control module includes a first light emission control module, which is used to selectively provide a first power signal to the driving module;

[0019] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0020] The compensation module is used to compensate the threshold voltage of the driving transistor;

[0021] The method for driving at least one frame of the display panel includes:

[0022] The luminescence phase and the bias phase;

[0023] During the light-emitting stage, the first light-emitting control module is turned on, and the driving transistor and the light-emitting element are connected.

[0024] During the biasing phase, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The driving transistor is disconnected from the light-emitting element, and the first power signal is written to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0025] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above.

[0026] In this embodiment of the invention, the operation of the pixel circuit includes a biasing stage. During the biasing stage, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. A first power signal is written to the drain of the driving transistor through the turned-on first light-emitting control module and driving module to adjust the drain potential of the driving transistor, thereby improving the potential difference between the gate potential and the drain potential of the driving transistor. It is known that a pixel circuit includes at least one unbiased stage. When a driving current is generated in the driving transistor, there may be a situation where the gate potential of the driving transistor is greater than the drain potential, causing the IV curve of the driving transistor to shift and the threshold voltage of the driving transistor to drift. During the biasing stage, by adjusting the gate potential and drain potential of the driving transistor, the shift phenomenon of the IV curve of the driving transistor in the unbiased stage can be balanced, the threshold voltage drift phenomenon of the driving transistor can be reduced, and the display uniformity of the display panel can be ensured. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0028] Figure 1 This is a schematic diagram of the pixel circuit of the first type of display panel provided in the embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor;

[0030] Figure 3 This is a schematic diagram of the pixel circuit of the second type of display panel provided in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the pixel circuit of the third type of display panel provided in the embodiments of the present invention;

[0032] Figure 5 This is a schematic diagram of the pixel circuit of the fourth type of display panel provided in the embodiments of the present invention;

[0033] Figure 6 This is a schematic diagram of the pixel circuit of the fifth type of display panel provided in the embodiments of the present invention;

[0034] Figure 7 This is a schematic diagram of the pixel circuit of the sixth type of display panel provided in the embodiments of the present invention;

[0035] Figure 8 This is a schematic diagram of the first operating timing of a pixel circuit;

[0036] Figure 9 This is a schematic diagram of the second operating timing of the pixel circuit;

[0037] Figure 10 This is a schematic diagram of the third operating timing of the pixel circuit;

[0038] Figure 11 This is a schematic diagram of the fourth operating timing of the pixel circuit;

[0039] Figure 12 This is a schematic diagram of the fifth operating timing sequence of the pixel circuit;

[0040] Figure 13 This is a schematic diagram of the sixth operating timing sequence of the pixel circuit;

[0041] Figure 14 This is a schematic diagram of the seventh operating timing sequence of the pixel circuit;

[0042] Figure 15 This is a schematic diagram of the eighth operating timing of the pixel circuit;

[0043] Figure 16 This is a schematic diagram of the ninth operating timing sequence of the pixel circuit;

[0044] Figure 17 This is a schematic diagram of the tenth operating timing sequence of the pixel circuit;

[0045] Figure 18 This is a schematic diagram of the eleventh operating timing sequence of the pixel circuit;

[0046] Figure 19 This is a schematic diagram of the twelfth operating timing sequence of the pixel circuit;

[0047] Figure 20 This is a schematic diagram of the thirteenth operating timing sequence of the pixel circuit;

[0048] Figure 21 This is a schematic diagram of the fourteenth operating timing sequence of the pixel circuit;

[0049] Figure 22 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention;

[0050] Figure 23 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0052] refer to Figure 1 , Figure 1 This is a schematic diagram of the pixel circuit of a first type of display panel provided in this embodiment of the invention. The display panel provided in this embodiment includes: a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a light-emitting control module, a driving module 12, and a compensation module 13; the light-emitting control module includes a first light-emitting control module 11, which is used to selectively provide a first power signal PVDD to the driving module 12; the driving module 12 is used to provide a driving current to the light-emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is used to compensate the threshold voltage of the driving transistor T0; the operation process of the pixel circuit 10 includes a light-emitting stage and a bias stage, wherein, in the light-emitting stage, the first light-emitting control module 11 is turned on, and the driving transistor T0 and the light-emitting element 20 are connected; in the bias stage, the first light-emitting control module 11 and the driving module 12 are turned on, and the compensation module 13 is turned off, the driving transistor T0 and the light-emitting element 20 are disconnected, and the first power signal PVDD is written from the source of the driving transistor T0 to the drain of the driving transistor T0 to adjust the bias state of the driving transistor T0.

[0053] It is important to note that Figure 1 The above embodiments only schematically illustrate the key structures and do not include all the structures in which the circuit operates. The complete circuit structure will be gradually shown in the following description of this embodiment.

[0054] Additionally, it should be noted that the terms "first type of display panel" and "first type of working sequence" used in this article are only used to distinguish different schematic diagrams and should not be interpreted as implying a certain ordering relationship between the schematic diagrams.

[0055] In this embodiment, the pixel circuit 10 includes a first light-emitting control module 11. The input terminal of the first light-emitting control module 11 receives a first power signal PVDD, the control terminal of the first light-emitting control module 11 receives a first light-emitting control signal EM1, and the output terminal of the first light-emitting control module 11 is electrically connected to the input terminal of the driving module 12. The first light-emitting control signal EM1 received by the pixel circuit 10 is a pulse signal. A valid pulse of the first light-emitting control signal EM1 controls the transmission path of the input and output terminals of the first light-emitting control module 11 to be turned on, so as to provide the first power signal PVDD to the driving module 12; an invalid pulse of the first light-emitting control signal EM1 controls the transmission path of the input and output terminals of the first light-emitting control module 11 to be turned off. Therefore, under the control of the first light-emitting control signal EM1, the first light-emitting control module 11 selectively provides the first power signal PVDD to the driving module 12.

[0056] In this embodiment, the first light-emitting control module 11 is connected between the first power signal terminal and the source of the driving transistor T0, and the first power signal terminal is used to provide the first power signal PVDD; the compensation module 13 is connected between the gate of the driving transistor T0 and the drain of the driving transistor T0.

[0057] The pixel circuit 10 includes a driving module 12, the output terminal of which is electrically connected to the light-emitting element 20. The driving module 12 includes a driving transistor T0. When the driving transistor T0 is turned on, the driving module 12 provides a driving current to the light-emitting element 20. The source of the driving transistor T0 is electrically connected to the input terminal of the driving module 12, and the drain of the driving transistor T0 is electrically connected to the output terminal of the driving module 12. In other embodiments, the drain of the driving transistor may be electrically connected to the input terminal of the driving module, and the source of the driving transistor may be electrically connected to the output terminal of the driving module. It is understood that the source and drain of the transistor are not constant but change with the driving state of the transistor.

[0058] The pixel circuit 10 includes a compensation module 13, which is used to compensate the threshold voltage of the driving transistor T0. The first terminal of the compensation module 13 is electrically connected to the output terminal of the driving module 12, the control terminal of the compensation module 13 receives a scan signal S3, and the second terminal of the compensation module 13 is electrically connected to the control terminal of the driving module 12. The scan signal S3 received by the pixel circuit 10 is a pulse signal. A valid pulse of the scan signal S3 controls the transmission path of the first and second terminals of the compensation module 13 to conduct, thereby adjusting the voltage between the control terminal and the output terminal of the driving module 12; an invalid pulse of the scan signal S3 controls the transmission path of the first and second terminals of the compensation module 13 to turn off. Therefore, the scan signal S3 controls the compensation module 13 to turn on, which can be used to compensate the threshold voltage of the driving transistor T0.

[0059] The operation of the pixel circuit 10 includes a light-emitting stage. During this stage, the first light-emitting control signal EM1 outputs a valid pulse signal, turning on the first light-emitting control module 11. This also connects the driving transistor T0 to the light-emitting element 20, allowing driving current to flow into the element and cause it to emit light. In the non-biased stages, such as the light-emitting stage, the gate potential of the driving transistor may be greater than its drain potential. Prolonged use of this setting can lead to ion polarization within the driving transistor, resulting in a built-in electric field and a continuous increase in the threshold voltage of the driving transistor. (Refer to...) Figure 2 , Figure 2 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor, as shown below. Figure 2 As shown, the Id-Vg curve shifts, indicating a shift in the threshold voltage, which affects the stability of the driving transistor and consequently the uniformity of the display.

[0060] refer to Figure 3 , Figure 3 This is a schematic diagram of the pixel circuit of the second type of display panel provided in this embodiment of the invention. In this embodiment, a bias stage is added to the operation of the pixel circuit 10. During the bias stage, the first light-emitting control module 11 and the driving module 12 are turned on, and the compensation module 13 is turned off. Then, the first power signal PVDD is written to the drain of the driving transistor T0 through the source of the driving transistor T0 via the first light-emitting control module 11, so as to increase the drain potential of the driving transistor T0, adjust the potential difference between the gate potential and the drain potential of the driving transistor T0, realize the voltage bias between the gate and the drain of the driving transistor T0, thereby reducing the degree of ion polarization inside the driving transistor T0, and further reducing the threshold voltage drift of the driving transistor T0, thus improving the display uniformity.

[0061] In this embodiment of the invention, the operation of the pixel circuit includes a light-emitting stage and a biasing stage, such as... Figure 3 As shown, during the biasing phase, the first light-emitting control module and the driving module are turned on, while the compensation module is turned off. The driving transistor and the light-emitting element are disconnected. Therefore, the first power signal is written to the source of the driving transistor through the turned-on first light-emitting control module and to the drain of the driving transistor, adjusting the drain potential. This reduces the threshold voltage of the driving transistor by biasing the gate and drain voltages. It is known that during the biasing phase, such as the light-emitting phase of the pixel circuit, the gate potential of the driving transistor may be greater than the drain potential, causing the threshold voltage of the driving transistor to drift. Therefore, biasing the voltage between the gate and drain of the driving transistor during the biasing phase can balance the threshold voltage drift during the light-emitting phase, improve the Id-Vg curve offset, and ensure the display uniformity of the display panel.

[0062] The optional light-emitting control module also includes a second light-emitting control module 14, which is used to selectively allow drive current to flow into the light-emitting element 20; during the biasing phase, the second light-emitting control module 14 is turned off; during the light-emitting phase, the second light-emitting control module 14 is turned on.

[0063] In this embodiment, the input terminal of the second light-emitting control module 14 is connected to the output terminal of the driving module 12, and the output terminal of the second light-emitting control module 14 is connected to the light-emitting element 20. The control terminal of the second light-emitting control module 14 receives the second light-emitting control signal EM2. The second light-emitting control signal EM2 is a pulse signal. A valid pulse output by the second light-emitting control signal EM2 controls the transmission path of the input and output terminals of the second light-emitting control module 14 to be turned on, so as to allow the driving current to flow into the light-emitting element 20; an invalid pulse output by the second light-emitting control signal EM2 controls the transmission path of the input and output terminals of the second light-emitting control module 14 to be turned off.

[0064] During the biasing phase, the first power signal PVDD needs to be written to the drain of the driving transistor T0 to bias the gate and drain voltages of the driving transistor. Therefore, during the biasing phase, the second light-emitting control module 14 is turned off to prevent the first power signal PVDD from driving the light-emitting element 20 via the second light-emitting control module 14 and affecting the display effect of the display panel. During the light-emitting phase, when the light-emitting element 20 needs to emit light, the second light-emitting control module 14 is turned on, allowing the driving current to flow into the light-emitting element 20 to make it emit light, ensuring the normal light emission of the display panel.

[0065] The optional first light-emitting control module 11 includes a first transistor T1, the source of which receives a first power supply signal PVDD, and the drain of which is connected to the source of a driving transistor T0. The compensation module 13 includes a second transistor T2, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the gate of the driving transistor T0. The second light-emitting control module 14 includes a third transistor T3, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the light-emitting element 20. The gate of the first transistor T1 receives a first light-emitting control signal EM1, and the gate of the third transistor T3 receives a second light-emitting control signal EM2. The gate of the second transistor T2 receives a scan signal S3.

[0066] Optionally, the control terminal of the first light-emitting control module 11 is connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal EM1; the control terminal of the second light-emitting control module 14 is connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal EM2. Here, EM1 represents the first light-emitting control signal line and the first light-emitting control signal transmitted therein, and EM2 represents the second light-emitting control signal line and the second light-emitting control signal transmitted therein.

[0067] Generally, the width of the first light-emitting control signal line EM1 can be equal to the width of the second light-emitting control signal line EM2. In some embodiments, the width of the first light-emitting control signal line EM1 can be greater than the width of the second light-emitting control signal line EM2. The first light-emitting control signal line EM1 outputs valid pulses in both the biasing and light-emitting phases, turning on the first transistor T1. The second light-emitting control signal line EM2 outputs valid pulses in the light-emitting phase. Therefore, the signal transmission time of the first light-emitting control signal line EM1 is longer than that of the second light-emitting control signal line EM2. Thus, by increasing the width of the first light-emitting control signal line, the transmission impedance of the first light-emitting control signal in the first light-emitting control signal line can be reduced, the transmission loss of the first light-emitting control signal line EM1 can be reduced, and the long-term accumulation of loss in the first light-emitting control signal line can be avoided from affecting the biasing or light emission.

[0068] Optionally, in this embodiment, the pixel circuit 10 further includes a reset module 17. The reset module 17 is used to provide a reset signal Vref to the gate of the driving transistor T0 to reset the gate of the driving transistor T0. The control terminal of the reset module 17 is used to receive a first scan signal S1. The first scan signal S1 provides a valid pulse to the pixel circuit 10, thereby turning on the reset module 17.

[0069] Optionally, the reset module 17 includes a seventh transistor T7. The source of the seventh transistor T7 receives a reset signal Vref, the drain of the seventh transistor T7 is electrically connected to the gate or drain of the driving transistor T0, and the gate of the seventh transistor T7 receives a scan signal S1.

[0070] Optional, such as Figure 3 As shown, the reset module 17 is connected between the reset signal terminal and the gate of the driving transistor T0. When the reset module 17 is turned on, the reset signal Vref is applied to the gate of the driving transistor T0 through the reset module 17.

[0071] Additionally, refer to Figure 4 , Figure 4This is a schematic diagram of the pixel circuit of the third type of display panel provided in the embodiment of the present invention. The reset module 17 is connected between the reset signal terminal and the drain of the driving transistor T0. When the reset module 17 and the compensation module 13 are turned on at the same time, the reset signal Vref is applied to the gate of the driving transistor T0 through the reset module 17 and the compensation module 13.

[0072] refer to Figure 5 , Figure 5 This is a schematic diagram of the pixel circuit of the fourth type of display panel provided in this embodiment of the invention. The optional first light-emitting control module 11 includes a first sub-light-emitting control module 11a and a second sub-light-emitting control module 11b. The first sub-light-emitting control module 11a and the second sub-light-emitting control module 11b are connected in parallel between the first power signal terminal PVDD and the driving module 12. During the biasing phase, the second sub-light-emitting control module 11b is turned off, and the first sub-light-emitting control module 11a is turned on. During the biasing phase, the first power signal PVDD output from the first power signal terminal is written into the drain of the driving transistor T0 through the turned-on first sub-light-emitting control module 11a and the driving module 12, thereby biasing the driving transistor T0.

[0073] The control terminals of the optional second light-emitting control module 14 and the second sub-light-emitting control module 11b are both connected to the third light-emitting control signal line EM3 to receive the third light-emitting control signal. During the biasing phase, the third light-emitting control signal EM3 outputs an invalid pulse signal, causing both the second light-emitting control module 14 and the second sub-light-emitting control module 11b to turn off, preventing drive current from flowing into the light-emitting element 20. Then, the first power supply signal PVDD is written to the drain of the drive transistor T0 through the activated first sub-light-emitting control module 11a and the drive module 12. During the light-emitting phase, the third light-emitting control signal EM3 outputs a valid pulse signal, causing both the second light-emitting control module 14 and the second sub-light-emitting module 11b to turn on. Then, the first power supply signal PVDD sequentially flows through the activated second sub-light-emitting control module 11b, the drive module 12, and the second light-emitting control module 14, generating a drive current that flows into the light-emitting element 20.

[0074] The control terminal of the optional first sub-light-emitting control module 11a is connected to the bias control signal line ST to receive the bias control signal. The bias control signal outputs a valid pulse during the bias phase, which turns on the first sub-light-emitting control module 11a, allowing the first power supply signal PVDD to be written to the drain of the driving transistor T0.

[0075] refer to Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the pixel circuit of the fifth type of display panel provided in the embodiments of the present invention. Figure 7This is a schematic diagram of the pixel circuit of the sixth type of display panel provided in this embodiment of the invention. The optional display panel further includes a reset module 17, which is used to selectively provide a reset signal to the gate of the driving transistor T0. The control terminal of the reset module 17 is connected to the first scan signal line S1 and is used to receive the first scan signal S1. In some optional embodiments, such as... Figure 6 As shown, the bias control signal ST and the first scan signal S1 are the same signal.

[0076] like Figure 6 and Figure 7 As shown, the input terminal of the reset module 17 receives the reset signal Vref, the control terminal of the reset module 17 receives the first scan signal S1, and the output terminal of the reset module 17 is electrically connected to the gate or drain of the driving transistor T0. The first scan signal S1 provides a valid pulse to the pixel circuit 10, causing the reset module 17 to turn on, and then... Figure 6 The reset signal Vref shown is directly written to the gate of the driving transistor T0 for reset. Alternatively, the first scan signal S1 provides a valid pulse to the pixel circuit 10, and the scan signal S3 provides a valid pulse to the compensation module 13, thereby turning on the reset module 17 and the compensation module 13. Figure 7 The reset signal Vref shown is written to the gate of the driving transistor T0 through the compensation module 13 to reset it. The reset signal Vref is usually a negative voltage signal, such as -7V. During the reset phase, the gate of the driving transistor T0 maintains a negative voltage, which facilitates subsequent bias adjustment and data writing.

[0077] The optional pixel circuit 10 also includes an initialization module 15, which selectively provides an initialization signal Vini to the light-emitting element 20; wherein, the initialization module 15 remains on for at least a portion of the bias phase. The control terminal of the initialization module 15 is connected to the second scan signal line S2 to receive the second scan signal; wherein, as... Figure 7 As shown, the bias control signal ST and the second scan signal S2 can be the same signal. The input terminal of the initialization module 15 receives the initialization signal Vini, the output terminal of the initialization module 15 is electrically connected to the light-emitting element 20, and the control terminal of the initialization module 15 receives the scan signal S2. During the initialization phase, the scan signal S2 provides a valid pulse to the pixel circuit 10 to enable the initialization module 15, and the initialization signal Vini is written to the light-emitting element 20 of the pixel circuit 10 for initialization. The initialization signal Vini is usually a negative voltage signal, so during the initialization phase, the anode of the light-emitting element 20 maintains a negative initial voltage.

[0078] The optional pixel circuit 10 also includes a data writing module 16, which writes the data signal Vdata to the gate of the driving transistor T0. The input of the data writing module 16 receives the data signal Vdata, its output is connected to the input of the driving module 12, and its control terminal receives the scan signal S4. The scan signal S1 outputs a valid pulse signal during the data writing phase, and the scan signal S3 provides a valid pulse to the compensation module 13, enabling the data signal to be written to the gate of the driving transistor T0 through the activated data writing module 16 and compensation module 13.

[0079] The optional initialization module 15 includes a fourth transistor T4, the source of which is used to receive the initialization signal Vini, the drain of which is connected to the anode of the light-emitting element 20, and the gate of which is used to receive the scan signal S2.

[0080] The optional data writing module 16 includes a fifth transistor T5, the source of which receives a data signal, the drain of which is connected to the source of the driving transistor T0, and the gate of which receives a scan signal S4.

[0081] The optional second sub-light emission control module 11b includes a sixth transistor T6, the source of which receives a first power supply signal PVDD, the drain of which is connected to the source of the driving transistor T0, and the gate of which receives a third light emission control signal EM3.

[0082] The optional reset module 17 includes a seventh transistor T7. The source of the seventh transistor T7 receives a reset signal Vref, the drain of the seventh transistor T7 is electrically connected to the gate or drain of the driving transistor T0, and the gate of the seventh transistor T7 receives a scan signal S1.

[0083] The optional pixel circuit 10 also includes a storage capacitor C1, the first plate of which is connected to the first power signal terminal, and the second plate of which is connected to the gate of the driving transistor T0.

[0084] During the biasing phase, the first transistor T1 and the driving transistor T0 are turned on, the second transistor T2 is turned off, and the first power supply signal PVDD is written to the drain of the driving transistor T0 to bias the drain and gate voltages of the driving transistor T0.

[0085] Optional transistors T0, T1, T3, T4, T5, and T6 are PMOS transistors using polysilicon as the active layer, while T2 and T7 are NMOS transistors using indium gallium zinc oxide as the active layer. It can be understood that the effective pulse of the scan signal for an NMOS transistor is high, while the effective pulse of the scan signal for a PMOS transistor is low. It should be noted that... Figures 1 to 7The pixel circuit shown is merely an example, and the structure of the pixel circuit in this embodiment of the invention is not limited to this. For example, in other embodiments, the pixel circuit may be a 6T1C structure, without an initialization module. It is understood that if the structure of the pixel circuit changes, the driving timing will change according to the structural change of the pixel circuit, provided that the driving principle remains unchanged.

[0086] In this embodiment, optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than that of the PMOS transistor. Since the NMOS transistor mainly functions as a switching transistor in this application, it requires rapid response capability. A transistor with a large width-to-length ratio has a shorter channel region, which is beneficial to improving the transistor's response capability.

[0087] Furthermore, in this application, the four scan signals S1, S2, S3, and S4 can be different signals. Under certain specific conditions, such as when the timing meets certain requirements, at least two of the four signals S1, S2, S3, and S4 can also be the same signal. For example, when T4 and T7 are transistors of the same type, such as both being PMOS or both being NMOS, then S1 and S2 can be the same signal. The specific situation depends on the specific circuit structure and timing, and this embodiment does not impose any particular limitations on this.

[0088] Optionally, in this embodiment, the first power signal received by the first light-emitting control module during the light-emitting stage and the first power signal received by the first light-emitting control module during the biasing stage can be the same or different. If they are the same, only one first power signal is needed to meet the requirements of both the light-emitting and biasing stages, significantly simplifying the panel's operation. In some embodiments, at least one of the first power signals received by the first light-emitting control module during the light-emitting stage and the first power signal received by the first light-emitting control module during the biasing stage is greater than the other. For example, in the light-emitting stage, the first power signal is PVDD1, and in the biasing stage, the first power signal is PVDD2. PVDD1 can be equal to or different from PVDD2. In some embodiments, PVDD2 > PVDD1. Because PVDD2 is greater than PVDD1, PVDD2 is a higher high level, which allows the drain voltage of the driving transistor to be sufficiently raised during the biasing stage, shortening the time required for the biasing stage. In other embodiments, PVDD2 < PVDD1, suitable for situations requiring a larger current intensity and a larger PVDD voltage during the light-emitting stage to ensure the brightness of the light-emitting element. The specific design depends on the specific circumstances.

[0089] In this embodiment, the operation process of the selectable pixel circuit further includes at least one non - bias stage; in the bias stage, the gate voltage of the driving transistor is Vg1, the source voltage is Vs1, and the drain voltage is Vd1; in the non - bias stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd2; where,

[0090] |Vg1 - Vd1| < |Vg2 - Vd2|;

[0091] In such a case, by reducing the potential difference between the gate potential and the drain potential of the driving transistor T0, the phenomenon of threshold voltage shift caused by the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non - bias stage can be alleviated.

[0092] Additionally, in some embodiments of this embodiment,

[0093] (Vg1 - Vs1)×(Vg2 - Vs2) < 0, or,

[0094] (Vg1 - Vd1)×(Vg2 - Vd2) < 0.

[0095] During the operation of the pixel circuit, if the first power supply signal PVDD is written from the source of the driving transistor to the drain of the driving transistor, the gate voltage and the drain voltage of the driving transistor satisfy (Vg1 - Vd1)×(Vg2 - Vd2) < 0. In the non - bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the drain voltage of the driving transistor, that is, Vg2 > Vd2, then Vg2 - Vd2 > 0. In the bias stage, the first power supply signal PVDD is written to the drain of the driving transistor, making the gate voltage of the driving transistor less than the drain voltage of the driving transistor, that is, Vg1 < Vd1, then Vg1 - Vd1 < 0. Then (Vg1 - Vd1)×(Vg2 - Vd2) < 0.

[0096] In other embodiments, during the operation of the selectable pixel circuit, if the first power supply signal PVDD is written from the drain of the driving transistor to the source of the driving transistor, the gate voltage and the source voltage of the driving transistor satisfy (Vg1 - Vs1)×(Vg2 - Vs2) < 0. In the non - bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the source voltage of the driving transistor, that is, Vg2 > Vs2, then Vg2 - Vs2 > 0. In the bias stage, the first power supply signal PVDD is written to the source of the driving transistor, making the gate voltage of the driving transistor less than the source voltage of the driving transistor, that is, Vg1 < Vs1, then Vg1 - Vs1 < 0. Then (Vg1 - Vs1)×(Vg2 - Vs2) < 0.

[0097] Alternatively, optionally, in this embodiment, since the time of non-offset phases such as the light-emitting phase of the display panel is relatively long, and to fully balance the threshold voltage offset of the non-offset phase during the offset phase and avoid spending too much time in the offset phase, it can be set that Vd1 - Vg1 > Vg2 - Vd2 > 0. In this way, Vd1 - Vg1 in the offset phase is large enough, so that the expected offset effect can be achieved in a short time in the offset phase. In other embodiments, if the source and drain of the driving transistor are converted, it can also be set that Vs1 - Vg1 > Vg2 - Vs2 > 0, depending on the specific circuit situation.

[0098] Optionally, in other embodiments of this embodiment, the time length of the offset phase is t1, and the time length of the non-offset phase is t2, where

[0099] (|Vg1 - Vs1| - |Vg2 - Vs2|) × (t1 - t2) < 0, or

[0100] (|Vg1 - Vd1| - |Vg2 - Vd2|) × (t1 - t2) < 0.

[0101] In this embodiment, during the offset phase, the first power supply signal PVDD is written from the source of the driving transistor to the drain of the driving transistor. In some embodiments, the drain voltage of the driving transistor can be made greater than the gate voltage of the driving transistor, that is, Vg1 - Vd1 < 0. During the non-offset phase, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, that is, Vg2 - Vd2 > 0. When driving the driving transistor during the offset phase, if the offset voltage is large, the offset time can be appropriately reduced. If the offset voltage is small, the offset time can be appropriately extended.

[0102] Based on this, if |Vg1 - Vd1| - |Vg2 - Vd2| > 0, it means that the offset voltage is large. At this time, the duration of the offset phase can be appropriately reduced, that is, t1 < t2, so as to reduce the deviation of the threshold voltage between the offset phase and the non-offset phase. If |Vg1 - Vd1| - |Vg2 - Vd2| < 0, it means that the offset voltage is small. At this time, the duration of the offset phase can be appropriately extended, that is, t1 > t2, so as to reduce the deviation of the threshold voltage between the offset phase and the non-offset phase.

[0103] In other embodiments, during the offset phase, the first power supply signal PVDD is written from the drain of the driving transistor to the source of the driving transistor. Then, for the gate and drain of the driving transistor in the offset phase and the non-offset phase, (|Vg1 - Vs1| - |Vg2 - Vs2|) × (t1 - t2) < 0, which can reduce the deviation of the threshold voltage between the offset phase and the non-offset phase.

[0104] Optionally, in this embodiment, the bias phase duration is greater than 5 microseconds, and more specifically, the bias phase duration can be greater than 20 microseconds. The inventors of this application have verified that when the bias phase duration is greater than 5 microseconds, especially greater than 20 microseconds, it can effectively alleviate the threshold voltage shift phenomenon. However, when the bias phase duration is less than 5 microseconds, because the bias phase duration is too short, the bias state of the driving transistor T0 is not sufficiently adjusted, and it cannot effectively alleviate the threshold voltage shift.

[0105] The optional non-biased stage can be a light-emitting stage of the display panel. For example, in a light-emitting stage, the source voltage of the driving transistor T0 is 4.6V, the gate voltage is 3V, and the drain voltage is 1V. The gate voltage of the driving transistor is greater than the drain voltage of the driving transistor. By biasing the driving transistor in the biased stage, the threshold voltage offset of the driving transistor in the light-emitting stage can be compensated.

[0106] Within one frame of the optional display panel, the operation of the pixel circuit includes a pre-lighting stage and a light-emitting stage; wherein, within at least one frame of the display panel, the pre-lighting stage of the pixel circuit includes a biasing stage.

[0107] In this embodiment, the pixel circuit operates within one frame of the display panel, including a pre-processing stage and a light-emitting stage. Within at least one frame, the pre-processing stage of the pixel circuit includes a biasing stage. During the biasing stage, a first power supply signal is written from the source of the driving transistor to the drain of the driving transistor, adjusting the drain potential and biasing the driving transistor. In non-biased stages such as the light-emitting stage, the gate voltage of the driving transistor may be greater than its drain voltage, leading to an increase in the threshold voltage of the driving transistor. Therefore, a biasing stage is added to the pixel circuit within at least one frame. This biasing stage can at least partially balance the increase in the threshold voltage of the driving transistor during the non-biased stage, improving the display uniformity of the display panel.

[0108] refer to Figure 8 , Figure 8 This is a schematic diagram of the first operating timing of a pixel circuit, combined with... Figure 6 In the pixel circuit, the control terminal of the optional reset module 17 is connected to the first scan signal line S1. The bias control signal ST is the same as the first scan signal S1. Here, the transistor T7 in the reset module and the transistor T1 in the first sub-light emission control module are the same type of transistor, such as both being NMOS transistors or PMOS transistors. Based on this, the operation process of the optional pixel circuit includes a reset stage and a bias stage; the reset stage and the bias stage are performed simultaneously.

[0109] During the bias and reset phases, the third light-emitting control signal EM3 outputs an invalid pulse, causing the sixth transistor T6 and the third transistor T3 to turn off; the first scan signal S1 outputs a valid pulse, causing the seventh transistor T7 to turn on, and the reset signal Vref is written to the gate of the driving transistor T0; the third scan signal S3 outputs an invalid pulse, causing the second transistor T2 to turn off; the fourth scan signal S4 outputs an invalid pulse, causing the fifth transistor T5 to turn off. This achieves the reset of the gate of the driving transistor T0. Simultaneously, the first transistor T1 turns on, and the first power supply signal PVDD is written to the drain of the driving transistor T0, achieving the biasing of the gate and drain voltages of the driving transistor T0.

[0110] The reset phase and the bias phase are performed simultaneously. On the one hand, the gate voltage of the driving transistor T0 is adjusted by the reset signal, and on the other hand, the drain voltage of the driving transistor T0 is adjusted by the first power supply signal PVDD. This allows the gate voltage and drain voltage of the driving transistor T0 to be adjusted simultaneously, thereby improving the bias effect.

[0111] refer to Figure 9 , Figure 9 This is a schematic diagram of the second operating timing of the pixel circuit, combined with... Figure 7 The pixel circuit shown may optionally include an initialization module 15, which remains on for at least a portion of the bias phase. The portion of the bias phase is multiplexed as the initialization phase, where a valid pulse is output from the optional second scan signal S2, causing the fourth transistor T4 to turn on. In this case, the initialization module 15 provides an initialization signal Vini to the light-emitting element 20.

[0112] The optional bias control signal ST and the second scan signal S2 are the same signal. The operation of the optional pixel circuit includes an initialization phase and a bias phase; the initialization phase and the bias phase are performed simultaneously. That is, the entire time period of the bias phase is synchronized with the initialization phase.

[0113] Performing the initialization phase simultaneously with the bias phase ensures that the light-emitting element 20 receives the initialization signal. During the bias phase, the data signal is written to the drain of the driving transistor T0. Although T3 is turned off at this time, the transistor may still have a certain leakage current. Therefore, if the light-emitting element 20 does not receive the initialization signal, there is a risk that the light-emitting element 20 may light up during the bias phase. However, by initializing the light-emitting element 20 during the bias phase, it can be ensured that the light-emitting element 20 does not emit light.

[0114] In other embodiments, such as Figure 8 As shown, a portion of the reset phase can also be reused as the initialization phase. Provided that reset, bias, and initialization do not cause interference, relevant personnel can appropriately configure the reset timing, bias timing, and initialization timing.

[0115] refer to Figure 10 , Figure 10 This is a schematic diagram of the third operating timing of the pixel circuit, combined with... Figure 3 The pixel circuit shown can optionally include a reset stage and a bias stage in the pre-processing stage; in the reset stage, the gate of the driving transistor receives a reset signal to reset.

[0116] During the reset phase, the scan signal S1 outputs a high-level pulse, turning on the seventh transistor T7 and turning off the first transistor T1. The reset signal Vref is written to the gate of the driving transistor T0, resetting the gate of the driving transistor T0 to a negative potential less than 0V. During the bias phase, the scan signal S1 outputs a low-level pulse, turning off the seventh transistor T7 and causing the EM1 signal to go low. The first transistor T1 turns on, while the second transistor T2 remains off. The first power supply signal PVDD is written to the drain of the driving transistor T0, thus biasing the driving transistor.

[0117] The optional bias phase has a duration of t1, and the reset phase has a duration of t3, where t1 > t3.

[0118] The reset phase is only used to write a reset signal to the gate of the driving transistor, resetting the gate to a negative potential less than 0V. Therefore, the reset phase duration t3 can be relatively short. In the bias phase, the first power supply signal is written to the drain of the driving transistor, biasing it to reduce the threshold voltage drift during the light-emitting phase. Since the light-emitting phase is relatively long, the bias phase duration t1 is also relatively long to sufficiently reduce the threshold voltage drift during the unbiased phase. Therefore, t1 is set to > t3.

[0119] like Figure 10 When the optional reset phase ends, the gate of the driving transistor is disconnected from the reset signal. Simultaneously, the first light-emitting control module is turned on, and the pixel circuit enters the bias phase. In this embodiment, when the reset phase of the pixel circuit ends, the first light-emitting control module is turned on to enter the bias phase. Therefore, there is no time interval between the reset phase and the bias phase, ensuring that the pre-processing phase of the pixel circuit is shortened as much as possible, thereby reducing the duration of one frame.

[0120] refer to Figure 11 , Figure 11A schematic diagram of the fourth operating timing of the pixel circuit is shown. The timing can be selected between the end of the reset phase and the beginning of the bias phase. The pre-phase includes a first interval phase. In the first interval phase, the gate of the driving transistor is disconnected from the reset signal, and the first light-emitting control module remains off. In this embodiment, during the first interval phase, the scan signal S1 transitions from a high level to a low level, the seventh transistor T7 is turned off, and the gate of the driving transistor is disconnected from the reset signal. The first light-emitting control signal EM1 remains a high-level pulse signal, and the first light-emitting control module remains off, allowing the driving transistor to have a stable period. At the end of the first interval phase, the first light-emitting control signal EM1 transitions to a low-level pulse signal, the first light-emitting control module is turned on, and the pixel circuit enters the bias phase. By stabilizing the driving transistor through the first interval phase after the reset phase before entering the bias phase, the stability of the pixel circuit can be improved.

[0121] The optional bias phase duration is t1, the reset phase duration is t3, and the first interval phase duration is t4, where t1 > t4 or t3 > t4. It can be understood that the reset phase is only used to reset the gate voltage of the driving transistor, and the first interval phase is used to stabilize the driving transistor. Therefore, the reset phase duration t3 and the first interval phase duration t4 only need to have one response time length, without needing to be too long. Therefore, t1 > t4 or t3 > t4 is set.

[0122] refer to Figure 12 , Figure 12 This is a schematic diagram of the fifth operating timing of the pixel circuit, where the time periods of the optional reset phase and bias phase at least partially overlap. For Figure 3 The pixel circuit shown has a reset module 17 directly connected to the gate of the driving transistor T0. When the first power supply signal is written to the drain of the driving transistor during the bias phase, the operations of the reset phase and the bias phase do not affect each other when the second transistor T2 is turned off. Therefore, the time periods of the optional reset phase and bias phase can at least partially overlap.

[0123] During the reset phase, the second transistor T2 is turned off and the seventh transistor T7 is turned on, so the reset signal Vref is written to the gate of the driving transistor T0. During the overlap of the bias and reset phases, the second transistor T2 remains off and the first transistor T1 is turned on, so the first power supply signal is written to the drain of the driving transistor T0. Simultaneously, the seventh transistor T7 remains on, so the reset signal Vref is continuously written to the gate of the driving transistor T0, stabilizing the gate voltage of the driving transistor T0. By performing the reset phase concurrently with the bias phase, the potential of the drain of the driving transistor T0 is adjusted by the first power supply signal, and the potential of the gate of the driving transistor T0 is adjusted by the reset signal, achieving simultaneous adjustment of the gate and drain potentials of the driving transistor, thereby improving the bias effect.

[0124] refer to Figure 13 , Figure 13 This is a schematic diagram of the sixth operating timing of the pixel circuit. Optionally, during the bias phase, the gate of the driving transistor receives a reset signal. During the bias phase, the second transistor T2 remains off, the first transistor T1 remains on, and the seventh transistor T7 remains on. A first power supply signal is written to the drain of the driving transistor T0, and simultaneously, the reset signal Vref is continuously written to the gate of the driving transistor T0, stabilizing the gate voltage of the driving transistor T0 during the bias phase. Furthermore, the reset phase overlaps with the bias phase, shortening the pre-processing time of the pixel circuit and enabling high-frequency display. Optionally, the on-time of the reset phase is earlier than or equal to the on-time of the bias phase, and the end-time of the reset phase is later than or equal to the end-time of the bias phase.

[0125] refer to Figure 14 , Figure 14 This is a schematic diagram of the seventh operating timing of the pixel circuit. The optional reset phase includes a first reset phase and a second reset phase. In the first reset phase, which does not overlap with the bias phase, the gate of the driving transistor receives a first reset signal. During at least a portion of the bias phase, the gate of the driving transistor receives a second reset signal, and the bias phase and the second reset phase at least partially overlap. The first reset phase can be used to reset the gate potential of the driving transistor, and in some cases, it can lower the gate potential below 0V. The second reset phase can be used to stabilize the gate potential of the driving transistor during the bias phase, realizing bias adjustment of the driving transistor. A portion of the optional bias phase overlaps with the second reset phase, or the entire duration of the optional bias phase overlaps with the second reset phase.

[0126] Optionally, the first reset signal and the second reset signal can have the same potential. Alternatively, the first reset signal and the second reset signal can have different potentials. The first reset signal needs to pull down the gate potential of the driving transistor, making the first reset signal less than 0V. The second reset signal is used to stabilize the gate potential of the driving transistor during the biasing phase, thereby improving the biasing effect. Based on this, the second reset signal can be the same as or different from the first reset signal. Those skilled in the art can flexibly design pixel circuits according to different design requirements.

[0127] Optionally, the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the first reset signal is lower than the potential of the second reset signal; or, the driving transistor is an NMOS transistor, and the potential of the first reset signal is higher than the potential of the second reset signal. Optionally, if the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal, then, while the second reset signal plays a biasing role during the biasing phase, using a second reset signal with a lower absolute value can reduce the power consumption of the pixel circuit.

[0128] In another embodiment, optionally, the absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the second reset signal is lower than the potential of the first reset signal; or, the driving transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal. Optionally, the absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal. In specific cases of the display panel, such as high-frequency driving, during the reset phase, the level of the first reset signal is a relatively small negative potential, which can shorten the data writing phase time, thereby helping to achieve high-frequency driving.

[0129] refer to Figure 15 , Figure 15 This is a schematic diagram of the eighth operating timing of the pixel circuit. In the bias phase, the second reset phase is performed at least twice, and the gate of the driving transistor is disconnected from the reset signal between adjacent second reset phases. In this embodiment, multiple second reset phases can be designed in the bias phase. Each second reset phase can reset the gate potential of the driving transistor, stabilizing the gate potential of the driving transistor in the bias phase, facilitating bias adjustment of the driving transistor, and further improving the bias effect.

[0130] Optional, such as Figure 14 and Figure 15As shown, before the end of the bias phase, the gate of the driving transistor is disconnected from the reset signal, and then the bias phase ends. Before the end of the bias phase, the seventh transistor T7 is turned off, disconnecting the gate of the driving transistor from the reset signal. After the end of the bias phase, the bias phase ends. In this way, the drain of the driving transistor can still receive the first power supply signal after the reset phase ends, ensuring the bias effect of the driving transistor.

[0131] Additionally, optional, such as Figure 13 As shown, the gate of the driving transistor is disconnected from the reset signal at the end of the bias phase. In this embodiment, the entire time period of the bias phase overlaps with the reset phase. The start time of the reset phase is earlier than or the same as the start time of the bias phase, and the end time of the reset phase is later than or the same as the end time of the bias phase. For example, in some embodiments, the gate of the driving transistor may be disconnected from the reset signal again after the end of the bias phase. As described above, the reset signal is continuously written to the gate of the driving transistor during both the reset and bias phases, ensuring the stability of the gate voltage of the driving transistor before the data writing phase and improving the biasing effect.

[0132] Optional, such as Figures 3-7 As shown, in this embodiment, the pixel circuit 10 further includes a data writing module 16, which is used to selectively provide data signals to the driving module 12. Optionally, in this embodiment, the pre-stage includes a bias stage and a data writing stage. In the data writing stage, the data writing module 16, the driving module 12, and the compensation module 13 are all turned on, and the data signal is written to the gate of the driving transistor T0. In the data writing stage, the fifth transistor T5, the driving transistor T0, and the second transistor T2 are all turned on, and the data signal is written to the control terminal of the driving module 12, i.e., the gate of the driving transistor T0, through the turned-on data writing module 16, the driving module 12, and the compensation module 13.

[0133] The optional bias phase has a duration of t1, and the data writing phase has a duration of t5, where t1 > t5. It can be understood that the data writing phase is only used to write the data signal to the gate of the driving transistor, so the response time is sufficient. During the bias phase, the first power supply signal is written to the drain of the driving transistor, biasing the driving transistor to reduce the threshold voltage drift of the driving transistor during the light emission phase. Since the non-bias phases, such as the light emission phase, have a longer duration, the duration of the bias phase t1 is increased to sufficiently reduce the threshold voltage drift during the non-bias phases. Based on this, t1 > t5 is set.

[0134] refer to Figure 16 , Figure 16This is a schematic diagram of the ninth operating timing of the pixel circuit. From the end of the bias phase to the beginning of the data writing phase, the pixel circuit includes a second interval phase. During this second interval phase, the first light-emitting control module is turned off, and the data writing module remains off. In this embodiment, during the second interval phase, the first light-emitting control signal EM1 transitions from a low level to a high level, causing the first transistor T1 to turn off, disconnecting the drain of the driving transistor from the first power supply signal. Simultaneously, the data writing module remains off, allowing the driving transistor to have a stabilization period. At the end of the second interval phase, the first light-emitting control signal EM1 remains high, causing the first transistor T1 to turn off, and the pixel circuit enters the data writing phase. By stabilizing the driving transistor through the second interval phase after the bias phase ends, the stability of the pixel circuit can be improved before entering the data writing phase.

[0135] The optional bias phase has a duration of t1, the data writing phase has a duration of t5, and the second interval phase has a duration of t6, where t1 > t6 or t5 > t6. It can be understood that the data writing phase is only used to write the data signal to the gate of the driving transistor, and the second interval phase is used to stabilize the driving transistor. Therefore, the duration t5 of the data writing phase and the duration t6 of the second interval phase can have only one response time length, without needing to be too long. Therefore, t1 > t6 or t5 > t6 is set.

[0136] Alternatively, in this embodiment, it can also be as follows: Figures 10-15 As shown, at the end of the optional bias stage, the first light-emitting control module is turned off, and simultaneously, the data writing module is turned on, and the pixel circuit enters the data writing stage. In this embodiment, when the first light-emitting control module is turned off at the end of the bias stage, the first power signal will not be written to the source of the driving transistor. At the same time, the data writing module is turned on, the pixel circuit enters the data writing stage, and the data signal is written to the drain of the driving transistor via the source of the driving transistor. Thus, the first light-emitting control module is turned off during the data writing stage to prevent the first power signal from affecting the data writing process. In addition, this method can also significantly shorten the duration of the pre-phase while ensuring the length of the bias stage, thereby facilitating the realization of high-frequency displays.

[0137] Optionally, in this embodiment, reference is made to... Figure 6 as well as Figures 10-16 The pixel circuit also includes a data writing module, which is used to selectively provide data signals to the driving module. The pre-stage includes a reset stage, a bias stage and a data writing stage in sequence. In the reset stage, the gate of the driving transistor receives a reset signal to reset. In the data writing stage, the data writing module, the driving module and the compensation module are all turned on, and the data signal is written to the gate of the driving transistor.

[0138] In this embodiment, during the pre-processing stage of the pixel circuit, the gate of the driving transistor is first reset, causing the gate voltage of the driving transistor to be pulled down to a negative voltage below 0V, facilitating subsequent biasing of the driving transistor. Next, the driving transistor is biased by writing a first power supply signal to the drain of the driving transistor, reducing the threshold voltage drift of the driving transistor caused by the non-biasing stage. Finally, during the data writing stage, the data writing module, driving module, and compensation module are all activated, and the data signal is written to the gate of the driving transistor.

[0139] The optional bias phase duration is t1, the reset phase duration is t3, and the data write phase duration is t4, where t1 > t3 and t4. Within one frame, the non-bias phase causes threshold voltage drift in the driving transistor, and since the non-bias phase is relatively long, the bias phase duration is set to be longer to reduce threshold voltage drift in the non-bias phase. The data write phase is only used to write data signals to the gate of the driving transistor, so the data write phase duration is set to be shorter. The reset phase is only used to write reset signals to the gate of the driving transistor, so the reset phase duration is set to be shorter. Based on this, t1 > t3 and t4 are set.

[0140] refer to Figure 17 , Figure 17 This is a schematic diagram of the tenth working timing of the pixel circuit. For example, based on any of the above embodiments, the optional bias stage includes m sub-bias stages performed sequentially, where m ≥ 1; among the m sub-bias stages, the interval between two adjacent sub-bias stages is the third interval stage, in which the first light emission control module is turned off.

[0141] like Figure 17 As shown, the optional bias stage includes at least two sub-bias stages performed sequentially, with a third interval stage between two adjacent sub-bias stages. In the sub-bias stage, the first light-emitting control module is turned on, and a first power supply signal is written to the drain of the driving transistor. In the third interval stage, the first light-emitting control module is turned off. Specifically, in the sub-bias stage, the first light-emitting control signal EM1 outputs a valid pulse signal, causing the first light-emitting control module to turn on. The first power supply signal is then sequentially written to the drain of the driving transistor through the first light-emitting control module and the driving module, thus biasing the driving transistor. In the third interval stage, the first light-emitting control signal EM1 outputs an invalid pulse signal, causing the first light-emitting control module to turn off, thus disconnecting the first power supply signal from the drain of the driving transistor. Since the bias stage includes multiple sub-bias stages, each sub-bias stage can reduce the threshold voltage drift of the driving transistor in the non-bias stage. Through multiple sub-bias stages, the threshold voltage drift of the driving transistor caused by the non-bias stage can be sufficiently reduced, further improving the biasing effect.

[0142] In other embodiments, alternatives may also be selected, such as Figure 11 The biasing stage shown includes a sub-biasing stage, namely the biasing stage, in which the first light-emitting control module is normally open.

[0143] The optional bias stage includes at least two third interval stages, wherein the durations of the at least two third interval stages are not equal. The duration of the optional third interval stage increases or decreases sequentially with the m sub-bias stages. The duration of at least one optional third interval stage may be shorter than the duration of at least one sub-bias stage. The third interval stage is a transition stage between sub-bias stages; therefore, its duration can be shorter than the duration of the sub-bias stages. Specifically, the duration of any third interval stage is shorter than the duration of any sub-bias stage. It is understood that the durations of the multiple third interval stages can be the same or different, or the durations of the multiple third interval stages may satisfy rules such as increasing or decreasing. In this embodiment of the invention, the bias stages of the pixel circuit are flexibly designed according to the bias requirements of the pixel circuit under different conditions, and are not limited thereto.

[0144] Among the selectable m sub-biasing stages, at least two sub-biasing stages have unequal durations. The duration of the first sub-biasing stage may be longer than the durations of the other sub-biasing stages. The duration of each sub-biasing stage may decrease sequentially with each of the m sub-biasing stages. It is understood that the durations of multiple sub-biasing stages can be the same or different, or the durations of multiple sub-biasing stages may follow increasing or decreasing rules. In this embodiment of the invention, the biasing stages of the pixel circuit are flexibly designed according to the biasing requirements of the pixel circuit under different circumstances, and are not limited to these limitations.

[0145] When the first sub-biasing stage is longer than the others, biasing the driving transistor during the first sub-biasing stage effectively reduces the threshold voltage drift of the driving transistor in the unbiased stage. Subsequent, shorter sub-biasing stages allow for dynamic bias adjustments based on the bias conditions. Through multiple sub-biasing stages, the threshold voltage drift of the driving transistor in the unbiased stage is sufficiently reduced, ensuring that the biasing stage duration is not excessively long.

[0146] Optional, combined Figure 17 and Figure 16The duration of at least one third interval phase is not equal to the duration of the second interval phase. Since the third interval phase is the interval between any two adjacent sub-bias phases, and the second interval phase is the time interval between the bias phase and the data writing phase, the durations of the second and third interval phases can be flexibly set depending on the specific circumstances. In some implementations, the duration of the second interval phase is longer than the duration of the third interval phase. In other implementations, the duration of the second interval phase may be shorter than the duration of the third interval phase.

[0147] For example, based on any of the above embodiments, one data write cycle of the optional display panel includes S frames of refresh, including data write frames and hold frames, where S > 0. At least one data write frame includes a bias phase. During the data write frame phase, the pixel circuit writes new display data; during the hold frame phase, the pixel circuit refreshes normally but holds the display data of the previous frame and does not write new display data. During the data write frame time, in the bias phase, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The first power signal is written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor.

[0148] refer to Figure 18 , Figure 18 This is a schematic diagram of the eleventh operating timing of the pixel circuit. In this embodiment, at least one data write frame and at least one hold frame may include a bias phase, and the duration of the bias phase within the at least one hold frame is longer than the duration of the bias phase within the data write frame. During the hold frame's display time, in the bias phase, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The first power signal is then written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor. The hold frame displays the previous frame and does not include the data write phase. As long as the first light-emitting control module is turned on, the compensation module is turned off, and the second light-emitting control module is turned off, it constitutes the bias phase. Therefore, a longer duration can be used for bias adjustment. The data write frame displays the new frame and needs to ensure its normal light-emitting phase duration. Based on this, the duration of the bias phase within the at least one hold frame may be longer than the duration of the bias phase within the data write frame, achieving a better bias effect while ensuring display quality.

[0149] refer to Figure 19 , Figure 19This is a schematic diagram of the twelfth operating timing of the pixel circuit. The optional display panel includes at least two data write frames, wherein the bias phase durations of the at least two data write frames are different. The optional display panel includes a first data write frame and a second data write frame, with n second data write frames between any two adjacent first data write frames, where n≥1; the bias phase duration in the first data write frame is t7, and the bias phase duration in the second data write frame is t8, where t7>t8≥0.

[0150] The display panel shows multiple second data write frames. In each second data write frame, the bias phase lasts for t8 seconds. During this phase, the gate and drain voltages of the driving transistor are biased, reducing the threshold voltage drift. However, in practical applications, the bias phase in the second data write frame cannot sufficiently reduce the threshold voltage drift. Therefore, after multiple second data write frames are displayed, the accumulated drift over time will still cause changes in the internal characteristics of the driving transistor. To address this, the bias phase in the first data write frame is lengthened to t7 seconds. By increasing the duration of this bias phase, the accumulated threshold voltage drift of the driving transistor by the time the next frame is reduced, improving the bias effect and thus enhancing display uniformity.

[0151] In some implementations, the second data write frame may not include the bias phase, i.e., t8 = 0. In this case, it is not necessary to perform the bias phase in every data write frame. The bias phase can be set only in the first data write frame, thereby simplifying the driving process of the display panel.

[0152] refer to Figure 20 , Figure 20 This is a schematic diagram of the thirteenth operating timing of the pixel circuit. One data write cycle of the optional display panel includes S frames of refresh, including data write frames and hold frames, where S > 0. At least one hold frame includes a bias phase. In this embodiment, during the hold frame phase, the pixel circuit refreshes normally but holds the display data of the previous frame. This hold frame does not include the data write phase; therefore, the hold frame displays the display data of the previous frame. During the hold frame's duration, in the bias phase, a first power signal is written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor. After this bias phase ends, the hold frame directly enters the light-emitting phase to display the previous frame. This shortens the duration of the hold frame's pre-phase, thereby shortening the working time of the hold frame and increasing the frame refresh rate.

[0153] Optional, such as Figure 20As shown, in the holding frame, the pre-processing stage includes a reset stage and a bias stage in sequence; in the reset stage, the gate of the driving transistor receives a reset signal to reset; there is no data writing stage between the bias stage and the light emission stage.

[0154] refer to Figure 21 , Figure 21 This is a schematic diagram of the fourteenth operating timing of the pixel circuit. One data write cycle of the optional display panel includes S frames of refresh, including data write frames and hold frames, where S > 0. At least one hold frame includes a bias phase. Within the hold frame, the pre-set phase includes a reset phase and a bias phase. During the reset phase, the gate of the driving transistor receives a reset signal to reset. The reset phase and the bias phase at least partially overlap in time. In this embodiment, since the reset phase and the bias phase at least partially overlap within the hold frame, the duration of the pre-set phase of the hold frame can be further shortened, thereby shortening the working time of the hold frame and further increasing the frame refresh rate.

[0155] It should be noted that in this embodiment, only the pre-processing stage of the data write frame may include the bias stage, while the pre-processing stage of the hold frame may not include the bias stage. In this case, if the bias problem can be solved using only the data write frame, then there is no need to set the bias stage in the hold frame. Alternatively, only the pre-processing stage of the hold frame may include the bias stage, while the pre-processing stage of the data write frame may not include the bias stage. Since the data write frame also undertakes the work of the reset stage and the data write stage, if the hold frame can fully undertake the work of the bias stage, then there is no need to set the bias stage in the data write frame, thereby simplifying the timing of the data write frame.

[0156] It should be noted that the above figures illustrate the case where the initialization phase, bias phase, and reset phase of the light-emitting element at least partially overlap. However, this embodiment is not limited to this. In some other embodiments, the initialization phase may not overlap with the bias phase, or the initialization phase may be performed simultaneously throughout the entire bias phase, or the initialization phase may continue even after the bias phase ends. All of these solutions are acceptable. The design can be flexibly adapted to the specific circuit conditions.

[0157] Based on the same inventive concept, this embodiment of the invention also provides a driving method for a display panel. In this embodiment, the display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a light-emitting control module, a driving module, and a compensation module; the light-emitting control module includes a first light-emitting control module, which is used to selectively provide a first power signal to the driving module; the driving module is used to provide a driving current to the light-emitting element, and the driving module includes a driving transistor; the compensation module is used to compensate for the threshold voltage deviation of the driving transistor.

[0158] refer to Figure 22 , Figure 22 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention. The driving method for at least one frame of the display panel includes:

[0159] S1. During the light-emitting stage, the first light-emitting control module is turned on, and the driving transistor and the light-emitting element are connected.

[0160] S2. During the biasing phase, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. The driving transistor is disconnected from the light-emitting element. The first power supply signal is written from the source of the driving transistor to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0161] In other implementations of the driving method, the method used in the driving process of any of the foregoing implementations can be referred to, and should be understood as being within the protection scope of the driving method of this embodiment.

[0162] In this embodiment of the invention, the operation of the pixel circuit includes a biasing stage. During the biasing stage, the first light-emitting control module and the driving module are turned on, and the compensation module is turned off. A first power signal is written to the drain of the driving transistor through the turned-on first light-emitting control module and driving module to adjust the drain potential of the driving transistor, thereby improving the potential difference between the gate potential and the drain potential of the driving transistor. It is known that a pixel circuit includes at least one unbiased stage. When a driving current is generated in the driving transistor, there may be a situation where the gate potential of the driving transistor is greater than the drain potential, causing the IV curve of the driving transistor to shift and the threshold voltage of the driving transistor to drift. During the biasing stage, by adjusting the gate potential and drain potential of the driving transistor, the shift phenomenon of the IV curve of the driving transistor in the unbiased stage can be balanced, the threshold voltage drift phenomenon of the driving transistor can be reduced, and the display uniformity of the display panel can be ensured.

[0163] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel as described in any of the above embodiments. Optionally, the display panel can be an organic light-emitting display panel or a micro LED display panel.

[0164] refer to Figure 23 , Figure 23 This is a schematic diagram of a display device provided in an embodiment of the present invention. Optionally, this display device can be applied to electronic devices 100 such as smartphones and tablet computers. It is understood that the above embodiments only provide partial examples of the pixel circuit structure and the driving method of the pixel circuit; the display panel also includes other structures, which will not be described in detail here.

[0165] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a light emission control module; The driving module includes a driving transistor; The light emission control module includes: A first light-emitting control module is connected between a first power signal line and the source of the driving transistor. The first power signal line is used to provide a first power signal. The second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element; The operation of the pixel circuit includes a light-emitting stage and a biasing stage; wherein... During the light-emitting stage, both the first light-emitting control module and the second light-emitting control module are turned on. During the biasing phase, the first light-emitting control module is turned on, and the second light-emitting control module is turned off. The biasing phase includes m sub-biasing phases, where m ≥ 1; The durations of the m sub-biasing stages are not equal, and the duration of the first sub-biasing stage is longer than the durations of the other sub-biasing stages.

2. The display panel according to claim 1, characterized in that, The interval between two adjacent sub-biasing stages is a third interval stage. The time lengths of at least two of the third interval stages are not equal, and the time length of the third interval stage increases sequentially with the m sub-biasing stages.

3. The display panel according to claim 1, characterized in that, The duration of the sub-biasing phase decreases sequentially with each of the m sub-biasing phases.

4. The display panel according to claim 2, characterized in that, During the third interval phase, the first light-emitting control module is turned off.

5. The display panel according to claim 2, characterized in that, The duration of at least one of the third interval stages is less than the duration of at least one of the sub-bias stages.

6. The display panel according to claim 5, characterized in that, The duration of any of the third interval stages is less than the duration of any of the sub-bias stages.

7. The display panel according to claim 2, characterized in that, The pixel circuit includes a data writing module. During the data writing phase, the data writing module is activated to provide data signals to the driving module. The period between the end of the bias phase and the start of the data writing phase includes a second interval phase, during which both the first light-emitting control module and the data writing module are turned off; wherein... The duration of at least one of the third interval stages is not equal to the duration of the second interval stage.

8. The display panel according to claim 7, characterized in that, The duration of the second interval phase is longer than the duration of the third interval phase.

9. The display panel according to claim 7, characterized in that, The duration of the second interval phase is shorter than the duration of the third interval phase.

10. The display panel according to claim 1, characterized in that, The control terminal of the first light-emitting control module is connected to the first light-emitting control signal line and is used to receive the first light-emitting control signal. The control terminal of the second light-emitting control module is connected to the second light-emitting control signal line and is used to receive the second light-emitting control signal.

11. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a light emission control module; The light-emitting control module includes a first light-emitting control module, which is used to provide a first power signal to the driving module; The operation of the pixel circuit includes a light-emitting stage and a biasing stage; wherein... During the light-emitting stage, the first light-emitting control module is turned on, and the driving module is connected to the light-emitting element; During the biasing phase, the first light-emitting control module is turned on, and the driving module is disconnected from the light-emitting element; The biasing phase includes m sub-biasing phases, where m ≥ 1; The durations of the m sub-biasing stages are not equal, and the duration of the first sub-biasing stage is longer than the durations of the other sub-biasing stages.

12. The display panel according to claim 11, characterized in that, The interval between two adjacent sub-biasing stages is a third interval stage, and the time lengths of at least two of the third interval stages are not equal. The time length of the third interval stage increases sequentially with the m sub-biasing stages.

13. The display panel according to claim 11, characterized in that, The duration of the sub-biasing phase decreases sequentially with each of the m sub-biasing phases.

14. The display panel according to claim 12, characterized in that, During the third interval phase, the first light-emitting control module is turned off.

15. The display panel according to claim 12, characterized in that, The duration of at least one of the third interval stages is less than the duration of at least one of the sub-bias stages.

16. The display panel according to claim 15, characterized in that, The duration of any of the third interval stages is less than the duration of any of the sub-bias stages.

17. The display panel according to claim 12, characterized in that, The pixel circuit includes a data writing module. During the data writing phase, the data writing module is activated to provide data signals to the driving module. The period between the end of the bias phase and the start of the data writing phase includes a second interval phase, during which both the first light-emitting control module and the data writing module are turned off; wherein... The duration of at least one of the third interval stages is not equal to the duration of the second interval stage.

18. The display panel according to claim 17, characterized in that, The duration of the second interval phase is longer than the duration of the third interval phase.

19. The display panel according to claim 17, characterized in that, The duration of the second interval phase is shorter than the duration of the third interval phase.

20. A driving method for a display panel, characterized in that, The display panel includes pixel circuitry and light-emitting elements; The pixel circuit includes a driving module and a light emission control module; The driving module includes a driving transistor; The light emission control module includes: A first light-emitting control module is connected between a first power signal line and the source of the driving transistor. The first power signal line is used to provide a first power signal. The second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element; The method for driving at least one frame of the display panel includes: The luminescence phase and the bias phase; among which, During the light-emitting stage, both the first light-emitting control module and the second light-emitting control module are turned on. During the biasing phase, the first light-emitting control module is turned on, and the second light-emitting control module is turned off. The biasing phase includes m sub-biasing phases, where m ≥ 1; The durations of the m sub-biasing stages are not equal, and the duration of the first sub-biasing stage is longer than the durations of the other sub-biasing stages.

21. The driving method for a display panel according to claim 20, characterized in that, The interval between two adjacent sub-biasing stages is a third interval stage. The time lengths of at least two of the third interval stages are not equal, and the time length of the third interval stage increases sequentially with the m sub-biasing stages.

22. A driving method for a display panel, characterized in that, The display panel includes pixel circuitry and light-emitting elements; The pixel circuit includes a driving module and a light emission control module; The light-emitting control module includes a first light-emitting control module, which is used to provide a first power signal to the driving module; The method for driving at least one frame of the display panel includes: The luminescence phase and the bias phase; among which, During the light-emitting stage, the first light-emitting control module is turned on, and the driving module is connected to the light-emitting element; During the biasing phase, the first light-emitting control module is turned on, and the driving module is disconnected from the light-emitting element; The biasing phase includes m sub-biasing phases, where m ≥ 1; The durations of the m sub-biasing stages are not equal, and the duration of the first sub-biasing stage is longer than the durations of the other sub-biasing stages.

23. The driving method for a display panel according to claim 22, characterized in that, The interval between two adjacent sub-biasing stages is a third interval stage. The time lengths of at least two of the third interval stages are not equal, and the time length of the third interval stage increases sequentially with the m sub-biasing stages.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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