Pixel circuits, display panels and display devices

Abstract

This application provides a pixel circuit, a display panel, and a display device. The pixel circuit includes: a driving module; a bias compensation module, wherein the control terminal of the bias compensation module is electrically connected to a first control signal line, the first terminal of the bias compensation module is electrically connected to a target signal line, and the second terminal of the bias compensation module is electrically connected to either the first terminal or the second terminal of the driving module; the target signal line is electrically connected to a first periodic signal. This application can adjust the bias state of the threshold voltage of the driving module and can flexibly meet the adjustment requirements of the threshold voltage of the driving module under different conditions.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a pixel circuit, a display panel, and a display device. Background Technology

[0002] Figure 1 This is a schematic diagram illustrating the Id-Vg curve drift of the driving module in the pixel circuit. (Example:) Figure 1 As shown, during the non-biased phases such as the light-emitting stage, the control terminal potential of the pixel circuit may be higher than the second terminal potential. Prolonged use of this setting can lead to ion polarization within the driver module, resulting in a built-in electric field. This causes the threshold voltage Vth of the driver module to continuously increase, causing a shift in the Id-Vg curve, which in turn affects the driving current flowing into the light-emitting element and consequently impacts display uniformity. For example, when switching from a black screen to a white screen, the display brightness increases slowly, requiring 4-5 frames of data refresh before stabilizing. Due to this long recovery time, the human eye can perceive screen flicker. Summary of the Invention

[0003] This application provides a pixel circuit, a display panel, and a display device that can adjust the bias state of the threshold voltage of the driving module and flexibly meet the adjustment requirements of the threshold voltage of the driving module under different circumstances.

[0004] In a first aspect, embodiments of this application provide a pixel circuit, which includes: a driving module; a bias compensation module, wherein the control terminal of the bias compensation module is electrically connected to a first control signal line, the first terminal of the bias compensation module is electrically connected to a target signal line, and the second terminal of the bias compensation module is electrically connected to the first terminal of the driving module or the second terminal of the driving module; and the target signal line is electrically connected to a first periodic signal.

[0005] Secondly, based on the same inventive concept, embodiments of this application provide a display panel, which includes multiple rows of pixel circuits, each row of pixel circuits including the pixel circuits provided in the first aspect.

[0006] Thirdly, based on the same inventive concept, embodiments of this application provide a display device, which includes a display panel as provided in the second aspect.

[0007] The pixel circuit, display panel, and display device of this application embodiment, on the one hand, allow the bias compensation module to transmit the first periodic signal of the target signal line to the first end or the second end of the driving module, thereby improving the potential difference between the potential of the second end of the driving module and the potential of the control end, reducing the degree of ion polarization inside the driving module, lowering the threshold voltage of the driving module, and adjusting the bias state of the threshold voltage of the driving module; on the other hand, since the target signal line provides the first periodic signal, when adjusting the threshold voltage of the driving module, any voltage value of the first periodic signal or a combination of multiple voltage values ​​can be selected to adjust the threshold voltage of the driving module, thereby flexibly meeting the adjustment requirements of the threshold voltage of the driving module under different circumstances. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the Id-Vg curve drift of the driving module in the pixel circuit.

[0010] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0011] Figure 3 The illustration schematically depicts a first-periodic signal;

[0012] Figure 4 A timing diagram of the first periodic signal during the first bias compensation stage and the second bias compensation stage;

[0013] Figure 5 Another timing diagram of the first periodic signal during the first bias compensation stage and the second bias compensation stage;

[0014] Figure 6 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0015] Figure 7 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0016] Figure 8 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0017] Figure 9 for Figure 8 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0018] Figure 10 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0019] Figure 11 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0020] Figure 12 for Figure 11 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0021] Figure 13 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0022] Figure 14 for Figure 13 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0023] Figure 15 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0024] Figure 16 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of this application;

[0025] Figure 17 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0026] Figure 18 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0027] Figure 19 for Figure 18 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0028] Figure 20 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0029] Figure 21 Another structural schematic diagram of the display panel provided in the embodiments of this application;

[0030] Figure 22 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0031] Figure 23 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0032] Figure 24 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0033] Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0034] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0035] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0036] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0037] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0038] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0039] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0040] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0041] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0042] like Figure 1As shown, during the non-biased phases such as the light-emitting stage, the control terminal potential of the pixel circuit may be higher than the second terminal potential. Prolonged use of this setting can lead to ion polarization within the driver module, resulting in a built-in electric field. This causes the threshold voltage Vth of the driver module to continuously increase, causing a shift in the Id-Vg curve, which in turn affects the driving current flowing into the light-emitting element and consequently impacts display uniformity. For example, when switching from a black screen to a white screen, the display brightness increases slowly, requiring 4-5 frames of data refresh before stabilizing. Due to this long recovery time, the human eye can perceive screen flicker.

[0043] Currently, although some solutions can adjust the second terminal potential of the drive module and thus adjust the threshold voltage Vth of the drive module by adding a bias compensation signal (DVH signal), the current bias compensation signal is usually a constant voltage signal, that is, a voltage signal with a fixed potential, which cannot meet the adjustment requirements of the threshold voltage of the drive module under different conditions.

[0044] In view of the inventors’ above-mentioned research findings, the embodiments of this application provide a pixel circuit, a display panel and a display device, which can solve the above-mentioned technical problems existing in the related art.

[0045] The technical concept of this application embodiment is as follows: the control terminal of the bias compensation module in the pixel circuit is electrically connected to the first control signal line, the first terminal of the bias compensation module is electrically connected to the target signal line, the second terminal of the bias compensation module is electrically connected to the first terminal of the driving module or the second terminal of the driving module, the target signal line is electrically connected to the first periodic signal, and the potential of the second terminal of the driving module is adjusted by the first periodic signal, thereby adjusting the threshold voltage of the driving module.

[0046] In this way, on the one hand, the bias compensation module can transmit the first periodic signal of the target signal line to the first or second end of the drive module, improve the potential difference between the potential of the second end and the control end of the drive module, reduce the degree of ion polarization inside the drive module, reduce the threshold voltage of the drive module, and adjust the bias state of the threshold voltage of the drive module. On the other hand, since the target signal line provides the first periodic signal, when adjusting the threshold voltage of the drive module, any voltage value of the first periodic signal or a combination of multiple voltage values ​​can be selected to adjust the threshold voltage of the drive module, thereby flexibly meeting the adjustment requirements of the threshold voltage of the drive module under different conditions.

[0047] The pixel circuit provided in the embodiments of this application will be described below.

[0048] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 2 As shown, the pixel circuit 20 provided in this embodiment may include a driving module 201 and a bias compensation module 202. The driving module 201 can be used to drive the light-emitting element D to emit light. Exemplarily, the light-emitting element D includes, but is not limited to, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), or quantum dot (QDs). Inorganic light-emitting diodes include, but are not limited to, mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (QLEDs).

[0049] The control terminal of the bias compensation module 202 is electrically connected to the first control signal line K1, the first terminal of the bias compensation module 202 is electrically connected to the target signal line V1, and the second terminal of the bias compensation module 202 is electrically connected to either the first terminal a or the second terminal b of the driving module 201. For example, when the driving module 201 is a thin-film transistor (TFT), the first terminal a of the driving module 201 can be the source of the TFT, and the second terminal b of the driving module can be the drain of the TFT. Of course, the first terminal a of the driving module 201 can also be the drain of the TFT, and the second terminal b of the driving module can be the source of the TFT; this embodiment of the application does not limit this.

[0050] In this embodiment, the target signal line V1 is electrically connected to the first periodic signal. Alternatively, the target signal line V1 is used to transmit the first periodic signal. Exemplarily, the first periodic signal may include a pulse signal. This embodiment does not limit the shape of the pulse signal; the pulse signal includes, but is not limited to, rectangular pulse signals, sine signals, or cosine signals.

[0051] Optionally, when the bias compensation module 202 is turned on, the drive module 201 is also turned on. Therefore, regardless of whether the first periodic signal is transmitted to the first terminal a of the drive module 201 or the second terminal b of the drive module 201, the first periodic signal can ultimately be transmitted to the second terminal b of the drive module 201. It should be noted that... Figure 2 The illustration only takes the example of the second end of the bias compensation module 202 being electrically connected to the first end a of the drive module 201. However, it can be understood that the second end of the bias compensation module 202 can also be electrically connected to the second end b of the drive module 201.

[0052] On the one hand, the bias compensation module 202 transmits the first periodic signal of the target signal line V1 to the first end of the driving module 201 or the second end of the driving module, which can improve the potential difference between the potential of the second end of the driving module and the potential of the control end, reduce the degree of ion polarization inside the driving module, reduce the threshold voltage of the driving module, adjust the bias state of the threshold voltage of the driving module, and thus improve the problems of low brightness and poor brightness uniformity in the first frame.

[0053] On the other hand, since the target signal line V1 provides the first periodic signal, when adjusting the threshold voltage of the drive module, the voltage signal of any voltage value in the first periodic signal or a combination of multiple voltage signals of different voltage values ​​can be selected to adjust the threshold voltage of the drive module, thereby flexibly meeting the adjustment requirements of the threshold voltage of the drive module under different circumstances.

[0054] Figure 3 This schematically illustrates a first-order periodic signal. For example, such as Figure 3 As shown, when adjusting the threshold voltage of the drive module, for example, the voltage signal of the first voltage value v1 in the first periodic signal can be selected to adjust the threshold voltage of the drive module, or the voltage signal of the second voltage value v2 in the first periodic signal can be selected to adjust the threshold voltage of the drive module. Alternatively, the threshold voltage of the drive module can be adjusted multiple times by combining the voltage signals of the first voltage value v1 and the second voltage value v2, thereby flexibly meeting the adjustment requirements of the threshold voltage of the drive module under different circumstances.

[0055] In some examples, both the first voltage value v1 and the second voltage value v2 can be greater than 0V, i.e., both are positive voltage values. In other examples, both the first voltage value v1 and the second voltage value v2 can be less than 0V, i.e., both are negative voltage values. In still other examples, the first voltage value v1 can be greater than 0V, and the second voltage value v2 can be less than 0V, i.e., the first voltage value v1 is a positive voltage value, and the second voltage value v2 is a negative voltage value. In yet another example, the first voltage value v1 can be less than 0V, and the second voltage value v2 can be greater than 0V, i.e., the first voltage value v1 is a negative voltage value, and the second voltage value v2 is a positive voltage value. This application does not limit the specific examples in this regard.

[0056] Figure 4 This is a timing diagram illustrating the first periodic signal during the first and second bias compensation stages. (Combined with...) Figure 2 and Figure 4As shown, according to some embodiments of this application, optionally, one light emission cycle of the pixel circuit 20 may include at least one first bias compensation stage t1 and at least one second bias compensation stage t2. During both the first bias compensation stage t1 and the second bias compensation stage t2, the bias compensation module 202 can be turned on, and the first periodic signal of the target signal line V1 is transmitted via the bias compensation module 202 to the first terminal a or the second terminal b of the driving module 201 to adjust the bias state of the threshold voltage of the driving module.

[0057] The first periodic signal has different polarities and / or amplitudes in the first bias compensation stage t1 and the second bias compensation stage t2. For example, in the first bias compensation stage t1, the voltage value of the first periodic signal can be a first voltage value v1. The first periodic signal with the first voltage value v1 is transmitted to the first terminal a or the second terminal b of the drive module 201 via the bias compensation module 202 to adjust the bias state of the threshold voltage of the drive module. For example, in the second bias compensation stage t2, the voltage value of the first periodic signal can be a second voltage value v2. The first periodic signal with the second voltage value v2 is transmitted to the first terminal a or the second terminal b of the drive module 201 via the bias compensation module 202 to adjust the bias state of the threshold voltage of the drive module.

[0058] The first voltage value v1 and the second voltage value v2 can be different, that is, their amplitudes are different. For example, the first voltage value v1 can be greater than the second voltage value v2, or the first voltage value v1 can be less than the second voltage value v2.

[0059] The polarities of the first voltage value v1 and the second voltage value v2 can be the same or opposite. For example, both the first voltage value v1 and the second voltage value v2 can be greater than 0V. For example, the first voltage value v1 can be greater than 0V and the second voltage value v2 can be less than 0V. For example, the first voltage value v1 can be less than 0V and the second voltage value v2 can be greater than 0V. The embodiments of this application do not limit this.

[0060] Thus, in different bias compensation stages, the threshold voltage of the drive module can be adjusted by using a combination of voltage signals with different polarities and / or amplitudes in the first periodic signal. That is, by repeatedly applying voltages of different potentials to the first or second terminal of the drive module, it is beneficial to restore the characteristics of the drive module. At the same time, the second terminal of the drive module can be flexibly adjusted to the desired potential, realizing the dynamic adjustment of the potential of the second terminal of the drive module, thereby flexibly meeting the adjustment requirements of the threshold voltage of the drive module.

[0061] Figure 5 This is another timing diagram of the first periodic signal during the first and second bias compensation stages. (Combined with...) Figure 2 and Figure 5 As shown, according to some other embodiments of this application, optionally, the polarity of the first periodic signal can be the same in the first bias compensation stage t1 and the second bias compensation stage t2. For example, in the first bias compensation stage t1, the voltage value of the first periodic signal can be a third voltage value v3, and the first periodic signal with the third voltage value v3 is transmitted to the first terminal a or the second terminal b of the driving module 201 via the bias compensation module 202 to adjust the bias state of the threshold voltage of the driving module. For example, in the second bias compensation stage t2, the voltage value of the first periodic signal can be a fourth voltage value v4, and the first periodic signal with the fourth voltage value v4 is transmitted to the first terminal a or the second terminal b of the driving module 201 via the bias compensation module 202 to adjust the bias state of the threshold voltage of the driving module.

[0062] In this configuration, the third voltage value v3 and the fourth voltage value v4 have the same polarity. For example, both the third voltage value v3 and the fourth voltage value v4 can be greater than 0V, meaning both are positive voltage values. Alternatively, both the third voltage value v3 and the fourth voltage value v4 can be less than 0V, meaning both are negative voltage values.

[0063] It should be noted that the magnitudes of the third voltage value v3 and the fourth voltage value v4 can be the same or different. When the magnitudes of the third voltage value v3 and the fourth voltage value v4 are different, the third voltage value v3 can be greater than the fourth voltage value v4, or the third voltage value v3 can be less than the fourth voltage value v4.

[0064] Thus, by using voltage signals of the same polarity in the first periodic signal to adjust the threshold voltage of the driving module multiple times during the multiple bias compensation stages in a light emission cycle, the threshold voltage of the driving module can be adjusted to the ideal state, which can effectively improve the problems of low brightness and poor brightness uniformity in the first frame.

[0065] Figure 6 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 6 As shown, according to some embodiments of this application, optionally, the display panel where the pixel circuit 20 is located may include a light emission control signal line EM and a scan control signal line Scan. The light emission control signal line EM can be used to transmit light emission control signals. The scan control signal line Scan can be used to transmit scan control signals. The target signal line V1 may multiplex the scan control signal line Scan or the light emission control signal line EM that is not from the pixel circuit itself.

[0066] Specifically, for example, a row of pixel circuits 20 can be connected to a scan control signal line Scan and a light emission control signal line EM. For any i-th row of pixel circuits, the target signal line V1 connected to the i-th row of pixel circuits can reuse the scan control signal line Scan connected to the i-th row of pixel circuits, or the target signal line V1 connected to the i-th row of pixel circuits can reuse the light emission control signal line EM connected to other row of pixel circuits besides the i-th row of pixel circuits, where i is a positive integer.

[0067] Since both the light emission control signal and the scan control signal are pulse signals, such as periodic signals, multiplexing the scan control signal line Scan or the light emission control signal line EM (not from the pixel circuit itself) as the target signal line V1 allows the first periodic signal to be transmitted to either the first terminal a of the driving module 201 or the second terminal b of the driving module 101, thereby adjusting the bias state of the threshold voltage of the driving module 201. Furthermore, because the target signal line V1 multiplexes the scan control signal line Scan or the light emission control signal line EM (not from the pixel circuit itself), the number of signal lines in the display panel can be reduced, which is beneficial for wiring design and reduces production costs.

[0068] Figure 7 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 6 and Figure 7 As shown, according to some embodiments of this application, optionally, in the first bias compensation stage t1, the bias compensation module 202 can be turned on under the control of the first control signal line K1, and transmit the first level light emission control signal of the light emission control signal line EM or the first level scan signal of the scan control signal line Scan to the first terminal a or the second terminal b of the drive module 201, so as to adjust the bias state of the threshold voltage of the drive module 201. Figure 7 The illustration is based on the first level being high, but the first level can also be low.

[0069] In the second bias compensation stage t2, the bias compensation module 202 can be turned on under the control of the first control signal line K1, transmitting the first level or the second level light emission control signal of the light emission control signal line EM to the first terminal a or the second terminal b of the driving module 201, or transmitting the first level or the second level scan signal of the scan control signal line Scan to the first terminal a or the second terminal b of the driving module 201, so as to adjust the bias state of the threshold voltage of the driving module 201.

[0070] It should be noted that, Figure 7The example is given with the first level being high and the second level being low. However, it can be understood that the first level can also be low and the second level can also be high.

[0071] Figure 8 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 8 As shown, according to some embodiments of this application, optionally, for example, when the target signal line V1 reuses the light emission control signal line EM which is not its own pixel circuit, the first control signal line K1 can reuse the scan control signal line Scan. Figure 9 for Figure 8 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 8 and Figure 9 As shown, for any i-th row pixel circuit, the i-th row pixel circuit can be connected to the corresponding light emission control signal line EM(i), the target signal line V1 connected to the i-th row pixel circuit can reuse the light emission control signal lines EM(i±k) connected to other row pixel circuits except the i-th row pixel circuit, and the first control signal line K1 connected to the i-th row pixel circuit can reuse the scan control signal line Scan(i) connected to the i-th row pixel circuit, where i is a positive integer.

[0072] In the first bias compensation stage t1, the bias compensation module 202 in the i-th row pixel circuit can be turned on under the control of the scan control signal line Scan(i), transmitting the first level of the light emission control signal line EM(i±k) to the first terminal a or the second terminal b of the driving module 201, so as to adjust the bias state of the threshold voltage of the driving module 201. In the second bias compensation stage t2, the bias compensation module 202 in the i-th row pixel circuit can be turned on under the control of the scan control signal line Scan(i), transmitting the first level or the second level of the light emission control signal line EM(i±k) to the first terminal a or the second terminal b of the driving module 201, so as to adjust the bias state of the threshold voltage of the driving module 201.

[0073] Figure 10 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 10 As shown, according to some embodiments of this application, optionally, the control terminal of the drive module 201 can be electrically connected to the first node N1, the first terminal of the drive module 201 can be electrically connected to the second node N2, and the second terminal of the drive module 201 can be electrically connected to the third node N3.

[0074] The pixel circuit 20 may also include a first reset module 203. The control terminal of the first reset module 203 is electrically connected to the first scan control signal line S1, the first terminal of the first reset module 203 is electrically connected to the first reference voltage signal line vref1, and the second terminal of the first reset module 203 is electrically connected to the first node N1.

[0075] The first control signal line K1 can reuse the first scan control signal line S1. That is, the first reset module 203 and the bias compensation module 202 can be simultaneously turned on under the control of the first scan control signal line S1. When the first reset module 203 is turned on, the first reference voltage signal of the first reference voltage signal line vref1 is transmitted to the first node N1 through the first reset module 203 to reset the first node N1. When the bias compensation module 202 is turned on, the first periodic signal is transmitted to the first terminal a or the second terminal b of the drive module 201 through the bias compensation module 202 to adjust the bias state of the threshold voltage of the drive module.

[0076] Figure 11 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 11 As shown, according to some embodiments of this application, optionally, the pixel circuit 20 may further include a data writing module 204, the control terminal of the data writing module 204 being electrically connected to the second scan control signal line S2, the first terminal of the data writing module 204 being electrically connected to the data signal line data, and the second terminal of the data writing module 204 being electrically connected to the first terminal of the drive module 201.

[0077] Figure 12 for Figure 11 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 11 and Figure 12 As shown, one light-emitting cycle of the pixel circuit 20 may also include a first data writing stage t3 and a second data writing stage t4. During the first data writing stage t3 and the second data writing stage t4, the data writing module 204 is turned on under the control of the second scan control signal line S2, and writes the data signal of the data signal line to the first end of the driving module 201, thereby realizing the data signal writing.

[0078] In the same light emission cycle, the first data writing stage t3 can be located between the first bias compensation stage t1 and the second bias compensation stage t2, and the second bias compensation stage t2 is located between the first data writing stage t3 and the second data writing stage t4.

[0079] During the first bias compensation phase t1 and the second bias compensation phase t2, the first reset module 203 can be turned on under the control of the first scan control signal line S1, and the first reference voltage signal can be transmitted to the first node N1 through the first reset module 203 to reset the first node N1. During the first bias compensation phase t1 and the second bias compensation phase t2, the bias compensation module 202 can be turned on under the control of the first scan control signal line S1, and the first periodic signal can be transmitted to the first terminal a or the second terminal b of the drive module 201 through the bias compensation module 202 to adjust the bias state of the threshold voltage of the drive module. During the first data writing phase t3 and the second data writing phase t4, the data writing module 204 can be turned on under the control of the second scan control signal line S2 to write the data signal of the data signal line to the first terminal of the drive module 201, realizing the data signal writing.

[0080] Thus, by alternately resetting and writing data signals to the first node N1 during one light emission cycle, the potential of the first node N1 can be ensured to reach the expected potential. Furthermore, by alternately adjusting the bias state of the threshold voltage of the driving module and writing data signals during one light emission cycle, the threshold voltage of the driving module can be ensured to be adjusted to the ideal state.

[0081] Figure 13 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 13 As shown, according to some embodiments of this application, optionally, the first control signal line K1 may not reuse other signal lines, but may be an additional signal line. The target signal line V1 may reuse either the first scan control signal line S1 or the second scan control signal line S2.

[0082] Figure 14 for Figure 13 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 13 and Figure 14 As shown, on the one hand, since the first control signal line K1 is an additional signal line, the control of the bias compensation module 202 is more flexible. That is, the time for adjusting the bias state of the threshold voltage of the driving module is no longer affected and limited by the reset of the first node N1, which can better ensure that the threshold voltage of the driving module can be adjusted to the ideal state. On the other hand, the target signal line V1 reuses the first scan control signal line S1 or the second scan control signal line S2, which reduces the number of signal lines, lowers the output requirements of the driving chip, and is beneficial to the wiring design of the display panel.

[0083] The inventors of this application further realized that when the target signal line V1 reuses the second scan control signal line S2, if the bias compensation module 201 and the data writing module 204 are turned on at the same time, the second node N2 will simultaneously receive the second scan control signal provided by the second scan control signal line S2 and the data signal provided by the data signal line data. Consequently, the second scan control signal may affect the writing process of the data signal, causing the light-emitting element to fail to achieve the expected brightness.

[0084] Continue to combine Figure 13 and Figure 14 As shown, according to some embodiments of this application, optionally, during at least one data writing stage, both the bias compensation module 201 and the data writing module 204 can be turned on. When the target signal line V1 multiplexes the second scan control signal line S2, the voltage value of the second scan control signal provided by the second scan control signal line S2 can be the same as the voltage value of the data signal provided by the data signal line data.

[0085] In this way, since the voltage value of the second scan control signal provided by the second scan control signal line S2 is the same as the voltage value of the data signal provided by the data signal line data, even if the bias compensation module 201 and the data writing module 204 are turned on at the same time, the second scan control signal will not affect the writing process of the data signal, so that the potential of the first node N1 can reach the expected potential, thereby enabling the light-emitting element to reach the expected brightness.

[0086] Figure 15 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 15 As shown, according to some embodiments of this application, similarly, the first control signal line K1 may not reuse other signal lines, but may be an additional signal line. The target signal line V1 may reuse the light-emitting control signal line EM, which is not part of the pixel circuit itself.

[0087] Thus, on the one hand, since the first control signal line K1 is an additional signal line, the control of the bias compensation module 202 is more flexible. That is, the time for adjusting the bias state of the threshold voltage of the driving module is no longer affected and limited by the reset of the first node N1, which can better ensure that the threshold voltage of the driving module can be adjusted to the ideal state. On the other hand, the target signal line V1 reuses the light emission control signal line EM, which is not from the pixel circuit itself, reducing the number of signal lines, lowering the output requirements of the driving chip, and benefiting the wiring design of the display panel.

[0088] As mentioned above, the target signal line V1 can reuse the light emission control signal line EM, which is not part of the pixel circuit itself. Optionally, according to some embodiments of this application, the signal period of the light emission control signal line EM can be the same as the signal period of the first scan control signal line S1 and / or the second scan control signal line S2.

[0089] Figure 16 This is a schematic diagram illustrating the driving timing of a pixel circuit provided in an embodiment of this application. Figure 16 As shown, for example, suppose the interval between the start time of the enable level of the first scan control signal line S1(1) connected to the first row pixel circuit 20 and the start time of the enable level of the target signal line V1 (such as the light emission control signal line EM(1±k)) connected to the first row pixel circuit 20 is x1, and the interval between the start time of the enable level of the second scan control signal line S2(1) connected to the first row pixel circuit 20 and the start time of the enable level of the target signal line V1 (such as the light emission control signal line EM(1±k)) connected to the first row pixel circuit 20 is x2. Therefore, the interval between the start time of the enable level of the first scan control signal line S1(n) connected to the nth row pixel circuit 20 and the start time of the enable level of the target signal line V1 (such as the light emission control signal line EM(n±k)) connected to the nth row pixel circuit 20 is also x1, and / or the interval between the start time of the enable level of the second scan control signal line S2(n) connected to the nth row pixel circuit 20 and the start time of the enable level of the target signal line V1 (such as the light emission control signal line EM(n±k)) connected to the nth row pixel circuit 20 is also x2.

[0090] Thus, since the signal period of the light emission control signal line EM can be the same as the signal period of the first scan control signal line S1 and / or the second scan control signal line S2, it is convenient to adjust the phase difference and achieve consistent adjustment of the threshold voltage bias state of the driving modules of all rows of pixel circuits.

[0091] Figure 17 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 17As shown, according to some embodiments of this application, optionally, the driving module 201 may include a first transistor T1, the bias compensation module 202 may include a second transistor T2, the first reset module 203 may include a third transistor T3, and the data writing module 204 may include a fourth transistor T4. The pixel circuit 20 may also include a threshold compensation module 205, a second reset module 206, a first light emission control module 207, a second light emission control module 208, and a storage capacitor Cst. The threshold compensation module 205 may include a fifth transistor T5, the second reset module 206 may include a sixth transistor T6, the first light emission control module 207 may include a seventh transistor T7, and the second light emission control module 208 may include an eighth transistor T8. In some examples, at least one of the third transistor T3 and the fifth transistor T5 may be a dual-gate transistor to reduce the leakage current of the first node N1.

[0092] The gate of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the second node N2, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0093] The gate of the second transistor T2 is electrically connected to the first control signal line K1, the first terminal of the second transistor T2 is electrically connected to the target signal line V1, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the first transistor T1 or the second terminal of the first transistor T1.

[0094] The gate of the third transistor T3 is electrically connected to the first scan control signal line S1, the first terminal of the third transistor T3 is electrically connected to the first reference voltage signal line vref1, and the second terminal of the third transistor T3 is electrically connected to the first node N1.

[0095] The gate of the fourth transistor T4 is electrically connected to the second scan control signal line S2, the first terminal of the fourth transistor T4 is electrically connected to the data signal line data, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the first transistor T1.

[0096] The gate of the fifth transistor T5 is electrically connected to the third scan control signal line S3, the first terminal of the fifth transistor T5 is electrically connected to the first node N1, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3.

[0097] The gate of the sixth transistor T6 is electrically connected to the fourth scan control signal line S4, the first electrode of the sixth transistor T6 is electrically connected to the second reference voltage signal line vref2, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting element D.

[0098] The gate of the seventh transistor T7 is electrically connected to the light-emitting control signal line EM, the first terminal of the seventh transistor T7 is electrically connected to the first power supply voltage signal line PVDD, and the second terminal of the seventh transistor T7 is electrically connected to the second node N2.

[0099] The gate of the eighth transistor T8 is electrically connected to the light-emitting control signal line EM, the first electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the light-emitting element D.

[0100] The first plate of the storage capacitor Cst is electrically connected to the first power supply voltage signal line PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1. The second electrode of the light-emitting element D is electrically connected to the second power supply voltage signal line PVEE. The first electrode of the light-emitting element D can be the anode of the light-emitting element D, and the second electrode of the light-emitting element D can be the cathode of the light-emitting element D.

[0101] like Figure 17 As shown, in some embodiments, each transistor in the pixel circuit 20 (i.e., the first transistor T1 to the eighth transistor T8) can be a transistor of the same conductivity type, such as a P-type transistor. In this case, the second scan control signal line S2, the third scan control signal line S3, and the fourth scan control signal line S4 can be multiplexed, thereby reducing the number of signal lines and simplifying the wiring design.

[0102] Furthermore, when the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all transistors of the same conductivity type, such as all being P-type transistors, the first control signal line K1 can be an additional signal line. The first control signal line K1 can also reuse the first scan control signal line S1 or the second scan control signal line S2. Correspondingly, the target signal line V1 can be an additional signal line. The target signal line V1 can also reuse the first scan control signal line S1, the second scan control signal line S2, or the light-emitting control signal line EM (not from the pixel circuit itself).

[0103] In some embodiments, the first reference voltage signal line vref1 and the second reference voltage signal line vref2 may provide reference voltage signals with the same voltage value or reference voltage signals with different voltage values. This application embodiment does not limit this.

[0104] Figure 18 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 18 As shown, with Figure 17Unlike the illustrated embodiment, according to other embodiments of this application, optionally, the first reset module 203 and the threshold compensation module 205 can be N-type transistors, that is, the third transistor T3 and the fifth transistor T5 are N-type transistors, thereby reducing the leakage current of the first node N1 and ensuring that the light-emitting element can emit light stably.

[0105] Figure 19 for Figure 18 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 18 and Figure 19 As shown, according to some embodiments of this application, optionally, the third transistor T3 and the fifth transistor T5 are N-type transistors, and the fourth transistor T4 and the sixth transistor T6 are P-type transistors. Furthermore, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors. The second transistor T2 can be either an N-type transistor or a P-type transistor, as will be explained below. The first scan control signal line S1, the second scan control signal line S2, and the third scan control signal line S3 are different scan control signal lines. The fourth scan control signal line S4 can be multiplexed with the second scan control signal line S2.

[0106] In some embodiments, the bias compensation module 202 can also be an N-type transistor, i.e., the second transistor T2 is an N-type transistor. Correspondingly, the first control signal line K1 can be an additional signal line, and the first control signal line K1 can also reuse the first scan control signal line S1 or the third scan control signal line S3. Correspondingly, the target signal line V1 can be an additional signal line, and the target signal line V1 can also reuse the first scan control signal line S1, the second scan control signal line S2, the third scan control signal line S3, or the light emission control signal line EM that is not part of the pixel circuit itself.

[0107] In some embodiments, the bias compensation module 202 can also be a P-type transistor, i.e., the second transistor T2 is a P-type transistor. Correspondingly, the first control signal line K1 can be an additional signal line, and the first control signal line K1 can also reuse the second scan control signal line S2. Correspondingly, the target signal line V1 can be an additional signal line, and the target signal line V1 can also reuse the first scan control signal line S1, the second scan control signal line S2, the third scan control signal line S3, or the light emission control signal line EM that is not part of the pixel circuit itself.

[0108] See Figure 19Taking an example where the second transistor T2, the third transistor T3, and the fifth transistor T5 are all N-type transistors, and the other transistors are all P-type transistors, the first control signal line K1 can, for example, multiplex the first scan control signal line S1. During the first bias compensation stage t1 and the second bias compensation stage t2, the first scan control signal line S1 can provide a high level. The first reset module 203 (i.e., the third transistor T3) can be turned on under the control of the first scan control signal line S1, and the first reference voltage signal can be transmitted to the first node N1 through the first reset module 203 to reset the first node N1. During the first bias compensation stage t1 and the second bias compensation stage t2, the bias compensation module 202 (i.e., the second transistor T2) can be turned on under the control of the first scan control signal line S1. The first periodic signal is transmitted via the second transistor T2 to the first terminal or the second terminal of the first transistor T1 to adjust the bias state of the threshold voltage of the first transistor T1. During the first data writing stage t3 and the second data writing stage t4, the second scan control signal line S2 provides a low level and the third scan control signal line S3 provides a high level. The data writing module 204 (i.e., the fourth transistor T4) can be turned on under the control of the second scan control signal line S2, and the threshold compensation module 205 (i.e., the fifth transistor T5) is turned on under the control of the third scan control signal line S3, thereby realizing the data signal writing and the threshold voltage compensation of the first transistor T1.

[0109] Thus, in one light-emitting cycle, by alternately resetting and writing data signals to the first node N1, the potential of the first node N1 can be ensured to reach the expected potential. Furthermore, in one light-emitting cycle, by alternately adjusting the bias state of the threshold voltage of the first transistor T1 and writing data signals, the threshold voltage of the first transistor T1 can be ensured to be adjusted to the ideal state.

[0110] It should be noted that when the first control signal line K1 multiplexes the third scan control signal line S3, the bias compensation module 202 (i.e. the second transistor T2) can be turned on in the first data writing stage t3 and the second data writing stage t4. The first periodic signal is transmitted to the first terminal or the second terminal of the first transistor T1 via the second transistor T2 to adjust the bias state of the threshold voltage of the first transistor T1.

[0111] When the first control signal line K1 does not reuse the first scan control signal line S1 or the third scan control signal line S3, the bias compensation module 202 (i.e. the second transistor T2) can also be turned on in other stages to adjust the bias state of the threshold voltage of the first transistor T1. This application embodiment does not limit this.

[0112] Based on the pixel circuit 20 provided in the above embodiments, correspondingly, this application also provides a display panel. Figure 20 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 20 As shown, the display panel 100 provided in this embodiment may include multiple rows of pixel circuits, and each row of pixel circuits may include pixel circuits 20 as provided in the above embodiment.

[0113] The display panel 100 provided in this application embodiment has the following characteristics: On the one hand, the bias compensation module can transmit the first periodic signal of the target signal line to the first end or the second end of the driving module, improve the potential difference between the potential of the second end of the driving module and the potential of the control end, reduce the degree of ion polarization inside the driving module, reduce the threshold voltage of the driving module, and adjust the bias state of the threshold voltage of the driving module; on the other hand, since the target signal line provides the first periodic signal, when adjusting the threshold voltage of the driving module, any voltage value of the first periodic signal or a combination of multiple voltage values ​​can be selected to adjust the threshold voltage of the driving module, thereby flexibly meeting the adjustment requirements of the threshold voltage of the driving module under different circumstances.

[0114] Figure 21 This is another structural schematic diagram of the display panel provided in an embodiment of this application. For example... Figure 21 As shown, according to some embodiments of this application, optionally, the display panel 100 may include M rows of pixel circuits 20 and N light-emitting control signal lines EM. Each light-emitting control signal line EM corresponds to one row of pixel circuits 20, and the light-emitting control signal lines EM can be connected to the light-emitting control module (such as...) in the pixel circuits 20. Figure 17 The first light-emitting control module 207 and the second light-emitting control module 208 shown in the figure can optionally have a light-emitting control signal line EM electrically connected to both the first light-emitting control module 207 and the second light-emitting control module 208. N≥M and N and M are both positive integers.

[0115] Combination Figure 17 and Figure 21 As shown, for any i-th row pixel circuit 20 in the M-row pixel circuits 20, the target signal line V1 connected to the bias compensation module 202 in the i-th row pixel circuit 20 can reuse the light emission control signal line EM connected to the corresponding pixel circuit j in the j-th row pixel circuit 20. Here, i ≠ j, 1 ≤ i ≤ M, 1 ≤ j ≤ M, and i and j are both integers. The j-th row pixel circuit 20 and the i-th row pixel circuit 20 are not in the same row; the j-th row pixel circuit 20 can be located before or after the i-th row pixel circuit 20. That is, the aforementioned target signal line V1 reuses the light emission control signal line EM of a pixel circuit that is not itself.

[0116] Combination Figure 16 As shown, from the perspective of driving timing, when the target signal line V1 multiplexes the light emission control signal line EM which is not its own pixel circuit, the bias state of the threshold voltage of the driving module can be adjusted by either the positive voltage in the light emission control signal, the negative voltage in the light emission control signal, or a combination of the positive and negative voltages in the light emission control signal. This allows for flexible adjustment of the threshold voltage of the driving module under different conditions.

[0117] According to some embodiments of this application, optionally, the j-th row pixel circuit and the i-th row pixel circuit can be separated by k rows of pixel circuits, where k ≥ 1 and is an integer. That is, for the i-th row pixel circuit, the target signal line V1 connected to the bias compensation module 202 in the i-th row pixel circuit can reuse the light emission control signal line EM(i±k). Here, the light emission control signal line EM(i±k) is the light emission control signal line EM connected to the light emission control module in the j-th row pixel circuit 20.

[0118] See also Figure 21 According to some embodiments of this application, k can optionally be equal to 1, that is, the bias compensation module 202 in the i-th row pixel circuit can be electrically connected to the light emission control signal line EM corresponding to the previous or next row pixel circuit.

[0119] Figure 22 This is another schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 22 As shown, according to some other embodiments of this application, k may optionally be greater than 1. Figure 22 The diagram uses k=2 as an example, but k can also be greater than 2. That is, the bias compensation module 202 in the i-th row pixel circuit can be electrically connected to the light emission control signal line EM corresponding to the k-th row or the k-th row pixel circuit.

[0120] According to some embodiments of this application, optionally, the display panel 100 may include a first edge B1 and a second edge B2. Figure 21 In the illustrated embodiment, the first edge B1 of the display panel can be the upper edge of the display panel, and the second edge B2 of the display panel can be the lower edge of the display panel. Figure 21 As shown, in a first direction Y1 pointing from the first edge B1 to the second edge B2 of the display panel, the pixel circuits 20 in rows 1 to M are arranged sequentially, and the pixel circuit 20 in row j can be located on the side of the pixel circuit 20 in row i closer to the first edge B1. That is, in some specific examples, the bias compensation module 202 in the pixel circuit in row i can be electrically connected to the light emission control signal line EM(ik) corresponding to the pixel circuit in row k above.

[0121] In this way, by reusing the light emission control signal line EM(ik) corresponding to the upper k-row pixel circuit as the target signal line V1, the number of signal lines in the display panel is reduced, the wiring design is simplified, and the production cost is reduced.

[0122] Figure 23 This is another schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 23 As shown, according to some other embodiments of this application, optionally, in Figure 23 In the illustrated embodiment, the first edge B1 of the display panel can be the lower edge of the display panel, and the second edge B2 of the display panel can be the upper edge of the display panel. The j-th row pixel circuit 20 can be located on the side of the i-th row pixel circuit 20 closer to the lower edge of the display panel. That is, in some specific examples, the bias compensation module 202 in the i-th row pixel circuit can be electrically connected to the light emission control signal line EM(i+k) corresponding to the k-th row pixel circuit.

[0123] In this way, by reusing the light emission control signal line EM(i+k) corresponding to the lower k-row pixel circuit as the target signal line V1, the number of signal lines in the display panel is reduced, the wiring design is simplified, and the production cost is reduced.

[0124] The inventors of this application further realized that if the target signal line V1 reuses the light emission control signal line EM(i+k) corresponding to the lower k rows of pixel circuits, then the last k rows of pixel circuits need to have k additional light emission control signal lines EM to provide the first periodic signal required by the bias compensation module 202 for the last k rows of pixel circuits. Similarly, if the target signal line V1 reuses the light emission control signal line EM(ik) corresponding to the upper k rows of pixel circuits, then the first k rows of pixel circuits need to have k additional light emission control signal lines EM to provide the first periodic signal required by the bias compensation module 202 for the first k rows of pixel circuits.

[0125] See also Figure 21 Specifically, according to some embodiments of this application, optionally, N ≥ M + k. That is, the number of light-emitting control signal lines EM is greater than the number of rows of pixel circuits. The light-emitting control signal lines EM can extend along the second direction X and point along the first edge B1 of the display panel to the second edge B2 in the first direction Y1, with the first light-emitting control signal line EM to the Nth light-emitting control signal line EM arranged sequentially. The first direction Y1 intersects the second direction X.

[0126] Among them, at least k light-emitting control signal lines EM near the first edge B1 of the display panel are not connected to the light-emitting control module (such as the pixel circuit 20) in the pixel circuit 20. Figure 17The first light-emitting control module 207 and the second light-emitting control module 208 shown are electrically connected, and at least k light-emitting control signal lines EM can be separately added light-emitting control signal lines EM.

[0127] Each row of pixel circuits 20 from row (k+1) to row M can be electrically connected to the light-emitting control signal line EM(ik) corresponding to the k-th row of pixel circuits. Pixel circuits 20 from row 1 to row k are electrically connected to k light-emitting control signal lines EM located near the first edge B1 of the display panel. Specifically, each row of pixel circuits 20 is electrically connected to one light-emitting control signal line EM.

[0128] For example, the first to the kth light emission control signal lines EM, located near the first edge B1 of the display panel, are arranged sequentially along the first direction Y1. The bias compensation module in the first row pixel circuit 20 can be electrically connected to the first light emission control signal line EM, the bias compensation module in the second row pixel circuit 20 can be electrically connected to the second light emission control signal line EM, and so on, the bias compensation module in the kth row pixel circuit 20 can be electrically connected to the kth light emission control signal line EM.

[0129] Thus, by adding at least k light-emitting control signal lines EM to provide the first periodic signal required by the bias compensation module for the first k rows of pixel circuits, it can be ensured that the bias state of the threshold voltage of the driving module in the first k rows of pixel circuits can be adjusted, thus ensuring the display uniformity of the display panel.

[0130] See also Figure 23 Specifically, according to some embodiments of this application, optionally, the first edge B1 of the display panel can be the lower edge of the display panel, and the second edge B2 of the display panel can be the upper edge of the display panel. At least k light-emitting control signal lines EM near the lower edge of the display panel are not connected to the light-emitting control module (e.g., in the pixel circuit 20) in the pixel circuit 20. Figure 17 The first light-emitting control module 207 and the second light-emitting control module 208 shown are electrically connected, and at least k light-emitting control signal lines EM can be separately added light-emitting control signal lines EM.

[0131] Each row of pixel circuits 20 from row 1 to row Mk-1 can be electrically connected to the light emission control signal line EM(i+k) corresponding to the kth row of pixel circuits below. Pixel circuits 20 from row Mk to row M are respectively electrically connected to k light emission control signal lines EM near the lower edge of the display panel. Specifically, each row of pixel circuits 20 is electrically connected to one light emission control signal line EM.

[0132] For example, the k-th light emission control signal line EM to the 1st light emission control signal line EM, located near the bottom edge of the display panel, are arranged sequentially along a first direction Y1 from the top edge to the bottom edge of the display panel. The offset compensation module in the M-th row pixel circuit 20 can be electrically connected to the 1st light emission control signal line EM, the offset compensation module in the (M-1)-th row pixel circuit 20 can be electrically connected to the 2nd light emission control signal line EM, and so on, until the offset compensation module in the Mk-th row pixel circuit 20 can be electrically connected to the k-th light emission control signal line EM.

[0133] In this way, by adding at least k light emission control signal lines EM to provide the first periodic signal required by the bias compensation module for the last k rows of pixel circuits, it can be ensured that the bias state of the threshold voltage of the driving module in the last k rows of pixel circuits can be adjusted, thus ensuring the display uniformity of the display panel.

[0134] The inventors of this application further realized that, since the at least k additional light emission control signal lines EM are not electrically connected to the light emission control module in the pixel circuit 20, while the other light emission control signal lines EM are electrically connected to the light emission control module in the pixel circuit 20, the load of the at least k additional light emission control signal lines EM is different from the load of the other light emission control signal lines EM in the display panel. This may lead to different adjustment effects of the threshold voltage bias state of the driving modules in different rows of pixel circuits, resulting in display differences.

[0135] Figure 24 This is another schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 24 As shown, according to some other embodiments of this application, optionally, the display panel 100 may further include an impedance compensation module 23. The impedance compensation module 23 may be electrically connected to at least k light-emitting control signal lines EM near the first edge B1 of the display panel, that is, the impedance compensation module 23 may be electrically connected to the additional at least k light-emitting control signal lines EM to compensate for the load of the additional at least k light-emitting control signal lines EM. Exemplarily, the impedance compensation module 23 includes, but is not limited to, a resistor or a capacitor.

[0136] Thus, by compensating the load of the at least k additional light emission control signal lines EM through the impedance compensation module 23, the difference between the load of the at least k additional light emission control signal lines EM and the load of other light emission control signal lines EM in the display panel can be reduced, thereby making the adjustment effect of the threshold voltage bias state of the driving modules in different row pixel circuits the same or similar, and improving the display effect of the display panel.

[0137] In some embodiments, for the at least k additional light-emitting control signal lines EM, at least one impedance compensation module 23 can be connected to each light-emitting control signal line EM. The impedances of the impedance compensation modules 23 connected to different light-emitting control signal lines EM can be the same, and this embodiment does not limit this.

[0138] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 25 , Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 25 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 25 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 100 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments. These descriptions will not be repeated here.

[0139] It should be understood that the specific circuit structures and top-view structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0140] It should be clarified that the embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0141] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel circuit, characterized in that, include: Driver module; A bias compensation module, wherein the control terminal of the bias compensation module is electrically connected to the first control signal line, the first terminal of the bias compensation module is electrically connected to the target signal line, and the second terminal of the bias compensation module is electrically connected to the first terminal of the drive module or the second terminal of the drive module; The target signal line is electrically connected to the first periodic signal; The pixel circuit also includes: In the first bias compensation stage and the second bias compensation stage, the bias compensation module is turned on. The polarity and / or amplitude of the first periodic signal are different in the first bias compensation phase and the second bias compensation phase.

2. The pixel circuit according to claim 1, characterized in that, Also includes: In the first bias compensation stage and the second bias compensation stage, the bias compensation module is turned on. The first periodic signal has the same polarity in both the first bias compensation phase and the second bias compensation phase.

3. The pixel circuit according to claim 1, characterized in that, Also includes: The target signal line multiplexes the light emission control signal line or the scan control signal line of a non-pixel circuit.

4. The pixel circuit according to claim 1, characterized in that, Also includes: A first reset module, wherein the control terminal of the first reset module is electrically connected to the first scan control signal line, the first terminal of the first reset module is electrically connected to the first reference voltage signal line, the second terminal of the first reset module is electrically connected to the first node, and the first node is electrically connected to the control terminal of the drive module; The first control signal line reuses the first scan control signal line.

5. The pixel circuit according to claim 1, characterized in that, Also includes: In the first bias compensation stage and the second bias compensation stage, the bias compensation module is turned on. The data writing module has its control terminal electrically connected to the second scan control signal line, its first terminal electrically connected to the data signal line, and its second terminal electrically connected to the first terminal of the drive module. In the first data writing stage and the second data writing stage, the data writing module is turned on to write the data signal of the data signal line to the first end of the driving module. The first data writing stage is located between the first bias compensation stage and the second bias compensation stage, and the second bias compensation stage is located between the first data writing stage and the second data writing stage.

6. The pixel circuit according to claim 1, characterized in that, Also includes: A first reset module and a data writing module are provided. The control terminal of the first reset module is electrically connected to the first scan control signal line, the control terminal of the data writing module is electrically connected to the second scan control signal line, the first terminal of the data writing module is electrically connected to the data signal line, and the second terminal of the data writing module is electrically connected to the first terminal of the drive module. The target signal line reuses either the first scan control signal line or the second scan control signal line.

7. The pixel circuit according to claim 6, characterized in that, The target signal line reuses the second scan control signal line; During at least one of the data writing stages, the bias compensation module is turned on, the data writing module is turned on, and the voltage value of the second scan control signal provided by the second scan control signal line is the same as the voltage value of the data signal provided by the data signal line.

8. The pixel circuit according to claim 3, characterized in that, The pixel circuit further includes a first reset module and a data writing module. The control terminal of the first reset module is electrically connected to the first scan control signal line, and the control terminal of the data writing module is electrically connected to the second scan control signal line. The target signal line reuses the light emission control signal line that is not part of the pixel circuit itself; The signal period of the light emission control signal line is the same as the signal period of the first scan control signal line and / or the second scan control signal line.

9. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A first reset module, wherein the control terminal of the first reset module is electrically connected to the first scan control signal line, the first terminal of the first reset module is electrically connected to the first reference voltage signal line, the second terminal of the first reset module is electrically connected to the first node, and the first node is electrically connected to the control terminal of the drive module; A threshold compensation module, wherein the control terminal of the threshold compensation module is electrically connected to the third scan control signal line, the first terminal of the threshold compensation module is electrically connected to the first node, and the second terminal of the threshold compensation module is electrically connected to the second terminal of the drive module; The first reset module and the threshold compensation module both include N-type transistors.

10. The pixel circuit according to claim 9, characterized in that, The bias compensation module includes an N-type transistor, and the first control signal line multiplexes the first scan control signal line or the third scan control signal line.

11. The pixel circuit according to claim 9, characterized in that, The pixel circuit also includes: The data writing module has its control terminal electrically connected to the second scan control signal line, its first terminal electrically connected to the data signal line, and its second terminal electrically connected to the first terminal of the drive module. The bias compensation module and the data writing module both include P-type transistors, and the first control signal line multiplexes the second scan control signal line.

12. A display panel, characterized in that, The display panel includes multiple rows of pixel circuits, and each row of pixel circuits includes the pixel circuits as described in any one of claims 1-11.

13. The display panel according to claim 12, characterized in that, The display panel includes M rows of pixel circuits and N light-emitting control signal lines. One light-emitting control signal line corresponds to one row of pixel circuits. The light-emitting control signal lines are electrically connected to the light-emitting control modules in the pixel circuits. N≥M and both N and M are positive integers. The target signal line connected to the bias compensation module in the i-th row pixel circuit is multiplexed with the light emission control signal line connected to the corresponding pixel circuit in the j-th row, i ≠ j, 1 ≤ i ≤ M, 1 ≤ j ≤ M, and i and j are both integers.

14. The display panel according to claim 13, characterized in that, The j-th row pixel circuit is separated from the i-th row pixel circuit by k rows of pixel circuits, where k ≥ 1 and is an integer.

15. The display panel according to claim 14, characterized in that, Along a first direction from the first edge to the second edge of the display panel, the pixel circuits from the first row to the Mth row are arranged sequentially, and the pixel circuit in the jth row is located on the side of the pixel circuit in the ith row that is closer to the first edge.

16. The display panel according to claim 15, characterized in that, N≥M+k; The light emission control signal line extends along the second direction and points from the first edge of the display panel to the second edge in the first direction. The first light emission control signal line to the Nth light emission control signal line are arranged sequentially, and the first direction intersects the second direction. At least k light emission control signal lines near the first edge of the display panel are not electrically connected to the light emission control module in the pixel circuit; The pixel circuits in rows 1 to 1k are electrically connected to the k light-emitting control signal lines near the second edge of the display panel, or the pixel circuits in rows Mk to M are electrically connected to the k light-emitting control signal lines near the first edge of the display panel, wherein each row of pixel circuits is electrically connected to one light-emitting control signal line.

17. The display panel according to claim 16, characterized in that, The display panel also includes an impedance compensation module, which is electrically connected to at least k light emission control signal lines near the first edge of the display panel.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 12-17.

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