High-speed frequency hopping microsystem and implementation method thereof
By integrating multi-chip microsystems and combining three-level frequency hopping, the miniaturization and high integration issues of UAV communication equipment are solved, achieving high-speed broadband frequency hopping with high flexibility and scalability, supporting a variety of application requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING RES INST OF TELEMETRY
- Filing Date
- 2024-03-04
- Publication Date
- 2026-06-12
Smart Images
Figure CN118157710B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and specifically to a high-speed frequency hopping microsystem and its implementation method. Background Technology
[0002] With the rapid development of communication technology and the continuous expansion of application demands, the number and bandwidth of modern communication devices are constantly expanding, leading to increasingly complex electromagnetic environments for these devices. Against this backdrop, frequency-hopping communication has gained attention due to its advantages such as resistance to tracking interference, anti-interception capabilities, and resistance to narrowband interference, and is widely used, especially in functions such as UAV data links.
[0003] In frequency hopping communication, increasing the frequency hopping rate can effectively improve the anti-interference capability of the communication system. On the other hand, the demand for miniaturization and lightweighting of communication equipment on UAVs has become increasingly prominent in recent years, thus requiring a high-speed frequency hopping solution that can achieve miniaturization and high integration.
[0004] Traditional frequency hopping communication schemes can be divided into digital baseband frequency hopping and radio frequency front-end frequency hopping. Digital baseband frequency hopping completes digital mixing and frequency hopping during digital baseband processing. Its advantage lies in its fast digital processing speed and high frequency hopping rate. However, since it can only hop within the baseband bandwidth, its frequency hopping bandwidth is relatively narrow. Radio frequency front-end frequency hopping, on the other hand, achieves frequency hopping by changing the parameters of the radio frequency synthesizer. This method is limited by the phase-locked time of the frequency synthesizer, resulting in a lower frequency hopping rate, but a wider frequency hopping bandwidth. Using multiple frequency synthesizers for switching can effectively improve the frequency hopping rate of the radio frequency front-end, but it will significantly increase the complexity and size of the radio frequency source, which is not conducive to miniaturization and integration.
[0005] In addition, multi-chip microsystem integration technology can effectively improve system integration and miniaturization capabilities. However, since the hardware solution and interface are fixed after integration and cannot be modified again, a trade-off must be made between the integration level of the solution and the flexibility and universality of the application. Summary of the Invention
[0006] This invention addresses the challenge of miniaturized integration in high-speed frequency hopping by providing a high-speed frequency hopping microsystem and its implementation method. It achieves miniaturized integration of the frequency hopping link through a multi-chip microsystem integration scheme. The combined application of three-stage frequency hopping combines the advantages of digital baseband frequency hopping and RF front-end frequency hopping, achieving high-speed broadband frequency hopping with low power consumption and high integration density. Furthermore, this solution avoids simply integrating multiple frequency synthesizers on a single RF transceiver channel, preventing wasted hardware resources and improving the feasibility of miniaturized microsystem integration. The microsystem solution of this invention can simultaneously support high-speed frequency hopping across 4 transmit and 4 receive RF channels. The high-speed frequency hopping requirements of most applications can be met through first-stage digital baseband frequency hopping and second-stage PLL frequency switching. When the hopping speed requirement is further increased, the hopping speed can be increased by switching the local oscillator signal source during second-stage frequency hopping and switching the RF channel during third-stage frequency hopping. It can be flexibly combined into 3 transmit / receive, 2 transmit / receive, and 1 transmit / receive, achieving a balance between multi-channel selection flexibility, high hopping speed, and high-density integration.
[0007] This invention provides a high-speed frequency hopping microsystem, including a programmable information processing circuit and a radio frequency transceiver circuit electrically connected to each other, a radio frequency switch connected to the radio frequency transceiver circuit, and a DDR3 memory and a solid-state memory respectively connected to the programmable information processing circuit; the number of radio frequency transceiver circuits is two and arranged in parallel, and each radio frequency transceiver circuit is connected to the programmable information processing circuit at one end and to the radio frequency switch at the other end.
[0008] The programmable information processing circuit can perform frequency hopping processing of baseband data stream. The radio frequency transceiver circuit includes a radio frequency receiving channel and a transmitting channel, and both the radio frequency receiving channel and the transmitting channel include a mixer and a PLL. The PLL generates a local oscillator signal and outputs it to the mixer. The radio frequency switch can switch between any one of the two radio frequency transceiver circuits and connect it to the outside. The programmable information processing circuit is connected to the DDR3 memory through the DDR3 interface. When the frequency hopping application is working, the DDR3 memory caches the program and data. The solid-state memory stores the pre-written frequency hopping software program and outputs it to the programmable information processing circuit.
[0009] The programmable information processing circuit can perform the first-level frequency hopping through baseband digital frequency hopping during data processing. The radio frequency transceiver circuit can perform the second-level frequency hopping by switching the local oscillator signal source in the radio frequency receiving channel and the transmitting channel. The radio frequency switch can complete the third-level frequency hopping by switching the selected radio frequency transceiver circuit.
[0010] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the programmable information processing circuit includes an electrically connected programmable logic circuit and a processor circuit. The programmable logic circuit is connected to two radio frequency transceiver circuits through a control interface and a data interface, respectively. The processor circuit is connected to a DDR3 memory through a DDR3 interface and to a solid-state memory through a program configuration interface.
[0011] The programmable logic circuit performs frequency hopping processing of the baseband data stream and controls the RF switch to switch on and off. The processor circuit generates instructions to change the configuration status of the RF transceiver circuit parameters and outputs them to the RF transceiver circuit through the programmable logic circuit. The configuration status of the RF transceiver circuit parameters includes the frequency point of the PLL and the connection relationship of the PLL. When the programmable logic circuit is working, the processor circuit caches the program and data through DDR3 memory, receives the frequency hopping software program through solid-state memory and outputs it to the programmable logic circuit.
[0012] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the radio frequency transceiver circuit includes at least two radio frequency receiving channels and two transmitting channels.
[0013] In the RF transceiver circuit, some ports of one RF receiving channel and one RF transmitting channel are connected to the outside via an RF switch, while the remaining RF receiving channels and RF transmitting channels are directly connected to the outside. Under the control of the programmable information processing circuit, the RF switch selects one RF receiving channel and one RF transmitting channel from the two RF receiving channels and two RF transmitting channels of the two RF transceiver circuits to connect to the outside.
[0014] The bottom substrate of the high-speed frequency hopping microsystem uses ABF organic material, the top is a Cu heat sink, and the lead-out terminals adopt BGA form. The radio frequency and digital signals leading out to the outside of the high-speed frequency hopping microsystem are all led out through BGA solder balls.
[0015] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the radio frequency transceiver circuit includes three radio frequency receiving channels and three transmitting channels.
[0016] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the radio frequency transceiver circuit includes a control interface module and a data interface module connected to a programmable information processing circuit, and a digital front-end module, an ADC / DAC, a filter, a first amplifier, a mixer, a PLL, a switch, and a second amplifier and a receive / output port connected to the mixer in sequence. Each radio frequency receive channel and transmit channel includes a digital front-end module, an ADC or DAC, a filter, a first amplifier, a mixer, a PLL, and a second amplifier.
[0017] The control interface module receives instructions from the programmable information processing circuit to change the configuration status of the RF transceiver circuit parameters, while the data interface module communicates with the programmable information processing circuit to transmit and receive baseband data streams.
[0018] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the radio frequency transceiver circuit includes a radio frequency receiving channel 1 and a radio frequency receiving channel 2 that can operate simultaneously and independently. The radio frequency receiving channel 1 is connected to receiving port A, and the radio frequency receiving channel 2 is connected to receiving ports B and C. Both receiving ports B and C are connected to a second amplifier and then to a second mixer. Both radio frequency receiving channels 1 and 2 are connected to a first switch.
[0019] The radio frequency signal of the radio frequency receiving channel 1 is input from the receiving port A, and passes through the second amplifier, the first mixer, the first amplifier, the filter, the ADC, and the digital front-end module in sequence to connect to the data interface module. The first mixer is connected to the first PLL. The first PLL generates the local oscillator signal of the radio frequency receiving channel 1 and mixes it with the input signal from the receiving port A at the first mixer before outputting it to the first amplifier.
[0020] The radio frequency signal of the radio frequency receiving channel 2 can be selected from receiving port B or receiving port C as an input and sequentially passed through the second amplifier, the second mixer, the first amplifier, the filter, the ADC, and the digital front-end module to connect to the data interface module. The first switch is connected to the first PLL, the second PLL, and the second mixer. At the second mixer, the first switch can be used to select one of the first PLL and the second PLL as the local oscillator signal of the receiving channel 2 and mixed with the input signal from receiving port B or receiving port C before being output to the first amplifier.
[0021] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, the radio frequency transceiver circuit includes a transmit channel 1 and a transmit channel 2 that can operate simultaneously and independently. Transmit channel 1 is connected to transmit port A, and transmit channel 2 is connected to both transmit ports B and C. Both transmit channel 1 and transmit channel 2 are connected to a second switch. A second amplifier is connected to the front end of both transmit ports B and C, and both second amplifiers are connected to a fourth mixer.
[0022] The radio frequency signal of transmission channel 1 is input from the data interface module, and passes through the digital front-end module, DAC, filter, first amplifier, third mixer, and second amplifier in sequence before being output to transmission port A; the third PLL is connected to the third mixer, and the third PLL generates the local oscillator signal of transmission channel 1 and mixes it with the signal output from the first amplifier at the third mixer before being output to the second amplifier and transmission port A in sequence.
[0023] The radio frequency signal of the radio frequency receiving channel 2 is received from the data interface module, and then passes through the digital front-end module, DAC, filter, first amplifier, fourth mixer, and second amplifier in sequence before being output to the transmitting port B or transmitting port C. At the fourth mixer, the second switch can be used to select one of the third PLL and the fourth PLL as the local oscillator signal of the transmitting channel 2, which is then mixed with the transmitting signal output from the first amplifier and output to the second amplifier.
[0024] This invention provides a method for implementing a high-speed frequency hopping microsystem. When only the first-level frequency hopping is performed, the first-level digital baseband frequency hopping is performed in the programmable logic circuit of the programmable information processing circuit, and the data after the first frequency hopping is sent to the data interface module of the radio frequency transceiver circuit. The radio frequency transceiver circuit performs digital-to-analog conversion / analog-to-digital conversion, filtering, amplification, and transmission and reception of the data after the first frequency hopping.
[0025] When the frequency hopping point is outside the current bandwidth coverage and a second-level frequency hopping is required, the data interface module of the RF transceiver circuit is paused from receiving or transmitting. The programmable information processing circuit sends instructions through the control interface to configure the frequency of the PLL in the RF receiving channel or the PLL in the transmitting channel of the receiving RF transceiver circuit. After the frequency and phase locking are completed, the data interface module is enabled to receive or transmit, and the RF transceiver circuit performs a second-level frequency hopping through the PLL.
[0026] The combination of the first-level frequency hopping and the second-level frequency hopping is calculated in advance and the control program is obtained, which is stored in solid-state memory;
[0027] A first PLL is connected in the RF receiving channel 1 of the RF transceiver circuit, and a second PLL is connected in the RF receiving channel 2. The first PLL is connected to the first mixer of the RF receiving channel 1. A first switch is connected between the first PLL, the second PLL and the second mixer of the RF receiving channel 2, so that the second mixer can use the local oscillator signals of the first PLL and the second PLL.
[0028] A third PLL is connected in the transmit channel 1 of the RF transceiver circuit, and a fourth PLL is connected in the transmit channel 2. The third PLL is connected to the third mixer in the transmit channel 1. A second switch is connected between the third PLL, the fourth PLL and the fourth mixer in the transmit channel 2, so that the fourth mixer can use the local oscillator signals of the third PLL and the fourth PLL.
[0029] The single PLL control method for the second-level frequency hopping is as follows: RF receiving channel 1 uses the frequency output by the first PLL for mixing, RF receiving channel 2 uses the frequency output by the second PLL for mixing, transmitting channel 1 uses the frequency output by the third PLL for mixing, and transmitting channel 2 uses the frequency output by the fourth PLL for mixing; the second-level frequency hopping is controlled by switching the frequencies of the first PLL and / or the second PLL and / or the third PLL and / or the fourth PLL.
[0030] The second-level frequency hopping dual PLL ping-pong frequency hopping control method includes the following steps:
[0031] S101. In the initial state, the fourth mixer selects the fourth PLL as the local oscillator signal through the second switch and enters the normal working state. At this time, if only the first stage frequency hopping is required, normal transmission and reception can be achieved without any impact.
[0032] S102. Based on the frequency hopping spectrum design, the frequency point P1 of the next second-level frequency hopping can be determined in advance. The programmable information processing circuit sends control commands through the control interface module to configure the third PLL as frequency point P1.
[0033] S103. When frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch to make the third PLL provide local oscillator for the fourth mixer, hop the frequency to frequency point P1, and then open the data interface.
[0034] S104, The programmable information processing circuit sends a control command to configure the fourth PLL as the frequency point P2 for the next second-level frequency hopping;
[0035] S105. When frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch to make the fourth PLL provide local oscillator for the fourth mixer, hop the frequency to frequency point P2, and then open the data interface.
[0036] S106, Continue to switch between using the third PLL and the fourth PLL to provide the local oscillator signal.
[0037] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, two radio frequency transceiver circuits, both connected to a radio frequency switch, are radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2. During the third-level frequency hopping, the four PLLs of radio frequency transceiver circuits D1 and D2 are used in a cyclic switching manner to provide the local oscillator signal.
[0038] The control method for the third-level frequency hopping includes the following steps:
[0039] S201. In the initial state, the RF switch selects the transmit port C of the RF transceiver circuit D1 as the RF transmit signal, and the RF transceiver circuit D1 internally selects the fourth PLL as the local oscillator signal.
[0040] S202. According to the frequency hopping spectrum design, the frequency points P1, P2 and P3 of subsequent RF signal frequency hopping can be determined in advance. The programmable information processing circuit sends control commands through the control interface module to allocate and configure the third PLL of the RF transceiver circuit D1 transmission channel, the fourth PLL and the third PLL203 of the RF transceiver circuit D2 transmission channel as frequency points P1, P2 and P3.
[0041] S203. Close the data interface, switch the second switch of the RF transceiver circuit D1 to the third PLL, and then open the data interface module to connect with the programmable information processing circuit and complete the frequency hopping to frequency point P1.
[0042] S204. The programmable information processing circuit sends a control command to configure the fourth PLL of the radio frequency transceiver circuit D1 to frequency point P4.
[0043] S205. Close the data interface. The programmable information processing circuit controls the switching RF switch to select the RF transceiver circuit D2 as the RF transmission signal and opens the data interface of the RF transceiver circuit D2. At this time, the RF transceiver circuit D2 uses the fourth PLL as the local oscillator to complete the frequency hopping to frequency point P2.
[0044] S206. The programmable information processing circuit sends a control command to configure the third PLL of the radio frequency transceiver circuit D1 to frequency point P5, and at the same time switches the second switch of the radio frequency transceiver circuit D1 to the fourth PLL.
[0045] S207. Close the data interface, switch the second switch of the RF transceiver circuit D2 to the third PLL, and then open the data interface to complete the frequency hopping to frequency point P3.
[0046] S208, the programmable information processing circuit sends a control command to configure the fourth PLL of the radio frequency transceiver circuit D2 to frequency point P6;
[0047] S209. Close the data interface of the RF transceiver circuit D2. The programmable information processing circuit controls the switching RF switch to select the RF transceiver circuit D1 as the RF transmission signal. Open the data interface of the RF transceiver circuit D1. At this time, the RF transceiver circuit D1 uses the fourth PLL as the local oscillator to complete the frequency hopping to frequency point P4.
[0048] S210, the programmable information processing circuit sends a control command to configure the third PLL of the radio frequency transceiver circuit D2 to frequency point P7, and at the same time switches the second switch of the radio frequency transceiver circuit D2 to the fourth PLL.
[0049] In a preferred embodiment of the high-speed frequency hopping microsystem described in this invention, two radio frequency transceiver circuits, both connected to a radio frequency switch, are radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2, and the four PLLs of radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2 are used in a cyclic switching manner to provide the local oscillator signal.
[0050] The control method for the third-level frequency hopping includes the following steps:
[0051] S301. In the initial state, the RF switch selects the transmit port C of the RF transceiver circuit D1 as the RF transmit signal. At this time, the RF transceiver circuit D1 internally selects the fourth PLL as the local oscillator signal.
[0052] S302. According to the frequency hopping spectrum design, the frequency points P1, P2 and P3 of subsequent RF signal frequency hopping can be determined in advance. The programmable information processing circuit sends control commands through the control interface module to allocate and configure the fourth PLL of RF transceiver circuit D2, the third PLL of RF transceiver circuit D1 and the third PLL of RF transceiver circuit D2 as frequency points P1, P2 and P3.
[0053] S303. Close the data interface of the RF transceiver circuit D1. The programmable information processing circuit controls the switching of the RF switch to select the RF transceiver circuit D2 as the RF transmission signal. Open the data interface of the RF transceiver circuit D2. At this time, the RF transceiver circuit D2 uses the fourth PLL as the local oscillator to complete the frequency hopping to frequency point P1.
[0054] S304. The programmable information processing circuit sends a control command to configure the fourth PLL of the radio frequency transceiver circuit D1 to frequency point P4, and at the same time switches the second switch of the radio frequency transceiver circuit D1 to the third PLL.
[0055] S305. Close the data interface of the RF transceiver circuit D2. The programmable information processing circuit controls the switching of the RF switch to select the RF transceiver circuit D1 as the RF transmission signal. Open the data interface of the RF transceiver circuit D1. At this time, the RF transceiver circuit D1 uses the third PLL as the local oscillator to complete the frequency hopping to frequency point P2.
[0056] S306. The programmable information processing circuit sends a control command to configure the fourth PLL of the radio frequency transceiver circuit D2 to frequency point P5, and at the same time switches the second switch of the radio frequency transceiver circuit D2 to the third PLL.
[0057] S307. Close the data interface of RF transceiver circuit D1. The programmable information processing circuit controls the switching of RF switch to select RF transceiver circuit D2 as the RF transmission signal. Open the data interface of RF transceiver circuit D2. At this time, the third PLL is used as the local oscillator inside RF transceiver circuit D2 to complete the frequency hopping to frequency point P3.
[0058] S308, the programmable information processing circuit sends a control command to configure the third PLL of the radio frequency transceiver circuit D1 to frequency point P6, and at the same time switches the second switch of the radio frequency transceiver circuit D1 to the fourth PLL.
[0059] S309. Close the data interface of the RF transceiver circuit D2. The programmable information processing circuit controls the switching of the RF switch to select the RF transceiver circuit D1 as the RF transmission signal. Open the data interface of the RF transceiver circuit D1. At this time, the RF transceiver circuit D1 uses the fourth PLL as the local oscillator to complete the frequency hopping to frequency point P4.
[0060] The present invention has the following advantages:
[0061] (1) The high-speed frequency hopping microsystem and its implementation method proposed in this invention can realize digital processing and radio frequency transceiver functions for applications such as networking data links on the same chip-level hardware platform. It can support up to 4 radio frequency receiving and 4 radio frequency transmitting channels working simultaneously, thus supporting multiple concurrent applications and possessing high flexibility and scalability.
[0062] (2) The high-speed frequency hopping microsystem proposed in this invention has three-level frequency hopping capability. It can realize frequency hopping applications of different frequency bands and different hopping speeds as needed through different frequency hopping combinations, and can support high-speed frequency hopping applications of the entire radio frequency band. Attached Figure Description
[0063] Figure 1 This is a block diagram of a high-speed frequency-hopping microsystem.
[0064] Figure 2 This is a block diagram of the internal implementation of the radio frequency transceiver circuit of a high-speed frequency hopping microsystem.
[0065] Figure 3 This is a schematic diagram showing the connection relationship between the radio frequency transceiver circuit and the initial state radio frequency switch of a high-speed frequency hopping microsystem.
[0066] Figure 4 Here is a flowchart of an embodiment 2 of a method for implementing a high-speed frequency hopping microsystem;
[0067] Figure 5 Flowchart of Embodiment 3 for a method of implementing a high-speed frequency hopping microsystem;
[0068] Figure 6 Flowchart of Example 4 for implementing a high-speed frequency hopping microsystem.
[0069] Figure label:
[0070] 100. Programmable information processing circuit; 101. Programmable logic circuit; 102. Processor circuit; 200. Radio frequency transceiver circuit; 201. First phase-locked loop; 202. Second phase-locked loop; 203. Third phase-locked loop; 204. Fourth phase-locked loop; 205. Radio frequency switch; 206. First mixer; 207. Second mixer; 208. Third mixer; 209. First switch; 210. Second switch; 300. Initial state radio frequency switch; 400. DDR3 memory; 500. Solid state memory. Detailed Implementation
[0071] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1
[0072] like Figures 1-4 As shown, a high-speed frequency hopping microsystem and its implementation method are disclosed. The high-speed frequency hopping microsystem includes: a programmable information processing circuit 100, two radio frequency transceiver circuits 200, a radio frequency switch 300, a DDR3 memory 400, and a solid-state memory 500.
[0073] The programmable information processing circuit includes a programmable logic circuit 101 and a processor circuit 102. The programmable logic circuit 101 has an external control interface and a data interface, both of which are connected to the radio frequency transceiver circuit 200. The data interface transmits and receives baseband data streams with the transceiver circuit 200, and the corresponding baseband data streams are processed within the programmable logic circuit 101. The control interface is used to send configuration commands to the radio frequency transceiver circuit 200 and change its internal parameter configuration status.
[0074] The processor circuit 102 is connected to the DDR3 memory 400 through a DDR3 interface. When the frequency hopping application is working, the DDR3 memory 400 is used to cache programs and data when the microsystem is working. The processor circuit 102 is connected to the solid-state memory 500 through a program configuration interface. The solid-state memory 500 is used to store the pre-written frequency hopping software program.
[0075] Each RF transceiver circuit 200 has 3 RF receive channels and 3 RF transmit channels, wherein one RF receive channel and one transmit channel are connected to an RF switch 300; the RF switch 300 selects one transmit / receive channel from the two transmit / receive channels from the two RF transceiver circuits 200 and connects it to the outside of the microsystem.
[0076] The bottom substrate of the microsystem is made of ABF organic material, the top is a Cu heat sink, and the lead-out terminals are in BGA form. The radio frequency and digital signals led out to the outside of the microsystem are all led out through BGA solder balls.
[0077] The configuration instructions for the radio frequency transceiver circuit 200 by the programmable information processing circuit 100 are generated by the processor circuit 102, sent by the processor circuit 102 to the programmable logic circuit 101, and then forwarded to the control interface.
[0078] The processor circuit 102 also includes an Ethernet interface, which can receive external configuration information via Ethernet. The configuration information includes modifications to the configuration parameters of the radio frequency transceiver circuit 200 and changes to the information stored in the solid-state memory 500.
[0079] The radio frequency transceiver circuit 200 includes: a control interface module, a data interface module, a digital front-end module, an ADC / DAC, a filter, an amplifier, a mixer, a PLL, and switches, etc.; wherein the control interface module is used to receive configuration commands from the programmable information processing circuit 100, and the data interface module is used to communicate with the programmable information processing circuit 100 to transmit and receive baseband data streams.
[0080] The radio frequency transceiver circuit 200 includes: a radio frequency receiving channel 1, a receiving channel 2, a transmitting channel 1, and a transmitting channel 2, which can operate simultaneously and independently.
[0081] The radio frequency signal of the radio frequency receiving channel 1 is input from the receiving port A, and passes through the amplifier, the first mixer 205, the amplifier, the filter, the ADC, and the digital front-end module in sequence to connect to the data interface module; the first PLL 201 is used to generate the local oscillator signal of the receiving channel 1, which is mixed with the input signal from the receiving port A at the first mixer 205 and then output to the next stage amplifier.
[0082] The radio frequency signal of the radio frequency receiving channel 2 can be selected from the receiving port B or C as an input, and then passes through the amplifier, the second mixer 206, the amplifier, the filter, the ADC, and the digital front-end module in sequence to connect to the data interface module. At the second mixer 206, the first switch 209 can select one of the first PLL 201 and the second PLL 202 as the local oscillator signal of the receiving channel 2, which is mixed with the input signal from the receiving port B or C, and then output to the next stage amplifier.
[0083] The radio frequency signal of radio frequency transmission channel 1 starts from the data interface module, passes through the digital front-end module, DAC, filter, amplifier, mixer, and amplifier output to the transmission port A in sequence; the third PLL 203 is used to generate the local oscillator signal of transmission channel 1, which is mixed with the transmission signal of this channel at the third mixer 207 and then output to the next stage amplifier.
[0084] The radio frequency signal of the radio frequency receiving channel 2 starts from the data interface module, passes through the digital front-end module, DAC, filter, amplifier, mixer, and amplifier output to the transmitting port B or C in sequence; at the fourth mixer 208, the second switch 210 can select one of the third PLL 203 and the fourth PLL 204 as the local oscillator signal of the transmitting channel 2, mixes it with the transmitting signal of this channel, and then outputs it to the next stage amplifier.
[0085] The radio frequency transceiver circuit 200 includes receiving ports A and B, and transmitting ports A and B, which are directly led out to the outside of the high-speed frequency hopping microsystem as external radio frequency channels; receiving port C and transmitting port C are connected to the radio frequency switch 300.
[0086] For the RF transmitting channel, the RF switch 300 receives the transmitting signals from the transmitting ports C of the two RF transceiver circuits 200 and selects one of them to be transmitted to the outside of the microsystem by switching the switch; for the RF receiving channel, the RF switch 300 receives the RF receiving signals from the outside of the microsystem and selects to be transmitted to the receiving port C of one RF transceiver circuit 200 by switching the switch; the switching of the RF switch 300 is determined by the digital control signal issued by the programmable information processing circuit 100.
[0087] The high-speed frequency hopping microsystem has a three-level frequency hopping capability. The programmable information processing circuit 100 can complete the first-level frequency hopping through baseband digital frequency hopping during data processing. The radio frequency transceiver circuit 200 can complete the second-level frequency hopping by changing the PLL frequency and by switching the local oscillator signal source in the radio frequency receiving channel 2 and transmitting channel 2. The radio frequency switch 300 can complete the third-level frequency hopping by switching the selected radio frequency transceiver circuit 200. Through the combined application of the three-level frequency hopping, the high-speed frequency hopping application requirements covering the entire radio frequency band can be met within the microsystem.
[0088] The block diagram of the high-speed frequency hopping microsystem proposed in this invention is as follows: Figure 1 As shown, after the microsystem is powered on, the processor circuit 102 reads the required program from the solid-state memory 500, stores part of the program and data in the DDR3 memory 400, and loads the programmable logic circuit 101. The processor circuit 102 configures the initial state of the radio frequency transceiver circuit 200 through the control port of the programmable logic circuit 101. After the configuration is completed, the programmable logic circuit 101 starts transmitting and receiving radio frequency signals through the data interface. The frequency hopping spectrum of the frequency hopping signal, that is, the switching order of the frequency hopping points, is stored in the solid-state memory 500 in advance. During the frequency hopping process, the processor circuit 102 reads the frequency hopping spectrum, caches the program in the DDR3 memory, and executes the frequency hopping switching according to the program. After power-on, the processor circuit can receive program and frequency hopping spectrum update requests from the outside through the Ethernet interface and store them in the solid-state memory 500. The updated content will take effect when the microsystem is powered on again.
[0089] The following describes in detail the control and operation mode of the high-speed frequency hopping microsystem during frequency hopping.
[0090] In this embodiment, the four transmit and receive RF channels are used simultaneously for different application functions. Each channel can hop frequencies independently without affecting the others. The receive ports A and B, and the transmit ports A and B of each RF transceiver circuit 200 are connected to corresponding external RF transceiver signals. The frequency hopping control method is as follows:
[0091] If a certain function requires one receive and one transmit channel, and the receive port A and transmit port A of a certain radio frequency transceiver circuit 200 are used respectively, then frequency hopping is implemented through control combination and data interface.
[0092] When the frequency hopping point is within the current bandwidth coverage range, the first stage of digital baseband frequency hopping is completed in the programmable logic circuit 101, and the data is sent to the data interface. At this time, the data interface only needs to maintain data transmission and reception, while the control interface is idle.
[0093] When the frequency hopping point is outside the current bandwidth coverage, first pause the data interface to receive or transmit, and then send a command through the control interface to configure the frequency to receive the first PLL201 or send the third PLL203. After the frequency and phase locking are completed, start the data interface to receive or transmit, thus completing the second-level frequency hopping.
[0094] Based on the designed frequency hopping spectrum and bandwidth, it is easy to calculate whether the frequency point of each frequency hopping is within the current bandwidth coverage range, thereby determining how to combine the first and second level frequency hopping, and storing the control program in the solid-state memory 500 in advance.
[0095] The first-level frequency hopping can achieve a hopping rate of over tens of thousands of hops per second, while the second-level frequency hopping can achieve a large frequency hopping bandwidth across the entire radio frequency band. By combining the two, both high hopping rate and wide bandwidth frequency hopping can be achieved. Example 2
[0096] A high-speed frequency hopping microsystem and its implementation method are disclosed. In embodiment 1, when the second-level frequency hopping is performed, it is necessary to wait for the PLL to lock and the mixer to stabilize. In particular, the PLL lock time is relatively long, possibly on the order of hundreds of microseconds. At this time, it is necessary to wait for a long time to complete the frequency hopping and data transmission and reception. If the designed frequency hopping pattern requires the continuous use of the second-level frequency hopping, the frequency hopping speed will be significantly reduced.
[0097] For the above applications, faster frequency hopping can be achieved by switching the local oscillator signal source during the second-stage frequency hopping. In this case, the two receive channels within one RF transceiver circuit 200 can be combined into one receive channel, using only the receive port B; alternatively, the two transmit channels within one RF transceiver circuit 200 can be combined into one transmit channel, using only the transmit port B, as shown below. Figure 2 As shown;
[0098] like Figure 4 As shown, the control steps for the second-stage frequency hopping will now be described in detail, taking transmission as an example:
[0099] In step S101, the fourth mixer 208 initially selects the fourth PLL 204 as the local oscillator signal through the second switch 210 and enters the normal working state. At this time, if only the first stage frequency hopping is required, normal transmission and reception can be achieved without any impact.
[0100] Step S102: According to the frequency hopping spectrum design, the frequency point P1 of the next second-level frequency hopping can be determined in advance. Therefore, a control command is sent through the control interface to configure the third PLL203 as frequency point P1.
[0101] Step S103: When frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch 210, and use the third PLL 203 to provide local oscillator for the fourth mixer 208, hop the frequency to frequency point P1, and then open the data interface.
[0102] Step S104: Send a control command to configure the fourth PLL204 as the frequency point P2 for the next second-level frequency hopping;
[0103] In step S105, when frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch 210, and use the fourth PLL 204 to provide the local oscillator for the fourth mixer 208, hop the frequency to frequency point P2, and then open the data interface.
[0104] By repeating the above steps, the local oscillator signal can be provided by the third PLL203 and the fourth PLL204. Since after switching the second switch 210, it is only necessary to wait for the mixer signal to stabilize before continuing to transmit and receive data. The waiting time for this operation is usually within ten microseconds, which can greatly improve the frequency hopping rate.
[0105] In this embodiment, if only the two PLLs of one RF transceiver circuit 200 are used in a ping-pong switching configuration, the microsystem can use a total of 3 receive and 3 transmit RF channels; if both RF transceiver circuits 200 use their two PLLs in a ping-pong configuration, the microsystem can use a total of 2 receive and 2 transmit RF channels. Example 3
[0106] In a high-speed frequency hopping microsystem and its implementation method, in embodiment 2, if the second-level frequency hopping is used to switch a frequency point once, it can be completed within ten microseconds; if the designed frequency hopping pattern requires the continuous use of the second-level frequency hopping, it is still necessary to wait for the PLL to lock. For example, between steps S103 and S105 above, it is necessary to wait for the fourth PLL 204 to switch to frequency point P2 and lock in step S104. Therefore, when the second-level frequency hopping needs to be executed continuously, the interval between the two executions cannot be shorter than the PLL locking time on the order of hundreds of microseconds.
[0107] To address the above situation, the third-level frequency hopping can be achieved by using RF switch 300 to switch the selected RF transceiver circuit and channel, such as... Figure 3 As shown.
[0108] In this embodiment, the two radio frequency transceiver circuits 200 are referred to as D1 and D2, respectively, and are connected to the radio frequency switch 300 using the receive or transmit port C.
[0109] like Figure 5 As shown, the control steps for the third-level frequency hopping will now be described in detail, taking transmission as an example:
[0110] In step S201, the RF switch 300 initially selects the transmit port C of D1 as the RF transmit signal, and at this time, the fourth PLL204 is selected as the local oscillator signal inside D1.
[0111] Step S202: Based on the frequency hopping spectrum design, the frequency points P1, P2 and P3 of the subsequent radio frequency signal frequency hopping can be confirmed in advance. A control command is sent to allocate and configure the third PLL203 of D1, the fourth PLL204 and the third PLL203 of D2 as frequency points P1, P2 and P3.
[0112] Step S203: Close the data interface, switch the second switch 210 of D1 to the third PLL 203, and then open the data interface to complete the frequency hopping to frequency point P1;
[0113] Step S204: Send a control command to configure the fourth PLL204 of D1 as frequency point P4;
[0114] Step S205: Close the D1 data interface, the programmable information processing circuit 100 controls the switching RF switch 300 to select D2 as the RF transmission signal, and open the D2 data interface. At this time, the fourth PLL204 is used as the local oscillator inside D2 to complete the frequency hopping to frequency point P2.
[0115] Step S206: Send a control command to configure the third PLL203 of D1 to frequency point P5, and at the same time switch the second switch 210 of D1 to the fourth PLL204.
[0116] Step S207: Close the data interface, switch the second switch 210 of D2 to the third PLL 203, and then open the data interface to complete the frequency hopping to frequency point P3;
[0117] Step S208: Send a control command to configure the fourth PLL204 of D2 to frequency point P6;
[0118] Step S209: Close the D2 data interface, the programmable information processing circuit 100 controls the switching RF switch 300 to select D1 as the RF transmission signal, and open the D1 data interface. At this time, the fourth PLL204 is used as the local oscillator inside D1 to complete the frequency hopping to frequency point P4.
[0119] Step S210: Send a control command to configure the third PLL203 of D2 to frequency point P7, and at the same time switch the second switch 210 of D2 to the fourth PLL204.
[0120] By repeating the above steps, the four PLLs of D1 and D2 can be used to provide the local oscillator signal in a cyclic switching manner. Since this embodiment only needs to wait for the signal to stabilize after switching the second switch 210 or the RF switch 300, the interval between two executions can be shorter than the PLL lock-in time by hundreds of microseconds during continuous frequency hopping, thereby further significantly improving the frequency hopping rate. Example 4
[0121] A high-speed frequency-hopping microsystem and its implementation method, similar to Embodiment 3, such as... Figure 6 As shown, the local oscillator or channel order for frequency hopping can also be changed:
[0122] In step S301, the RF switch 300 initially selects the transmit port C of D1 as the RF transmit signal, and at this time, the fourth PLL204 is selected as the local oscillator signal inside D1.
[0123] Step S302: Based on the frequency hopping spectrum design, the frequency points P1, P2 and P3 of the subsequent radio frequency signal frequency hopping can be confirmed in advance. A control command is sent to allocate and configure the fourth PLL204 of D2, the third PLL203 of D1 and the third PLL203 of D2 as frequency points P1, P2 and P3.
[0124] Step S303: Close the D1 data interface, the programmable information processing circuit 100 controls the switching RF switch 300 to select D2 as the RF transmission signal, and open the D2 data interface. At this time, the fourth PLL204 is used as the local oscillator inside D2 to complete the frequency hopping to frequency point P1.
[0125] Step S304: Send a control command to configure the fourth PLL204 of D1 to frequency point P4, and at the same time switch the second switch 210 of D1 to the third PLL203.
[0126] Step S305: Close the D2 data interface, the programmable information processing circuit 100 controls the switching RF switch 300 to select D1 as the RF transmission signal, and open the D1 data interface. At this time, the third PLL203 inside D1 is used as the local oscillator to complete the frequency hopping to frequency point P2.
[0127] Step S306: Send a control command to configure the fourth PLL204 of D2 to frequency point P5, and at the same time switch the second switch 210 of D2 to the third PLL203.
[0128] Step S307: Close the D1 data interface, the programmable information processing circuit 100 controls the switching RF switch 300 to select D2 as the RF transmission signal, and open the D2 data interface. At this time, the third PLL203 inside D2 is used as the local oscillator to complete the frequency hopping to frequency point P3.
[0129] Step S308: Send a control command to configure the third PLL203 of D1 to frequency point P6, and at the same time switch the second switch 210 of D1 to the fourth PLL204.
[0130] Step S309: Close the D2 data interface. The programmable information processing circuit 100 controls the switching RF switch 300 to select D1 as the RF transmission signal and open the D1 data interface. At this time, the fourth PLL204 is used as the local oscillator inside D1 to complete the frequency hopping to frequency point P4.
[0131] By repeating the above steps, the four PLLs of D1 and D2 can also be used to provide the local oscillator signal in a cyclic switching manner. Unlike embodiment 3, in embodiment 4, the stabilization time of the RF channel frequency hopping depends only on the RF switch 300. Therefore, when the switching stabilization time of the RF switch 300 is shorter than the stabilization time of the second switch 210 in the RF transceiver circuit 200, embodiment 4 has a higher hopping speed. Conversely, embodiment 3 is better.
[0132] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A high speed frequency hopping microsystem, characterized by: The device includes a programmable information processing circuit (100) and a radio frequency transceiver circuit (200) electrically connected to each other, a radio frequency switch (300) connected to the radio frequency transceiver circuit (200), and a DDR3 memory (400) and a solid-state memory (500) respectively connected to the programmable information processing circuit (100); the number of radio frequency transceiver circuits (200) is two and arranged side by side, and each of the two radio frequency transceiver circuits (200) is connected at one end to the programmable information processing circuit (100) and at the other end to the radio frequency switch (300); The programmable information processing circuit (100) can perform frequency hopping processing of baseband data stream. The radio frequency transceiver circuit (200) includes a radio frequency receiving channel and a transmitting channel, and both the radio frequency receiving channel and the transmitting channel include a mixer and a phase-locked loop. The phase-locked loop generates a local oscillator signal and outputs it to the mixer. The radio frequency switch (300) can switch between any one of the two radio frequency transceiver circuits (200) and connect it to the outside. The programmable information processing circuit (100) is connected to the DDR3 memory (400) through a DDR3 interface. When the frequency hopping application is working, the DDR3 memory (400) caches the program and data. The solid-state memory (500) stores the pre-written frequency hopping software program and outputs it to the programmable information processing circuit (100). The programmable information processing circuit (100) can perform the first-level frequency hopping through baseband digital frequency hopping during data processing. The radio frequency transceiver circuit (200) can perform the second-level frequency hopping by switching the local oscillator signal source between the radio frequency receiving channel and the transmitting channel. The radio frequency switch (300) can complete the third-level frequency hopping by switching the selected radio frequency transceiver circuit (200).
2. The high-speed frequency hopping microsystem of claim 1, wherein: The programmable information processing circuit (100) includes a programmable logic circuit (101) and a processor circuit (102) electrically connected. The programmable logic circuit (101) is connected to the two radio frequency transceiver circuits (200) through a control interface and a data interface, respectively. The processor circuit (102) is connected to the DDR3 memory (400) through the DDR3 interface, and the processor circuit (102) is connected to the solid-state memory (500) through a program configuration interface. The programmable logic circuit (101) performs frequency hopping processing of the baseband data stream and controls the RF switch (300) to switch. The processor circuit (102) generates an instruction to change the parameter configuration state of the RF transceiver circuit (200) and outputs it to the RF transceiver circuit (200) through the programmable logic circuit (101). The parameter configuration state of the RF transceiver circuit (200) includes the frequency point of the phase-locked loop and the connection relationship of the phase-locked loop. When the programmable logic circuit (101) is working, the processor circuit (102) caches the program and data through the DDR3 memory (400), receives the frequency hopping software program through the solid-state memory (500), and outputs it to the programmable logic circuit (101).
3. The high-speed frequency hopping microsystem according to claim 1, characterized in that: The radio frequency transceiver circuit (200) includes at least two radio frequency receiving channels and two transmitting channels; In the radio frequency transceiver circuit (200), a portion of one of the radio frequency receiving channels and one of the transmitting channels are connected to the outside via the radio frequency switch (300), while the remaining radio frequency receiving channels and the transmitting channels are directly connected to the outside. Under the control of the programmable information processing circuit (100), the radio frequency switch (300) selects one radio frequency receiving channel and one transmitting channel from the two radio frequency receiving channels and two transmitting channels of the two radio frequency transceiver circuits (200) and connects them to the outside. The bottom substrate of the high-speed frequency hopping microsystem is made of ABF organic material, the top is a Cu heat sink, and the lead-out terminals are in the form of BGA. The radio frequency and digital signals leading out to the outside of the high-speed frequency hopping microsystem are all led out through BGA solder balls.
4. A high-speed frequency-hopping microsystem according to claim 3, characterized in that: The radio frequency transceiver circuit (200) includes three radio frequency receiving channels and three transmitting channels.
5. A high-speed frequency-hopping microsystem according to claim 1, characterized in that: The radio frequency transceiver circuit (200) includes a control interface module and a data interface module connected to the programmable information processing circuit (100), and a digital front-end module, an ADC / DAC, a filter, a first amplifier, a mixer, a phase-locked loop, a switch, and a second amplifier and a receive / output port connected to the mixer in sequence. Each radio frequency receiving channel and each transmitting channel includes the digital front-end module, the ADC or the DAC, the filter, the first amplifier, the mixer, the phase-locked loop, and the second amplifier. The control interface module receives the instruction from the programmable information processing circuit (100) to change the parameter configuration state of the radio frequency transceiver circuit (200), and the data interface module communicates with the programmable information processing circuit (100) to transmit and receive baseband data streams.
6. A high-speed frequency-hopping microsystem according to claim 5, characterized in that: The radio frequency transceiver circuit (200) includes a radio frequency receiving channel 1 and a radio frequency receiving channel 2 that can work independently at the same time. The radio frequency receiving channel 1 is connected to receiving port A, and the radio frequency receiving channel 2 is connected to receiving port B and receiving port C. The receiving port B and the receiving port C are both connected to a second amplifier and then connected to a second mixer (206). The radio frequency receiving channel 1 and the radio frequency receiving channel 2 are both connected to a first switch (209). The radio frequency signal of the radio frequency receiving channel 1 is input from the receiving port A, and passes through the second amplifier, the first mixer (205), the first amplifier, the filter, the ADC, and the digital front-end module in sequence to connect to the data interface module. The first mixer (205) is connected to the first phase-locked loop (201). The first phase-locked loop (201) generates the local oscillator signal of the radio frequency receiving channel 1 and mixes it with the input signal from the receiving port A at the first mixer (205) before outputting it to the first amplifier. The radio frequency signal of the radio frequency receiving channel 2 can be selected from the receiving port B or the receiving port C as an input and sequentially passed through the second amplifier, the second mixer (206), the first amplifier, the filter, the ADC, and the digital front-end module to connect to the data interface module. The first switch (209) is connected to the first phase-locked loop (201), the second phase-locked loop (202), and the second mixer (206). At the second mixer (206), the first switch (209) can select one of the first phase-locked loop (201) and the second phase-locked loop (202) as the local oscillator signal of the receiving channel 2 and mix it with the input signal from the receiving port B or the receiving port C before outputting it to the first amplifier.
7. A high-speed frequency-hopping microsystem according to claim 5, characterized in that: The radio frequency transceiver circuit (200) includes a transmitting channel 1 and a transmitting channel 2 that can work independently at the same time. The transmitting channel 1 is connected to the transmitting port A, and the transmitting channel 2 is connected to the transmitting port B and the transmitting port C. The transmitting channel 1 and the transmitting channel 2 are both connected to the second switch (210). The front end of the transmitting port B and the transmitting port C are both connected to a second amplifier, and the second amplifier is connected to the fourth mixer (208). The radio frequency signal of the transmission channel 1 is input from the data interface module, passes through the digital front-end module, the DAC, the filter, the first amplifier, the third mixer (207), and the second amplifier in sequence, and is output to the transmission port A; the third phase-locked loop (203) is connected to the third mixer (207), and the third phase-locked loop (203) generates the local oscillator signal of the transmission channel 1 and mixes it with the signal output from the first amplifier at the third mixer (207) and outputs it in sequence to the second amplifier and the transmission port A; The transmission signal of the transmission channel 2 is received from the data interface module, and sequentially passes through the digital front-end module, the DAC, the filter, the first amplifier, the fourth mixer (204), and the second amplifier before being output to the transmission port B or the transmission port C. At the fourth mixer (208), the second switch (210) can select one of the third phase-locked loop (203) and the fourth phase-locked loop (204) as the local oscillator signal of the transmission channel 2, and mix it with the transmission signal output from the first amplifier before outputting it to the second amplifier.
8. A method for implementing a high-speed frequency-hopping microsystem according to any one of claims 2 to 7, characterized in that: When only the first-level frequency hopping is performed, the first-level digital baseband frequency hopping is performed in the programmable logic circuit (101) of the programmable information processing circuit (100) and the data after the first frequency hopping is sent to the data interface module of the radio frequency transceiver circuit (200). The radio frequency transceiver circuit (200) performs digital-to-analog conversion / analog-to-digital conversion, filtering, amplification, and transmission and reception of the data after the first frequency hopping. When the frequency hopping point is outside the current bandwidth coverage range and a second-level frequency hopping is required, the data interface module of the radio frequency transceiver circuit (200) is paused from receiving or transmitting. The programmable information processing circuit (100) sends instructions through the control interface to configure the frequency of the phase-locked loop in the radio frequency receiving channel or the phase-locked loop in the transmitting channel of the radio frequency transceiver circuit (200). After the frequency and phase locking are completed, the data interface module is started to receive or transmit. The radio frequency transceiver circuit (200) performs a second-level frequency hopping through the phase-locked loop. The combination of the first-level frequency hopping and the second-level frequency hopping is calculated in advance and a control program is obtained, which is stored in the solid-state memory (500); A first phase-locked loop (201) is connected in the RF receiving channel 1 of the RF transceiver circuit (200), and a second phase-locked loop (202) is connected in the RF receiving channel 2. The first phase-locked loop (201) is connected to the first mixer (205) of the RF receiving channel 1. A first switch (209) is connected between the first phase-locked loop (201), the second phase-locked loop (202), and the second mixer (206) of the RF receiving channel 2, so that the second mixer (206) can use the local oscillator signals of the first phase-locked loop (201) and the second phase-locked loop (202). A third phase-locked loop (203) is connected in the transmit channel 1 of the radio frequency transceiver circuit (200), and a fourth phase-locked loop (204) is connected in the transmit channel 2. The third phase-locked loop (203) is connected to a third mixer (207) in the transmit channel 1. A second switch (210) is connected between the third phase-locked loop (203), the fourth phase-locked loop (204), and the fourth mixer (208) in the transmit channel 2, so that the fourth mixer (208) can use the local oscillator signals of the third phase-locked loop (203) and the fourth phase-locked loop (204). The single-phase-locked loop control method for second-level frequency hopping is as follows: the radio frequency receiving channel 1 uses the frequency output by the first phase-locked loop (201) for mixing, the radio frequency receiving channel 2 uses the frequency output by the second phase-locked loop (202) for mixing, the transmitting channel 1 uses the frequency output by the third phase-locked loop (203) for mixing, and the transmitting channel 2 uses the frequency output by the fourth phase-locked loop (204) for mixing; second-level frequency hopping single-phase-locked loop control is performed by switching the frequencies of the first phase-locked loop (201) and / or the second phase-locked loop (202) and / or the third phase-locked loop (203) and / or the fourth phase-locked loop (204); The second-stage frequency hopping dual phase-locked loop ping-pong frequency hopping control method includes the following steps: S101. In the initial state, the fourth mixer (208) selects the fourth phase-locked loop (204) as the local oscillator signal through the second switch (210) and enters the normal working state. At this time, if only the first stage frequency hopping is required, normal transmission and reception can be achieved without any impact. S102. According to the frequency hopping spectrum design, the frequency point P1 of the next second-level frequency hopping can be determined in advance. The programmable information processing circuit (100) sends a control command through the control interface module to configure the third phase-locked loop (203) as frequency point P1. S103. When frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch (210) so that the third phase-locked loop (203) provides the local oscillator for the fourth mixer (208), hop the frequency to frequency point P1, and then open the data interface. S104, the programmable information processing circuit (100) sends a control command to configure the fourth phase-locked loop (204) as the frequency point P2 for the next second-level frequency hopping; S105. When frequency hopping of the radio frequency channel is required, first close the data interface, then switch the second switch (210) so that the fourth phase-locked loop (204) provides the local oscillator for the fourth mixer (208), hop the frequency to frequency point P2, and then open the data interface. S106. Continue to switch between using the third phase-locked loop (203) and the fourth phase-locked loop (204) to provide the local oscillator signal.
9. The implementation method of a high-speed frequency hopping microsystem according to claim 8, characterized in that: The two radio frequency transceiver circuits (200) that are both connected to the radio frequency switch (300) are radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2, respectively. During the third-level frequency hopping, the four phase-locked loops of radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2 are used in a cyclic switching manner to provide the local oscillator signal. The control method for the third-level frequency hopping includes the following steps: S201. In the initial state, the radio frequency switch (300) selects the transmit port C of the radio frequency transceiver circuit D1 as the radio frequency transmit signal, and the radio frequency transceiver circuit D1 internally selects the fourth phase-locked loop (204) as the local oscillator signal. S202. According to the frequency hopping spectrum design, the frequency points P1, P2 and P3 of subsequent radio frequency signal frequency hopping can be determined in advance. The programmable information processing circuit (100) sends control commands through the control interface module to allocate and configure the third phase-locked loop (203) of the transmitting channel of the radio frequency transceiver circuit D1, the fourth phase-locked loop (204) and the third phase-locked loop (203) of the transmitting channel of the radio frequency transceiver circuit D2 as frequency points P1, P2 and P3. S203. Close the data interface, switch the second switch (210) of the radio frequency transceiver circuit D1 to the third phase-locked loop (203), and then open the data interface module to connect with the programmable information processing circuit (100) and complete the frequency hopping to frequency point P1. S204, the programmable information processing circuit (100) sends a control command to configure the fourth phase-locked loop (204) of the radio frequency transceiver circuit D1 to frequency point P4; S205. Close the data interface. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300) to select the radio frequency transceiver circuit D2 as the radio frequency transmission signal and open the data interface of the radio frequency transceiver circuit D2. At this time, the radio frequency transceiver circuit D2 uses the fourth phase-locked loop (204) as the local oscillator to complete the frequency hopping to frequency point P2. S206. The programmable information processing circuit (100) sends a control command to configure the third phase-locked loop (203) of the radio frequency transceiver circuit D1 to frequency point P5, and at the same time switches the second switch (210) of the radio frequency transceiver circuit D1 to the fourth phase-locked loop (204). S207. Close the data interface, switch the second switch (210) of the radio frequency transceiver circuit D2 to the third phase-locked loop (203), and then open the data interface to complete the frequency hopping to frequency point P3; S208, the programmable information processing circuit (100) sends a control command to configure the fourth phase-locked loop (204) of the radio frequency transceiver circuit D2 to frequency point P6; S209. Close the data interface of the radio frequency transceiver circuit D2. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300) to select the radio frequency transceiver circuit D1 as the radio frequency transmission signal and open the data interface of the radio frequency transceiver circuit D1. At this time, the radio frequency transceiver circuit D1 uses the fourth phase-locked loop (204) as the local oscillator to complete the frequency hopping to frequency point P4. S210, the programmable information processing circuit (100) sends a control command to configure the third phase-locked loop (203) of the radio frequency transceiver circuit D2 to frequency point P7, and at the same time switches the second switch (210) of the radio frequency transceiver circuit D2 to the fourth phase-locked loop (204).
10. The method for implementing a high-speed frequency-hopping microsystem according to claim 8, characterized in that: The two radio frequency transceiver circuits (200) that are both connected to the radio frequency switch (300) are radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2, respectively, and the four phase-locked loops of radio frequency transceiver circuit D1 and radio frequency transceiver circuit D2 are used in a cyclic switching manner to provide local oscillator signals. The control method for the third-level frequency hopping includes the following steps: S301. In the initial state, the RF switch (300) selects the transmit port C of the RF transceiver circuit D1 as the RF transmit signal. At this time, the RF transceiver circuit D1 internally selects the fourth phase-locked loop (204) as the local oscillator signal. S302. According to the frequency hopping spectrum design, the frequency points P1, P2 and P3 of subsequent RF signal frequency hopping can be determined in advance. The programmable information processing circuit (100) sends control commands through the control interface module to allocate and configure the fourth phase-locked loop (204) of the RF transceiver circuit D2, the third phase-locked loop (203) of the RF transceiver circuit D1 and the third phase-locked loop (203) of the RF transceiver circuit D2 as frequency points P1, P2 and P3. S303. Close the data interface of the radio frequency transceiver circuit D1. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300), selects the radio frequency transceiver circuit D2 as the radio frequency transmission signal, and opens the data interface of the radio frequency transceiver circuit D2. At this time, the radio frequency transceiver circuit D2 uses the fourth phase-locked loop (204) as the local oscillator to complete the frequency hopping to frequency point P1. S304. The programmable information processing circuit (100) sends a control command to configure the fourth phase-locked loop (204) of the radio frequency transceiver circuit D1 to frequency point P4, and at the same time switches the second switch (210) of the radio frequency transceiver circuit D1 to the third phase-locked loop (203). S305. Close the data interface of the radio frequency transceiver circuit D2. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300), selects the radio frequency transceiver circuit D1 as the radio frequency transmission signal, and opens the data interface of the radio frequency transceiver circuit D1. At this time, the radio frequency transceiver circuit D1 uses the third phase-locked loop (203) as the local oscillator to complete the frequency hopping to frequency point P2. S306, The programmable information processing circuit (100) sends a control command to configure the fourth phase-locked loop (204) of the radio frequency transceiver circuit D2 to frequency point P5, and at the same time switches the second switch (210) of the radio frequency transceiver circuit D2 to the third phase-locked loop (203). S307. Close the data interface of the radio frequency transceiver circuit D1. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300), selects the radio frequency transceiver circuit D2 as the radio frequency transmission signal, and opens the data interface of the radio frequency transceiver circuit D2. At this time, the radio frequency transceiver circuit D2 uses the third phase-locked loop (203) as the local oscillator to complete the frequency hopping to frequency point P3. S308, the programmable information processing circuit (100) sends a control command to configure the third phase-locked loop (203) of the radio frequency transceiver circuit D1 to frequency point P6, and at the same time switches the second switch (210) of the radio frequency transceiver circuit D1 to the fourth phase-locked loop (204). S309. Close the data interface of the radio frequency transceiver circuit D2. The programmable information processing circuit (100) controls the switching of the radio frequency switch (300), selects the radio frequency transceiver circuit D1 as the radio frequency transmission signal, and opens the data interface of the radio frequency transceiver circuit D1. At this time, the radio frequency transceiver circuit D1 uses the fourth phase-locked loop (204) as the local oscillator to complete the frequency hopping to frequency point P4.