A gate driving method and display panel
By using a lower pre-charge voltage and adjusting the charging time in the driving timing of the LCD panel, the problem of insufficient charging of high-resolution LCD panels was solved, data line power consumption was reduced, and display effect was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TRULY (RENSHOU) HIGH-END DISPLAY TECH LTD
- Filing Date
- 2024-04-19
- Publication Date
- 2026-06-16
AI Technical Summary
Existing LCD panels, when used at high resolutions, suffer from insufficient charging due to short charging times. Traditional 4H pre-charging technology increases power consumption of both the data cable and the display screen.
The pre-charge time is used to output drive timing to the nth row of pixels of the display panel. Pre-charging is performed with a lower first voltage and actual charging is performed with a higher second voltage. The power consumption of the data line is reduced by adjusting the charging time and voltage threshold.
It effectively reduces the power consumption of the data cable during the writing process and improves the display quality.
Smart Images
Figure CN118173068B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to a gate driving method and a display panel. Background Technology
[0002] As the resolution of LCD panels increases, especially with the number of vertical rows increasing, the time allocated to each row of pixels on the LCD panel becomes shorter, meaning the charging time allocated to each pixel becomes shorter. Using traditional pixel structures and driving methods inevitably leads to the problem of insufficient charging.
[0003] The pixel structure of a traditional LCD panel is as follows: Figure 1 As shown, there is only one thin-film transistor (TFT) switch in the pixel. The TFT switch is only turned on when a high-level voltage is input to the scan line connected to it, and the voltage signal on the data line can be input to the pixel electrode. The corresponding charge is stored through the liquid crystal capacitor Clc and the storage capacitor Cs.
[0004] To improve the charging rate, a pre-charging technique is employed. This technique involves initially charging the row pixels with a certain amount of charge, and then charging them with the actual charge only before the gate is turned off, thereby increasing the charging rate.
[0005] like Figure 2 When using 4H pre-charge technology for pixel driving, a 3H pre-charge is performed first, and the final 1H is the actual charging. This means that while charging the nth row of pixels, the data in rows n+1, n+2, and n+3 are also charged, increasing the load on the data lines (RC Loading) and thus increasing the power consumption of the display data lines. Additionally, a prolonged high-level gate drive signal also increases the display's power consumption. Summary of the Invention
[0006] Existing LCD screens require a 4-hour high-level signal during 4-hour pre-charging, which increases the power consumption of the data line.
[0007] To address the aforementioned issues, a gate driving method and display panel are proposed. By pre-charging the nth row of pixels of the display panel with a first voltage that is lower than the actual charging second voltage, the power consumption of the data line during the data writing process can be effectively reduced, thereby improving the display quality.
[0008] In a first aspect, a gate driving method includes:
[0009] Step 100: Provide a display panel, including a control unit and a timing unit, wherein the timing unit is used to output the gate driving timing of the display panel according to the control instructions of the control unit;
[0010] Step 200: Use the timing unit to output driving timing to the nth row of pixels on the display panel:
[0011] Pre-charging is performed using a first voltage, and actual charging is performed using a second voltage;
[0012] Wherein, the first voltage is a voltage value obtained by adding a first voltage threshold to the VGL level voltage;
[0013] The second voltage is the voltage value obtained by adding a second voltage threshold to the first voltage.
[0014] In conjunction with the gate driving method described in the first aspect of the present invention, in a first possible embodiment, step 200 includes:
[0015] Step 201: Precharge with the first voltage at the first H unit time in the driving timing;
[0016] Step 202: Set the voltage pulse to VGL at the second H unit time of the driving timing to stop pre-charging;
[0017] Step 203: Precharge with the first voltage at the third H unit time of the driving sequence;
[0018] Step 204: In the fourth H unit time of the driving sequence, actual charging is performed with the second voltage.
[0019] In conjunction with the gate driving method described in the first aspect of the present invention, in a second possible embodiment, step 200 further includes:
[0020] Step 205: Pre-charge with the first voltage during the first H unit time and the second H unit time of the driving timing.
[0021] Step 206: Set the voltage pulse to VGL level at the third H unit time of the driving sequence to stop pre-charging;
[0022] Step 207: In the fourth H unit time of the driving sequence, actual charging is performed with the second voltage.
[0023] In conjunction with the gate driving method described in the first aspect of the present invention, in a third possible embodiment, step 200 further includes:
[0024] Step 208: Precharge with the first voltage at the first H unit time in the driving timing;
[0025] Step 209: Perform actual charging at the second voltage in the second H unit time of the driving timing.
[0026] In conjunction with the gate driving method described in the first aspect of the present invention, in a fourth possible embodiment, step 200 further includes:
[0027] Step 210: Pre-charge with the first voltage during the first H unit time and the second H unit time of the driving timing.
[0028] Step 220: In the third H unit time of the driving sequence, actual charging is performed with the second voltage.
[0029] In conjunction with the gate driving method described in the first aspect of the present invention, in a fifth possible embodiment, step 200 further includes:
[0030] Step 230: Pre-charge with the first voltage during the first H unit time, the second H unit time, and the third H unit time of the driving timing.
[0031] Step 240: In the fourth H unit time of the driving sequence, actual charging is performed with the second voltage.
[0032] In a second aspect, a display panel employing the gate driving method described in the first aspect includes:
[0033] Control unit and timing unit;
[0034] The timing unit is used to output driving timing to the nth row of pixels according to the instructions of the control unit:
[0035] Pre-charging is performed using a first voltage, and actual charging is performed using a second voltage;
[0036] Wherein, the first voltage is a voltage value obtained by adding a first voltage threshold to the VGL level voltage;
[0037] The second voltage is the voltage value obtained by adding a second voltage threshold to the first voltage.
[0038] In conjunction with the display panel described in the second aspect, in a first possible implementation, the timing unit is further configured to:
[0039] Pre-charged with the first voltage during the first H unit time and the third H unit time of the driving timing;
[0040] During the second H unit time of the driving timing, the voltage pulse is set to the VGL level to stop pre-charging;
[0041] In the fourth H unit time of the driving sequence, actual charging is performed at the second voltage.
[0042] In conjunction with the display panel described in the second aspect, in a first possible implementation, the timing unit is further configured to:
[0043] Pre-charged with the first voltage during the first H unit time and the second H unit time of the driving timing;
[0044] In the third H unit time of the driving sequence, the voltage pulse is set to VGL to stop pre-charging;
[0045] In the fourth H unit time of the driving sequence, actual charging is performed at the second voltage.
[0046] In conjunction with the display panel described in the second aspect, in a second possible implementation, the timing unit is further configured to:
[0047] Pre-charging is performed with the first voltage during the first H unit time, the second H unit time, and the third H unit time of the driving timing sequence;
[0048] In the fourth H unit time of the driving sequence, actual charging is performed at the second voltage.
[0049] By implementing the gate driving method and display panel described in this invention, a first voltage is applied to the nth row of pixels of the display panel for pre-charging by outputting a pre-charging time of the driving timing. This first voltage is smaller than the actual charging second voltage, which can effectively reduce the power consumption of the data line during the data writing process and improve the display quality. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 A schematic diagram of an existing liquid crystal display device;
[0052] Figure 2 This is a schematic diagram of the existing driver timing.
[0053] Figure 3 This is a schematic diagram of the first and second voltages in the driving timing of this invention;
[0054] Figure 4 This is a first schematic diagram of the gate driving method flow in Example 1;
[0055] Figure 5 This is a second schematic diagram of the gate driving method flow in Example 1;
[0056] Figure 6 This is a schematic diagram of the gate drive timing in Example 1;
[0057] Figure 7 This is a schematic diagram of the gate driving method in Example 2;
[0058] Figure 8 This is a schematic diagram of the gate drive timing in Example 2;
[0059] Figure 9 This is a schematic diagram of the gate driving method in Example 3;
[0060] Figure 10 This is a schematic diagram of the gate drive timing in Example 3;
[0061] Figure 11 This is a schematic diagram of the gate driving method in Example 4;
[0062] Figure 12 This is a schematic diagram of the gate drive timing in Example 4;
[0063] Figure 13 This is a schematic diagram of the gate driving method in Example 5;
[0064] Figure 14 This is a schematic diagram of the gate drive timing in Example 5; Detailed Implementation
[0065] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.
[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0067] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0068] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0070] Existing LCD screens require a 4-hour high-level signal during 4-hour pre-charging, which increases the power consumption of the data line.
[0071] To address the above problems, a gate driving method and a display panel are proposed.
[0072] Example 1
[0073] Firstly, a gate driving method, such as Figure 4 , Figure 4 The first schematic diagram of the gate driving method flow in Example 1 includes:
[0074] Step 100: Provide a display panel, including a control unit and a timing unit, wherein the timing unit is used to output the gate driving timing of the display panel according to control instructions; Step 200: Use the timing unit to output driving timing to the nth row of pixels of the display panel: pre-charging with a first voltage and actual charging with a second voltage; wherein the first voltage is a voltage value obtained by adding a first voltage threshold ΔV1 to the VGL level voltage; the second voltage is a voltage value obtained by adding a second voltage threshold ΔV2 to the first voltage, such as... Figure 3 , Figure 3 This is a schematic diagram of the first and second voltages in the driving timing of this invention.
[0075] The second voltage is greater than the first voltage, and the first voltage threshold ΔV1 may be equal to or different from the second voltage threshold ΔV2.
[0076] The second voltage is the voltage during actual charging, while the first voltage is the pre-charging voltage. The first voltage does not need to be equal to the second voltage and can be lower, thereby reducing the power consumption of the data line. By pre-charging the nth row of pixels on the display panel with the disclosed first voltage during the output driving timing, which is smaller than the actual charging second voltage, the power consumption of the data line during data writing can be effectively reduced, improving display quality.
[0077] Preferably, such as Figure 5 , Figure 5 This is a second schematic diagram of the gate driving method flow in Example 1; step 200 includes:
[0078] Step 201: Pre-charge with the first voltage during the first H unit time of the driving sequence; Step 202: Set the voltage pulse to VGL during the second H unit time of the driving sequence and stop pre-charging; Step 203: Pre-charge with the first voltage during the third H unit time of the driving sequence; Step 204: Perform actual charging with the second voltage during the fourth H unit time of the driving sequence, such as... Figure 6 , Figure 6 This is a schematic diagram of the gate drive timing in Example 1.
[0079] In this embodiment, precharging is stopped in the second H unit time, and precharging is only performed in the first H unit time and the third H unit time. Reducing the unit time of precharging can also help reduce power consumption.
[0080] Example 2
[0081] Preferably, such as Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the gate driving method in Example 2. Figure 8 This is a schematic diagram of the gate driving timing in Example 2; Step 200 further includes Step 205, pre-charging with a first voltage during the first H unit time and the second H unit time of the driving timing; Step 206, setting the voltage pulse to VGL during the third H unit time of the driving timing and stopping the pre-charging; Step 207, performing actual charging with a second voltage during the fourth H unit time of the driving timing.
[0082] In this embodiment, precharging is stopped at the third H unit time, and precharging is only performed at the first H unit time and the second H unit time. Reducing the unit time of precharging can also help reduce power consumption.
[0083] Example 3
[0084] Preferably, such as Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of the gate driving method in Example 3. Figure 10 The diagram shows the gate driving timing in Example 3. Step 200 further includes step 208, pre-charging with a first voltage in the first H unit time of the driving timing; and step 209, actual charging with a second voltage in the second H unit time of the driving timing.
[0085] In this embodiment, only one unit time of pre-charging is performed. Reducing the unit time of pre-charging can also help reduce power consumption.
[0086] Example 4
[0087] Preferably, such as Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the gate driving method in Example 4. Figure 12 This is a schematic diagram of the gate driving timing in Example 4; step 200 further includes: step 210, pre-charging with a first voltage during the first H unit time and the second H unit time of the driving timing; step 220, actual charging with a second voltage during the third H unit time of the driving timing.
[0088] In this embodiment, only two H unit time pre-charging is performed. Reducing the unit time of pre-charging can also help reduce power consumption.
[0089] Example 5
[0090] Preferably, such as Figure 13 and Figure 14 , Figure 13 This is a schematic diagram of the gate driving method in Example 5. Figure 14 This is a schematic diagram of the gate driving timing in Embodiment 5; Step 200 further includes: Step 230, pre-charging with a first voltage during the first H unit time, the second H unit time, and the third H unit time of the driving timing; Step 240, actual charging with a second voltage during the fourth H unit time of the driving timing.
[0091] Example 6
[0092] In a second aspect, a display panel employing the gate driving method of the first aspect includes:
[0093] The control unit and timing unit are used to output driving timing to the nth row of pixels according to the instructions of the control unit: pre-charging with a first voltage and actual charging with a second voltage; wherein, the first voltage is a voltage value obtained by adding a first voltage threshold to the VGL level voltage; and the second voltage is a voltage value obtained by adding a second voltage threshold to the first voltage.
[0094] Furthermore, the timing unit is also used to: pre-charge with a first voltage at the first H unit time and the third H unit time of the driving timing; set the voltage pulse to VGL at the second H unit time of the driving timing to stop pre-charging; and perform actual charging with a second voltage at the fourth H unit time of the driving timing.
[0095] Furthermore, timing units are also used for:
[0096] Pre-charging is performed at the first voltage during the first H unit time and the second H unit time of the driving sequence; the voltage pulse is set to VGL during the third H unit time of the driving sequence to stop pre-charging; and actual charging is performed at the second voltage during the fourth H unit time of the driving sequence.
[0097] Furthermore, the timing unit is also used to: pre-charge with a first voltage during the first H unit time, the second H unit time, and the third H unit time of the driving timing; and to actually charge with a second voltage during the fourth H unit time of the driving timing.
[0098] A gate driving method and display panel implementing the present invention precharge the nth row of pixels of the display panel with a first voltage at a pre-charge time of output driving timing. The first voltage is smaller than the second voltage of actual charging, which can effectively reduce the power consumption of the data line during the data writing process and improve the display quality.
[0099] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A gate driving method, characterized in that it includes: Step 100: Provide a display panel, including a control unit and a timing unit, wherein the timing unit is used to output the gate driving timing of the display panel according to the control instructions of the control unit; Step 200: Use the timing unit to output driving timing to the nth row of pixels on the display panel: Pre-charging is performed using a first voltage, and actual charging is performed using a second voltage; Wherein, the first voltage is a voltage value obtained by adding a first voltage threshold to the VGL level voltage; The second voltage is the voltage value obtained by adding a second voltage threshold to the first voltage; Step 200 includes: Step 201: Precharge with the first voltage at the first H unit time in the driving timing; Step 202: Set the voltage pulse to VGL at the second H unit time of the driving timing to stop pre-charging; Step 203: Precharge with the first voltage at the third H unit time of the driving sequence; Step 204: In the fourth H unit time of the driving sequence, actual charging is performed with the second voltage.
2. A display panel employing the gate driving method of claim 1, characterized in that, include: Control unit and timing unit; The timing unit is used to output driving timing to the nth row of pixels according to the instructions of the control unit: Pre-charging is performed using a first voltage, and actual charging is performed using a second voltage; Wherein, the first voltage is a voltage value obtained by adding a first voltage threshold to the VGL level voltage; The second voltage is the voltage value obtained by adding a second voltage threshold to the first voltage.
3. The display panel according to claim 2, characterized in that, The timing unit is also used for: Pre-charged with the first voltage during the first H unit time and the third H unit time of the driving timing; During the second H unit time of the driving timing, the voltage pulse is set to the VGL level to stop pre-charging; In the fourth H unit time of the driving sequence, actual charging is performed at the second voltage.