Gate drive circuit and display device

Abstract

The application discloses a kind of gate drive circuit and display device, gate drive circuit, including cascaded multiple gate drive units, each gate drive unit includes: output end and scanning control block, with first node is connected, according to the first front stage gate signal first node is pulled up to high level, according to the first rear stage gate signal first node is pulled down to low level;Output module, with scanning control block is connected to first node, according to the potential of first node and this stage clock signal in output end outputs the this stage gate signal corresponding to this stage gate drive unit;Pull-down control module, with output end is connected, for according to this stage clock signal to the pull-down control of output end;Stable module, with first node and output end is connected, for when first node is pulled down to low level, first node and output end are maintained to low level.The edge of the gate signal of the application this stage is corresponding with the edge of this stage clock signal, can adjust the duty cycle of gate signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to gate driving circuits and display devices. Background Technology

[0002] Display devices generally include a display panel, a gate driving circuit, and a source driving circuit. The basic working principle of the liquid crystal display panel and driving circuit is as follows: the gate driving circuit sends a gate driving signal to the gate line through a pull-up transistor electrically connected to the gate line, sequentially turning on the MFM (Medium-to-Flatform) transistors in each row. Then, the source driving circuit simultaneously charges all the pixel units in an entire row to their required voltages to display different grayscale levels. Specifically, the gate driving circuit for the first row first turns on the thin-film transistors in the first row through its pull-up transistor, and then the source driving circuit charges the pixel units in the first row. When the pixel units in the first row are fully charged, the gate driving circuit turns off the thin-film transistors in that row. Then, the gate driving circuit for the second row turns on the thin-film transistors in the second row through its pull-up transistor, and the source driving circuit charges and discharges the pixel units in the second row. This process continues until the pixel units in the last row are fully charged, at which point charging begins again from the first row.

[0003] like Figure 1 and Figure 2 As shown, in the existing gate drive circuit, the switching element M10 receives the gate signal from the subsequent stage, thereby controlling the output terminal of the local gate signal to be pulled low. Since this circuit uses 8 CLKs as one cycle, the rising edge of the second subsequent stage gate signal Gn+4 and the falling edge of the local gate signal Gn must be switched simultaneously to match the cascaded subsequent stage gate drive unit output. Therefore, the CLK duty cycle design can only be 50%. When the second subsequent stage gate signal is another gate signal, such as Gn+2 or Gn+3, the duty cycle of the clock signal CLK will also change accordingly, but in the corresponding hardware circuit, the duty cycle of the clock signal CLK cannot be adjusted further.

[0004] Therefore, the pull-down circuit for the third gate signal Gn+x output by the subsequent gate drive unit cannot adjust the duty cycle of CLK. The high-level time of CLK can only be fixed at 2T, 3T, or 4T. Moreover, once the circuit is determined, the duty cycle must be fixed, and it is impossible to use other duty cycle signals, such as 3.5T (43.75%) or other arbitrary duty cycles, on the same circuit. Therefore, it is necessary to provide an improved technical solution to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a gate driving circuit and a display device, thereby solving the above technical problems.

[0006] According to one aspect of the present invention, a gate driving circuit is provided, comprising a plurality of cascaded gate driving units, each gate driving unit comprising: an output terminal and a scan control block connected to a first node, wherein the first node is pulled up to a high level according to a first preceding gate signal and pulled down to a low level according to a first following gate signal; an output module connected to the scan control block and connected to the first node, wherein the output module outputs a gate signal corresponding to the gate driving unit of the current stage according to the potential of the first node and the current stage clock signal; a pull-down control module connected to the output terminal, wherein the output terminal is pulled down according to the current stage clock signal; and a stabilization module connected to the first node and the output terminal, wherein the first node and the output terminal are kept at a low level when the first node is pulled down to a low level.

[0007] Optionally, the scan control block includes:

[0008] A first switching element, wherein the control terminal and the first path terminal of the first switching element receive the first front-end gate signal, and the second path terminal is connected to the first node;

[0009] The second switching element has a control terminal that receives the first subsequent gate signal, a first path terminal that is connected to the first node, and a second path terminal that receives the first reference voltage.

[0010] Optionally, the output module includes a third switching element, the control terminal of which is connected to the first node, the first path terminal receives the local clock signal, and the second path terminal is connected to the output terminal.

[0011] Optionally, the stabilization module includes a fourth, fifth, sixth, seventh, eighth, and ninth switching element. The first path terminal of the fourth switching element is connected to a control terminal and receives a second reference voltage. The second path terminal of the fourth switching element is connected to the first path terminal of the fifth switching element and the control terminal of the sixth switching element. The second path terminal of the fifth switching element receives a first reference voltage, and its control terminal is connected to the first node. The first path terminal of the sixth switching element receives the second reference voltage, and its second path terminal is connected to a second node. The first path terminal of the seventh switching element is connected to the second node, and its second path terminal receives the first reference voltage; its control terminal is connected to the first node. The first path terminal of the eighth switching element is connected to the first node, its second path terminal receives the first reference voltage, and its control terminal is connected to the second node. The first path terminal of the ninth switching element is connected to the output terminal, its second path terminal receives a third reference voltage, and its control terminal is connected to the second node.

[0012] Optionally, each gate driving unit further includes a reset module connected to the first node and the output terminal, used to reset the first node and the output terminal according to a reset control signal. The reset module includes a tenth switching element and an eleventh switching element. The first path terminal of the tenth switching element receives a third reference voltage, the second path terminal is connected to the output terminal, and the control terminal receives the reset control signal. The first path terminal of the eleventh switching element receives a first reference voltage, the second path terminal is connected to the first node, and the control terminal receives the reset control signal.

[0013] Optionally, the pull-down control module includes a twelfth switch element, a thirteenth switch element, and a fourteenth switch element. The first path terminal of the twelfth switch element is connected to the output terminal, the second path terminal of the twelfth switch element receives a third reference voltage, and the control terminal of the twelfth switch element is connected to the second path terminal of the thirteenth switch element and the first path terminal of the fourteenth switch element. The first path terminal of the thirteenth switch element is connected to the control terminal and receives a fourth reference voltage. The second path terminal of the fourteenth switch element receives the third reference voltage and is used to connect the second path terminal of the twelfth switch element to the control terminal according to the local clock signal.

[0014] Optionally, the control terminal of the fourteenth switching element receives the clock signal of this stage.

[0015] Optionally, the pull-down control module further includes a fifteenth switching element and a sixteenth switching element. The control terminal of the fourteenth switching element is connected to the first path terminal of the fifteenth switching element and the second path terminal of the sixteenth switching element. The second path terminal of the fifteenth switching element receives the current stage clock signal, and the control terminal receives the second pre-stage gate signal. The first path terminal of the sixteenth switching element receives the current stage clock signal, and the control terminal receives the second post-stage gate signal.

[0016] Optionally, for the nth stage gate driving unit: the first pre-stage gate signal includes the nMth stage gate signal output by the nMth stage gate driving unit; the first post-stage gate signal includes the n+Kth stage gate signal output by the n+Kth stage gate driving unit; the second pre-stage gate signal includes the (n-1)th stage gate signal output by the (n-1)th stage gate driving unit; and the second post-stage gate signal includes the (n+1)th stage gate signal output by the (n+1)th stage gate driving unit, where M and K are positive integers greater than 1.

[0017] According to another aspect of the present invention, a display device is provided, comprising the gate driving circuit described in any of the preceding claims.

[0018] The gate driving circuit provided by this invention can control the output terminal of the gate signal to a low potential through a pull-down control module, thereby enhancing the pull-down speed and increasing the pull-down capability of the output terminal, thus improving the charging effect of the gate driving circuit and improving display quality. Furthermore, this application can control the duty cycle of the gate signal by setting the duty cycle of the clock signal (the edge of the gate signal corresponds to the edge of the clock signal), without needing to control the rising edge of the subsequent gate signal to correspond to the falling edge of the current stage's driving signal, which would otherwise result in a fixed duty cycle for the gate signal.

[0019] In the embodiments of this application, the addition of a pull-down control module effectively increases the pull-down capability of the output, thereby reducing the performance requirements of the second switching element M2 and allowing the size of the second switching element M2 to be smaller. This significantly reduces the Q noise of the first node caused by the second switching element M2, improving the stability of the circuit.

[0020] In a preferred embodiment, by setting the fifteenth and sixteenth switching elements, the control terminal receives the second pre-stage gate signal and the second post-stage gate signal respectively. When the interval between adjacent clock signals is T, the high-level time of the second pre-stage gate signal and the second post-stage gate signal includes the high-level time of the gate signal of the current stage. This allows the fourteenth switching element to be turned on only once when displaying a frame, thus avoiding unnecessary power consumption. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A circuit block diagram of a gate drive unit according to the prior art is shown.

[0023] Figure 2 A timing diagram of the clock signal and output signal in the prior art is shown.

[0024] Figure 3 A circuit block diagram of a gate driving unit according to a first embodiment of the present invention is shown.

[0025] Figure 4 A circuit block diagram of a gate driving unit according to a second embodiment of the present invention is shown.

[0026] Figure 5 yes Figure 3 and 4 Timing diagrams of the various input and output signals in the embodiment. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0029] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0030] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] Figure 3 A circuit block diagram of a gate driving unit according to a first embodiment of the present invention is shown. Please refer to [link / reference]. Figure 3 The gate driving circuit of this embodiment includes multiple cascaded gate driving units. Each gate driving unit includes: a scan control block 10, an output module 20, a stabilization module 30, a pull-down enhancement module 40, and a reset module 50.

[0032] The scan control block 10 is connected to the first node Q. It pulls the first node Q up to a high level according to the first front gate signal Gn-4 output by the cascaded front gate drive unit, and pulls the first node Q down to a low level according to the first rear gate signal Gn+6 output by the cascaded rear gate drive unit.

[0033] The output module 20 is connected to the scan control block 10 at the first node Q. Based on the potential of the first node Q and the clock signal CLK_N, it outputs the gate signal Gn corresponding to the gate driving unit at the output terminal.

[0034] The stabilization module 30 is connected to the first node Q and the output terminal. The stabilization module 30 is used to pull down the output terminal to a low level when the first node Q is pulled down to a low level, and to maintain the first node Q and the output terminal at a low level.

[0035] The pull-down control module 40 is connected to the output terminal and is used to perform pull-down control on the output terminal according to the clock signal CLK_N.

[0036] The reset module 50 is connected to the first node Q and the output terminal, and is used to reset the first node Q and the output terminal according to the reset control signal Reset.

[0037] It is worth noting that, since the gate driving unit receives a start signal or an end signal from an external signal circuit when it is at the start or end position of the gate driving circuit, and there is no corresponding cascaded preceding gate driving unit providing the first gate signal, the gate driving unit receives the start signal or end signal from the external signal circuit. For example, if the starting gate driving unit does not have a cascaded preceding gate driving unit, the first gate signal output by the cascaded preceding gate driving unit required by the scan control block 10 of the starting gate driving unit needs to be provided by an external signal circuit, such as directly provided by the timing control circuit or provided via the source driving circuit.

[0038] Specifically, the scan control block 10 may include a first switching element M1 and a second switching element M2; the control terminal and the first path terminal of the first switching element M1 receive the first pre-stage gate signal Gn-4 output by the cascaded pre-stage gate driving unit, and the second path terminal of the first switching element M1 is connected to the first node Q; the control terminal of the second switching element M2 receives the first post-stage gate signal Gn+6 output by the cascaded post-stage gate driving unit, the first path terminal is connected to the first node Q, and the second path terminal of the second switching element M2 receives the first reference voltage VSQ; wherein, the first reference voltage VSQ is low level.

[0039] The output module 20 may include a third switching element M3; the control terminal of the third switching element M3 is connected to the first node Q, the first path terminal receives the clock signal CLK_N, and the second path terminal is connected to the output terminal.

[0040] The stabilization module 40 may include a fourth switching element M4, a fifth switching element M5, a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, and a ninth switching element M9.

[0041] The first path terminal of the fourth switching element M4 is connected to the control terminal of the fourth switching element M4 and receives the second reference voltage DCH. The second path terminal of the fourth switching element M4 is connected to the first path terminal of the fifth switching element M5 and the control terminal of the sixth switching element M6.

[0042] The second path terminal of the fifth switching element M5 receives the first reference voltage VSQ, and the control terminal is connected to the first node Q.

[0043] The first path terminal of the sixth switching element M6 receives the second reference voltage DCH, and the second path terminal is connected to the second node QB.

[0044] The first path terminal of the seventh switching element M7 is connected to the second node QB, the second path terminal receives the first reference voltage VSQ, and the control terminal is connected to the first node Q.

[0045] The first path terminal of the eighth switching element M8 is connected to the first node Q, the second path terminal receives the first reference voltage VSQ, and the control terminal is connected to the second node QB.

[0046] The first path terminal of the ninth switching element M9 is connected to the output terminal, the second path terminal receives the third reference voltage VGL, and the control terminal is connected to the second node QB.

[0047] The reset module 20 may include a tenth switching element M10 and an eleventh switching element M11.

[0048] The first path terminal of the tenth switching element M10 receives the third reference voltage VGL, the second path terminal is connected to the output terminal, and the control terminal receives the reset control signal.

[0049] The first path terminal of the eleventh switching element M11 receives the first reference voltage VSQ, the second path terminal is connected to the first node Q, and the control terminal receives the reset control signal.

[0050] In one embodiment, the pull-down control module 40 includes a twelfth switching element M12, a thirteenth switching element M13, and a fourteenth switching element M14.

[0051] The first path terminal of the twelfth switching element M12 is connected to the output terminal, the second path terminal receives the third reference voltage VGL, and the control terminal is connected to the second path terminal of the thirteenth switching element M13 and the first path terminal of the fourteenth switching element M14.

[0052] The first path terminal of the thirteenth switching element M13 is connected to the control terminal and receives the fourth reference voltage VGH.

[0053] The second path terminal of the fourteenth switching element M14 receives the third reference voltage VGL, which is used to connect the second path terminal of the twelfth switching element M12 to the control terminal according to the clock signal CLK_N. In the embodiments of this application, the control terminal of the fourteenth switching element M14 directly receives the clock signal CLK_N.

[0054] In one embodiment, the gate driving unit further includes a capacitor C1, with a first end connected to the first node Q and a second end connected to the output terminal. The capacitor C1 can be, but is not limited to, an external capacitor between the first node Q and the output terminal. Utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Q can be improved. As not shown in the figure, a capacitor may also be included between the first node Q and the third reference voltage VGL, which can effectively stabilize the first node Q, reduce noise, and improve circuit reliability.

[0055] In one embodiment, the gate driving unit can be placed on the left and right sides of the same row of pixels in the display panel. For example, the pull-down control module 40 is placed on one side of the same row of pixels in the display panel, while other parts are placed on the other side of the same row of pixels in the display panel. This replaces the existing left-right parallel charging design, which can save space for the gate driving unit and reduce the width of the left and right boundaries of the display panel.

[0056] In the embodiments of this application, the addition of a pull-down control module effectively increases the pull-down capability of the output, thereby reducing the performance requirements of the second switching element M2 and allowing the size of the second switching element M2 to be smaller. This significantly reduces the Q noise of the first node caused by the second switching element M2, improving the stability of the circuit.

[0057] Figure 4 This is a circuit block diagram of the gate driving unit according to the second embodiment of the present invention. Please refer to [link / reference]. Figure 4 The gate driving circuit of this embodiment includes multiple cascaded gate driving units. Each gate driving unit includes: a scan control block 10, an output module 20, a stabilization module 30, a pull-down enhancement module 40, and a reset module 50.

[0058] The scan control block 10 is connected to the first node Q. It pulls the first node Q up to a high level according to the first front gate signal Gn-4 output by the cascaded front gate drive unit, and pulls the first node Q down to a low level according to the first rear gate signal Gn+6 output by the cascaded rear gate drive unit.

[0059] The output module 20 is connected to the scan control block 10 at the first node Q. Based on the potential of the first node Q and the clock signal CLK_N, it outputs the gate signal Gn corresponding to the gate driving unit at the output terminal.

[0060] The stabilization module 30 is connected to the first node Q and the output terminal. The stabilization module 30 is used to pull down the output terminal to a low level when the first node Q is pulled down to a low level, and to maintain the first node Q and the output terminal at a low level.

[0061] The pull-down control module 40 is connected to the output terminal and is used to perform pull-down control on the output terminal according to the clock signal CLK_N.

[0062] The reset module 50 is connected to the first node Q and the output terminal, and is used to reset the first node Q and the output terminal according to the reset control signal Reset.

[0063] It is worth noting that, since the gate driving unit receives a start signal or an end signal from an external signal circuit when it is at the start or end position of the gate driving circuit, and there is no corresponding cascaded preceding gate driving unit providing the first gate signal, the gate driving unit receives the start signal or end signal from the external signal circuit. For example, if the starting gate driving unit does not have a cascaded preceding gate driving unit, the first gate signal output by the cascaded preceding gate driving unit required by the scan control block 10 of the starting gate driving unit needs to be provided by an external signal circuit, such as directly provided by the timing control circuit or provided via the source driving circuit.

[0064] Specifically, the scan control block 10 may include a first switching element M1 and a second switching element M2; the control terminal and the first path terminal of the first switching element M1 receive the first pre-stage gate signal Gn-4 output by the cascaded pre-stage gate driving unit, and the second path terminal of the first switching element M1 is connected to the first node Q; the control terminal of the second switching element M2 receives the first post-stage gate signal Gn+6 output by the cascaded post-stage gate driving unit, the first path terminal is connected to the first node Q, and the second path terminal of the second switching element M2 receives the first reference voltage VSQ; wherein, the first reference voltage VSQ is low level.

[0065] The output module 20 may include a third switching element M3; the control terminal of the third switching element M3 is connected to the first node Q, the first path terminal receives the clock signal CLK_N, and the second path terminal is connected to the output terminal.

[0066] The stabilization module 40 may include a fourth switching element M4, a fifth switching element M5, a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, and a ninth switching element M9.

[0067] The first path terminal of the fourth switching element M4 is connected to the control terminal of the fourth switching element M4 and receives the second reference voltage DCH. The second path terminal of the fourth switching element M4 is connected to the first path terminal of the fifth switching element M5 and the control terminal of the sixth switching element M6.

[0068] The second path terminal of the fifth switching element M5 receives the first reference voltage VSQ, and the control terminal is connected to the first node Q.

[0069] The first path terminal of the sixth switching element M6 receives the second reference voltage DCH, and the second path terminal is connected to the second node QB.

[0070] The first path terminal of the seventh switching element M7 is connected to the second node QB, the second path terminal receives the first reference voltage VSQ, and the control terminal is connected to the first node Q.

[0071] The first path terminal of the eighth switching element M8 is connected to the first node Q, the second path terminal receives the first reference voltage VSQ, and the control terminal is connected to the second node QB.

[0072] The first path terminal of the ninth switching element M9 is connected to the output terminal, the second path terminal receives the third reference voltage VGL, and the control terminal is connected to the second node QB.

[0073] The reset module 20 may include a tenth switching element M10 and an eleventh switching element M11.

[0074] The first path terminal of the tenth switching element M10 receives the third reference voltage VGL, the second path terminal is connected to the output terminal, and the control terminal receives the reset control signal.

[0075] The first path terminal of the eleventh switching element M11 receives the first reference voltage VSQ, the second path terminal is connected to the first node Q, and the control terminal receives the reset control signal.

[0076] In one embodiment, the pull-down control module 40 includes a twelfth switching element M12, a thirteenth switching element M13, and a fourteenth switching element M14.

[0077] The first path terminal of the twelfth switching element M12 is connected to the output terminal, the second path terminal receives the third reference voltage VGL, and the control terminal is connected to the second path terminal of the thirteenth switching element M13 and the first path terminal of the fourteenth switching element M14.

[0078] The first path terminal of the thirteenth switching element M13 is connected to the control terminal and receives the fourth reference voltage VGH.

[0079] The second path terminal of the fourteenth switching element M14 receives the third reference voltage VGL, which is used to connect the second path terminal of the twelfth switching element M12 to the control terminal according to the clock signal CLK_N. In the embodiments of this application, the control terminal of the fourteenth switching element M14 directly receives the clock signal CLK_N.

[0080] The pull-down control module 40 also includes a fifteenth switching element M15 and a sixteenth switching element M16.

[0081] The control terminal of the fourteenth switching element M14 is connected to the first path terminal of the fifteenth switching element M15 and the second path terminal of the sixteenth switching element M16.

[0082] The second path terminal of the fifteenth switching element M15 receives the clock signal CLK_N, and the control terminal receives the second front-stage gate signal Gn-1.

[0083] The first path terminal of the sixteenth switching element M16 receives the clock signal CLK_N, and the control terminal receives the second subsequent gate signal Gn+1.

[0084] In one embodiment, the specific circuits in the scan control block 10, output module 20, stabilization module 30 and reset module 50 can be adjusted according to the actual situation to achieve the corresponding functions. Correspondingly, the pull-down control module 40 provided in this embodiment can also be used on other gate driving units and is not limited to the circuit structure shown in the figure.

[0085] In one embodiment, the gate driving unit further includes a capacitor C1, with a first end connected to the first node Q and a second end connected to the output terminal. The capacitor C1 can be, but is not limited to, an external capacitor between the first node Q and the output terminal. Utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Q can be improved. As not shown in the figure, a capacitor may also be included between the first node Q and the third reference voltage VGL, which can effectively stabilize the first node Q, reduce noise, and improve circuit reliability.

[0086] In one embodiment, the gate driving unit can be placed on the left and right sides of the same row of pixels in the display panel. For example, the pull-down control module 40 is placed on one side of the same row of pixels in the display panel, while other parts are placed on the other side of the same row of pixels in the display panel. This replaces the existing left-right parallel charging design, which can save space for the gate driving unit and reduce the width of the left and right boundaries of the display panel.

[0087] In the embodiments of this application, the addition of a pull-down control module effectively increases the pull-down capability of the output terminal. Consequently, the performance requirements for the second switching element M2 are lower, and the size of the second switching element M2 can be smaller, which significantly reduces the Q noise of the first node caused by the second switching element M2 and improves the stability of the circuit.

[0088] Figure 5 yes Figure 3 and 4 The timing diagrams of the various input and output signals in the embodiment are as follows: Figure 5 As shown, taking an example where each gate driving unit is adjacent to the cascaded gate driving unit of the previous stage and the phase difference is 1 / 4 time period (e.g., T), and the first switching element M1 to the sixteenth switching element M16 are N-type TFTs, the working process of the gate driving unit in this embodiment is explained. The working process of the gate driving unit includes four stages: pre-charge stage, output stage, pull-down stage, and stabilization stage.

[0089] Pre-charging phase:

[0090] The first pre-stage gate signal Gn-4 output by the cascaded pre-stage gate drive unit transitions from low level to high level. Based on the first pre-stage gate signal Gn-4 output by the cascaded pre-stage gate drive unit, the scan control module 10 pulls the first node Q to high level. Thus, the first node Q can be stably pulled to high level, enabling the output module 20 to enter the working state.

[0091] In one embodiment of the present invention, during forward scanning, the first control terminal of the first switching element M1 receives the first front-stage gate signal Gn-4 output by the cascaded front-stage gate driving unit, which jumps from a low level to a high level, and the first switching element M1 becomes on; then the first node Q, which is connected to the second path terminal of the first switching element M1, receives the first front-stage gate signal Gn-4 through the on-stage first switching element M1, and the first node Q is charged and pulled up to a high level.

[0092] In one embodiment of the present invention, when the first node Q is charged and pulled up to a high level, the control terminal of the third switching element M3 connected to the first node Q is turned on, and the output module 20 enters the working state.

[0093] Before the clock signal CLK_N transitions from low to high, the twelfth switching element M12 remains on, and its output receives the third reference voltage VGL. The third reference voltage VGL is, for example, low.

[0094] In one embodiment of the present invention, when the first node Q is charged and pulled up to a high level, the control terminal of the seventh switching element M7 connected to the first node Q becomes high and becomes in a conducting state. Thus, the second node QB connected to the first path terminal of the seventh switching element M7 receives the first reference voltage VSQ through the conducting seventh switching element M7. The first reference voltage VSQ can be low and can be supplied by an internal circuit or an external driving system. When the second node QB is pulled down to a low level, the eighth control terminal of the eighth switching element M8 and the ninth control terminal of the ninth switching element M9 connected to the second node QB are low. Therefore, the eighth switching element M8 and the ninth switching element M9 are in a disconnected state, and the stabilization module 40 enters a non-working state, which has no effect on the output terminal.

[0095] Output phase:

[0096] When the clock signal CLK_N transitions from low to high, the fourteenth switching element M14 is turned on, disconnecting the output terminal from the third reference voltage terminal.

[0097] The first node Q is pulled up to a high level. According to the clock signal CLK_N, it jumps from a low level to a high level. The output terminal of the output module 20 receives the first clock signal CLK_N and outputs the gate signal Gn of this stage at the output terminal.

[0098] In one embodiment of the present invention, the second path terminal of the third switching element M3 is connected to the output terminal. The output terminal receives the first clock signal CLK_N on the first path terminal of the third switching element M3 through the conducting third switching element M3, thereby outputting the gate signal Gn of this stage. In another embodiment of the present invention, the first node Q is further pulled up by the second capacitor C1 to further increase the level of the first node Q and fully turn on the third switching element M3.

[0099] Pull-down phase:

[0100] When the clock signal CLK_N transitions from high to low, the third switching element M3 is turned off, and the output module 20 stops outputting the gate signal Gn at the output terminal.

[0101] When the clock signal CLK_N transitions from high to low, the twelfth switching element M12 turns on, and the output receives the third reference voltage VGL. For example, the third reference voltage VGL is low, and the falling edge of the gate signal Gn output from the output terminal is aligned with the falling edge of the clock signal CLK_N.

[0102] The pull-down control module can control the gate signal output terminal to be pulled to a low potential, enhancing the pull-down speed and increasing the pull-down capability of the output terminal, thereby improving the charging effect of the gate drive circuit and enhancing display quality. Furthermore, this application controls the duty cycle of the gate signal by setting the duty cycle of the clock signal (the edge of the gate signal corresponds to the edge of the clock signal). This eliminates the need to control the rising edge of the subsequent gate signal to correspond to the falling edge of the current stage's drive signal, thus avoiding a fixed duty cycle for the gate signal.

[0103] Stable phase:

[0104] When both the first pre-stage gate signal Gn-4 output from the cascaded pre-stage gate driver unit and the first post-stage gate signal Gn+6 output from the cascaded post-stage gate driver unit are low, the scan control module 10 enters a non-operating state. Simultaneously, the first node Q has been pulled down to a low level, so the output module 20 enters a non-operating state, without affecting the operation of the stabilization module 40. Therefore, the stabilization module 40 enters an operating state, which can be used to maintain the first node Q, the first output terminal, and the second output terminal at a low level.

[0105] In one embodiment of the present invention, the first node Q is pulled down to a low level, and the control terminal of the seventh switching element M7 connected to the first node Q becomes low, turning it into an off state. Thus, the second node QB, connected to the first path terminal of the seventh switching element M7, receives the second reference voltage DCH through the conducting fourth switching element M4 and sixth switching element M6. This second reference voltage DCH can be high, supplied by an internal circuit or an external driving system. When the second node QB is pulled up to a high level, the eighth control terminal of the eighth switching element M8 and the ninth control terminal of the ninth switching element M9 connected to the second node QB become high, and the eighth and ninth switching elements M8 and M9 become on. The stabilization module 40 enters a non-working state. The first node Q receives the first reference voltage VSQ through the connected on-state eighth switching element M8; the output terminal receives the third reference voltage VGL through the connected on-state ninth switching element M9, maintaining a low level during the stabilization phase to ensure system stability.

[0106] It should be noted that during the aforementioned dropdown phase, in Figure 3 In the pull-down control module shown, the thirteenth switch element M13 is normally open, while the fourteenth switch element M14 is directly controlled by the clock signal CLK_N. That is, the fourteenth switch element M14 will be turned on once in each clock cycle, so that the fourth reference voltage VGH and the third reference voltage VGL are neutralized and power consumption is generated.

[0107] Based on this, Figure 4In the pull-down control module shown, by setting the fifteenth switching element M15 and the sixteenth switching element M16, the control terminal receives the second pre-stage gate signal Gn-1 and the second post-stage gate signal Gn+1 respectively, from... Figure 5 As can be seen, when adjacent clock signals have an overlap time of 1T or more (1T is the actual charging time of a row of pixels), the high level time of the second pre-stage gate signal Gn-1 and the second post-stage gate signal Gn+1 includes the high level time of the gate signal Gn of the same stage. This allows the fourteenth switching element M14 to be turned on only once when displaying a frame, thus avoiding unnecessary power consumption.

[0108] In one embodiment of this application, the first front-stage gate signal Gn-4 is merely an exemplary description, which may include the gate signal Gn-N output by the nNth stage gate driving unit, and the first rear-stage gate signal Gn+6 is merely an exemplary description, which may include the gate signal Gn+M output by the (n+M)th stage gate driving unit, where M and N are positive integers greater than 1.

[0109] In one embodiment, when n is less than N or n+M is greater than the total number of gate lines, the gate signal Gn-N output by the nNth-level gate driving unit and the gate signal Gn+M output by the n+Mth-level gate driving unit can be provided by an external signal circuit, such as directly provided by a timing control circuit or provided as a start signal via a source driving circuit.

[0110] In another embodiment of this application, a display device is also provided, including the gate driving circuit described above.

[0111] It should be noted that those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be some small but reasonable delays, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms “approximately” or “substantially” used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., “1” or “0”) depends on whether positive or negative logic is used.

[0112] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A gate driving circuit, comprising a plurality of cascaded gate driving units, characterized in that, Each gate driving unit includes: an output terminal and... A scan control block, connected to the first node, pulls the first node up to a high level according to the first front-stage gate signal, and pulls the first node down to a low level according to the first rear-stage gate signal; The output module is connected to the first node and the scan control block. Based on the potential of the first node and the clock signal of the current stage, the output module outputs the gate signal of the current stage corresponding to the gate driving unit of the current stage at the output terminal. A pull-down control module, connected to the output terminal, is used to perform pull-down control on the output terminal according to the local clock signal; A stabilization module, connected to the first node and the output terminal, is used to maintain the first node and the output terminal at a low level when the first node is pulled down to a low level. The pull-down control module includes a twelfth switch element, a thirteenth switch element, and a fourteenth switch element. The first path terminal of the twelfth switching element is connected to the output terminal, the second path terminal of the twelfth switching element receives the third reference voltage, and the control terminal of the twelfth switching element is connected to the second path terminal of the thirteenth switching element and the first path terminal of the fourteenth switching element. The first path terminal of the thirteenth switching element is connected to the control terminal and receives the fourth reference voltage; The second path terminal of the fourteenth switching element receives the third reference voltage and is used to connect the second path terminal of the twelfth switching element to the control terminal according to the local clock signal.

2. The gate driving circuit according to claim 1, characterized in that, The scan control block includes: A first switching element, wherein the control terminal and the first path terminal of the first switching element receive the first front-end gate signal, and the second path terminal is connected to the first node; The second switching element has a control terminal that receives the first subsequent gate signal, a first path terminal that is connected to the first node, and a second path terminal that receives the first reference voltage.

3. The gate driving circuit according to claim 1, characterized in that, The output module includes a third switching element. The control terminal of the third switching element is connected to the first node, the first path terminal receives the clock signal of this stage, and the second path terminal is connected to the output terminal.

4. The gate driving circuit according to claim 1, characterized in that, The stabilization module includes a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, an eighth switching element, and a ninth switching element. The first path terminal of the fourth switching element is connected to the control terminal and receives the second reference voltage. The second path terminal of the fourth switching element is connected to the first path terminal of the fifth switching element and the control terminal of the sixth switching element. The second path terminal of the fifth switching element receives the first reference voltage, and the control terminal is connected to the first node; The first path terminal of the sixth switching element receives the second reference voltage, and the second path terminal is connected to the second node; The first path terminal of the seventh switching element is connected to the second node, the second path terminal receives the first reference voltage, and the control terminal is connected to the first node. The first path terminal of the eighth switching element is connected to the first node, the second path terminal receives the first reference voltage, and the control terminal is connected to the second node. The first path terminal of the ninth switching element is connected to the output terminal, the second path terminal receives the third reference voltage, and the control terminal is connected to the second node.

5. The gate driving circuit according to claim 1, characterized in that, Each of the gate driving units further includes a reset module, which is connected to the first node and the output terminal, and is used to reset the first node and the output terminal according to a reset control signal. The reset module includes a tenth switching element and an eleventh switching element. The first path terminal of the tenth switching element receives the third reference voltage, the second path terminal is connected to the output terminal, and the control terminal receives the reset control signal. The first path terminal of the eleventh switching element receives a first reference voltage, the second path terminal is connected to the first node, and the control terminal receives the reset control signal.

6. The gate driving circuit according to claim 1, characterized in that, The control terminal of the fourteenth switching element receives the clock signal of this level.

7. The gate driving circuit according to claim 1, characterized in that, The pull-down control module further includes a fifteenth switch element and a sixteenth switch element. The control terminal of the fourteenth switch element is connected to the first path terminal of the fifteenth switch element and the second path terminal of the sixteenth switch element. The second path terminal of the fifteenth switching element receives the clock signal of this stage, and the control terminal receives the second front-stage gate signal; The first path terminal of the sixteenth switching element receives the clock signal of this stage, and the control terminal receives the gate signal of the second subsequent stage.

8. The gate driving circuit according to claim 7, characterized in that, For the gate drive unit of the nth stage: The first front-stage gate signal includes the nMth stage gate signal output by the nMth stage gate drive unit; The first post-stage gate signal includes the (n+K)th stage gate signal output by the (n+K)th stage gate drive unit; The second front-stage gate signal includes the (n-1)th stage gate signal output by the (n-1)th stage gate drive unit; The second subsequent gate signal includes the (n+1)th gate signal output by the (n+1)th gate drive unit. Where M and K are positive integers greater than 1.

9. A display device, characterized in that, Includes the gate drive circuit according to any one of claims 1-8.

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