Method, system and device for improving uniformity of key dimensions of etched patterns on chips

Abstract

The present invention relates to the field of photolithography technology, and in particular to a method, system and device for improving the uniformity of key dimensions of etching patterns on a chip. The present invention provides a method for improving the uniformity of key dimensions of etching patterns on a chip, comprising the following steps: obtaining an initial etching pattern on a chip, extracting a photoresist pattern corresponding to the initial etching pattern; providing an etching deviation table, performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern; obtaining a density distribution map of the initial etching pattern on the chip and obtaining its corresponding etching deviation map; establishing a mapping relationship between the density distribution map and the etching deviation map; performing a second compensation on the target pattern based on the mapping relationship to obtain an optimized pattern; etching the optimized pattern to obtain a final etching pattern. The problem of poor uniformity of key dimensions of etching patterns during etching is solved.

Description

[Technical field]

[0001] The present invention relates to the field of photolithography technology, and in particular to a method, system and equipment for improving the uniformity of key dimensions of etched patterns on a chip. [Background technology]

[0002] The most core step in semiconductor chip manufacturing is to transfer the chip design pattern to the silicon wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching. The wafer fab (FAB) obtains the mask data (Mask) corrected by optical proximity (OPC) from the original design layout, and then forms a photoresist pattern on the photoresist. After the photoresist pattern is developed, it can be etched to form an etched pattern. However, the etching process will cause etching deviation, that is, the line width of the photoresist before etching is different from the line width of the etched material after the photoresist is removed. At present, the common practice in the industry is to first modify the design layout according to an etching bias table (EtchingBiasTable), and compensate the etching bias into the photolithography photoresist pattern to rewrite and calibrate the photolithography photoresist pattern.

[0003] If two photoresist patterns have the same local environment, but the environment is different in a larger range, it will lead to different etching load effects. Even if the etching deviation is taken into account through the etching deviation table, that is, the size of the photoresist pattern is the same, the size of the etched pattern obtained after etching will still be different, which will lead to line width uniformity (also known as CDU) problems, that is, poor uniformity of critical dimensions, which will affect the yield of wafer fab tapeout. [Summary of the invention]

[0004] In order to solve the problem of poor uniformity of key dimensions of etched patterns during the etching process, the present invention provides a method, system and device for improving the uniformity of key dimensions of etched patterns on a chip.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a method for improving the uniformity of key dimensions of etched patterns on a chip, comprising the following steps:

[0006] Obtaining an initial etching pattern on the chip, and extracting a photoresist pattern corresponding to the initial etching pattern;

[0007] Providing an etching deviation table, after extracting the photoresist pattern, performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern;

[0008] Obtaining a density distribution map of an initial etching pattern on a chip and obtaining a corresponding etching deviation map;

[0009] Establishing a mapping relationship between a density distribution map and an etching deviation map;

[0010] Performing a second compensation on the target graph based on the mapping relationship to obtain an optimized graph;

[0011] The optimized pattern is etched to obtain a final etched pattern.

[0012] Preferably, performing the first compensation on the photoresist pattern by using the etching deviation table comprises:

[0013] The parameters of the photoresist pattern include spacing and line width. The etching deviation value is obtained through the etching deviation table. The line width of the photoresist pattern and / or the spacing between the photoresist patterns are modified based on the etching deviation value to perform the first compensation on the photoresist pattern.

[0014] Preferably, obtaining a density distribution map of an initial etching pattern on a chip includes:

[0015] Divide the chip into blocks;

[0016] Get the area of ​​the initial etching pattern in a certain block;

[0017] Obtaining an initial etching pattern density of the block based on the area of ​​the initial etching pattern in the block and the area of ​​the block;

[0018] The position of the block is obtained, and the density distribution map of the initial etching pattern on the chip is obtained based on the position of the block and the density of the initial etching pattern in the block.

[0019] Preferably, after obtaining the density distribution map of the initial etching pattern on the chip, the method further includes:

[0020] Set the preset first density change value,

[0021] Determining whether the density difference between adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being greater than a preset first density change value;

[0022] If yes, then obtain the etching pattern corresponding to the position that meets the requirements, and cluster the etching pattern to obtain at least two categories of classification patterns;

[0023] Obtain the location of the etching pattern within the classification pattern for each category;

[0024] The density distribution map of the classification patterns of the same category is obtained based on the position of the etching pattern within the classification patterns of the same category and the density distribution map of the initial etching pattern.

[0025] Preferably, after obtaining the density distribution diagram of the classification graph, the method further includes:

[0026] Set the preset second density change value,

[0027] Determine whether the density difference between adjacent positions on the density distribution diagram of the classification graphics of the same category is greater than a preset second density change value;

[0028] If so, set the position as a local similarity point;

[0029] Performing etching processing on the target pattern corresponding to the local similar point to obtain the actual etching pattern;

[0030] Obtain the etching deviation value between the actual etching patterns.

[0031] Preferably, calculating and obtaining the corresponding etching deviation map includes:

[0032] An AI model is provided, and the density distribution map of the initial etching pattern on the chip is taken as input. The etching deviation map corresponding to the output density distribution map is calculated by the AI ​​model.

[0033] Preferably, performing a second compensation on the target graphic based on the mapping relationship includes:

[0034] The target graphics include spacing and line width;

[0035] Performing etching processing on the target pattern to obtain its corresponding target etching pattern;

[0036] Obtaining a density distribution map of a target etching pattern on a chip, and obtaining an etching deviation value based on the density distribution map of the target etching pattern and a mapping relationship;

[0037] The line width of the target pattern and / or the spacing between the target patterns are modified based on the etching deviation value to perform a second compensation on the target pattern.

[0038] Preferably, etching the optimized pattern includes:

[0039] Providing a local etching model, and using the local etching model to etch the optimized pattern obtained after the second compensation to obtain a final etching pattern;

[0040] Determine whether there is etching deviation in the final etching pattern;

[0041] If it exists, the optimized pattern is taken as the target pattern for iteration until the etching pattern finally obtained does not have etching deviation, and the etching pattern finally obtained is output.

[0042] In order to solve the above technical problems, the present invention provides another technical solution as follows: a system for improving the uniformity of key dimensions of etched patterns on a chip, the system comprising:

[0043] OPC module: used to perform analog imaging processing to obtain photoresist patterns;

[0044] Etching module: used for etching the photoresist pattern to obtain the initial etching pattern;

[0045] Identification module: used to obtain the density distribution map of the initial etching pattern on the chip;

[0046] Calculation module: used to calculate and obtain the etching deviation map corresponding to the initial etching pattern;

[0047] AI module: used to establish the mapping relationship between density distribution map and etching deviation map;

[0048] Processing module: used for performing a first compensation on the photoresist pattern through an etching deviation table to obtain a target pattern after the photoresist pattern is extracted, and performing a second compensation on the target pattern based on a mapping relationship to obtain an optimized pattern;

[0049] Output module: used to output the final etching pattern.

[0050] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer device, applied to the above method for improving the uniformity of key dimensions of etched graphics on chips, comprising a memory, a processor and a computer program stored in the memory, and the processor executes the above computer program to implement the method for improving the uniformity of key dimensions of etched graphics on chips.

[0051] Compared with the prior art, the method, system and device for improving the uniformity of key dimensions of etching patterns on a chip provided by the present invention have the following beneficial effects:

[0052] 1. A method for improving the uniformity of critical dimensions of etched patterns on a chip provided by an embodiment of the present invention comprises the following steps:

[0053] Obtaining an initial etching pattern on the chip, and extracting a photoresist pattern corresponding to the initial etching pattern;

[0054] Providing an etching deviation table, and performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern;

[0055] Obtaining a density distribution map of an initial etching pattern on a chip and obtaining a corresponding etching deviation map;

[0056] Establishing a mapping relationship between a density distribution map and an etching deviation map;

[0057] Performing a second compensation on the target graph based on the mapping relationship to obtain an optimized graph;

[0058] The optimized pattern is etched to obtain a final etched pattern.

[0059] 2. The first compensation of the photoresist pattern by the etching deviation table in the embodiment of the present invention includes:

[0060] The parameters of the photoresist pattern include spacing and line width. The etching deviation value is obtained through the etching deviation table. The line width of the photoresist pattern and / or the spacing between the photoresist patterns are modified based on the etching deviation value to perform a first compensation on the photoresist pattern. The first compensation can preliminarily eliminate the etching deviation of the photoresist pattern.

[0061] 3. The embodiment of the present invention obtains a density distribution map of the initial etching pattern on the chip, including:

[0062] Divide the chip into blocks;

[0063] Get the area of ​​the initial etching pattern in a certain block;

[0064] Obtaining an initial etching pattern density of the block based on the area of ​​the initial etching pattern in the block and the area of ​​the block;

[0065] The position of the block is obtained, and the density distribution map of the initial etching pattern on the chip is obtained based on the position of the block and the density of the initial etching pattern in the block. By obtaining the density of the initial etching pattern in each block, the density distribution map of the initial etching pattern on the chip is obtained, and the calculation process is simple and the processing efficiency is high.

[0066] 4. After obtaining the density distribution map of the initial etching pattern on the chip, the embodiment of the present invention further includes:

[0067] Set the preset first density change value,

[0068] Determining whether the density difference between adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being greater than a preset first density change value;

[0069] If yes, then obtain the etching pattern corresponding to the position that meets the requirements, and cluster the etching pattern to obtain at least two categories of classification patterns;

[0070] Obtain the location of the etching pattern within the classification pattern for each category;

[0071] Based on the position of the etching pattern in the classification pattern of the same category and the density distribution map of the initial etching pattern, the density distribution map of the classification pattern of the same category is obtained. Clustering the target patterns of the same shape can greatly simplify the calculation amount of the subsequent process and help improve the efficiency of obtaining the etching deviation map.

[0072] 5. After obtaining the density distribution diagram of the classification graph, the embodiment of the present invention further includes:

[0073] Set the preset second density change value,

[0074] Determine whether the density difference between adjacent positions on the density distribution diagram of the classification graphics of the same category is greater than a preset second density change value;

[0075] If so, set the position as a local similarity point;

[0076] Performing etching processing on the target pattern corresponding to the local similar point to obtain the actual etching pattern;

[0077] The etching deviation value between the actual etching patterns is obtained. The number of density distribution maps and etching deviation maps of the initial etching patterns that are directly analyzed is very large. The density distribution map and etching deviation map of the initial etching patterns are indirectly obtained by analyzing the relationship between the density distribution map and the etching deviation map of the classified patterns, which helps to reduce the amount of calculation.

[0078] 6. The embodiment of the present invention calculates and obtains the corresponding etching deviation map including:

[0079] Provide an AI model, take the density distribution map of the initial etching pattern on the chip as input, and calculate the etching deviation map corresponding to the output density distribution map through the AI ​​model. Applying the AI ​​model to the analysis process of the density distribution map and the etching deviation map greatly improves the expressiveness of the model and reduces the residual error of the model.

[0080] 7. The second compensation of the target graphic based on the mapping relationship in the embodiment of the present invention includes:

[0081] The target graphics include spacing and line width;

[0082] Performing etching processing on the target pattern to obtain its corresponding target etching pattern;

[0083] Obtaining a density distribution map of a target etching pattern on a chip, and obtaining an etching deviation value based on the density distribution map of the target etching pattern and a mapping relationship;

[0084] The line width of the target pattern and / or the spacing between the target patterns are modified based on the etching deviation value to perform a second compensation on the target pattern. After the target pattern has undergone the second compensation and etching process, the influence of the load effect has been considered during the photolithography and etching process, so the final etching pattern generated by the etching is closer to the expectation.

[0085] 8. The embodiment of the present invention etches the optimized pattern including:

[0086] Providing a local etching model, and using the local etching model to etch the optimized pattern obtained after the second compensation to obtain a final etching pattern;

[0087] Determine whether there is etching deviation in the final etching pattern;

[0088] If it exists, the optimized pattern is used as the target pattern for iteration until the final etched pattern has no etching deviation, and the final etched pattern is output. By providing a local etching model, the optimized pattern obtained after the second compensation is etched using the local etching model to obtain the final etching pattern.

[0089] 9. An embodiment of the present invention also provides a system having the same beneficial effects as the above-mentioned method for improving the uniformity of key dimensions of etched patterns on a chip, which will not be described in detail here.

[0090] 10. An embodiment of the present invention further provides a computer device having the same beneficial effects as the above-mentioned method for improving the uniformity of key dimensions of etched patterns on a chip, which will not be described in detail here.

Brief Description of the Drawings

[0091] Figure 1a It is a schematic flow chart of a method for improving the uniformity of key dimensions of etched patterns on a chip provided by the first embodiment of the present invention.

[0092] Figure 1b It is a schematic diagram of the process of etching an optimized pattern in a method for improving the uniformity of key dimensions of an etched pattern on a chip provided by the first embodiment of the present invention.

[0093] Figure 2a It is a comparison diagram provided by the first embodiment of the present invention in which the local environment is the same but the larger environment is different.

[0094] Figure 2b yes Figure 2a Magnified view of upper area 2c.

[0095] Figure 3a It is a schematic diagram of the process of obtaining a density distribution map provided by the first embodiment of the present invention.

[0096] Figure 3b It is a schematic diagram of a density distribution diagram provided by the first embodiment of the present invention.

[0097] Figure 3c A schematic diagram of a process of replicating a chip into a replica image provided by a first embodiment of the present invention.

[0098] Figure 4 It is a schematic diagram of graphic categories after clustering provided by the first embodiment of the present invention.

[0099] Figure 5 It is a density distribution diagram of the classification graphics provided by the first embodiment of the present invention.

[0100] Figure 6 This is an etching deviation diagram provided by the first embodiment of the present invention.

[0101] Figure 7It is a schematic diagram of the structure of a system for improving the uniformity of key dimensions of etched patterns on a chip provided by the second embodiment of the present invention.

[0102] Figure 8 It is a schematic diagram of the structure of a computer device provided by the second embodiment of the present invention.

[0103] Description of the accompanying drawings:

[0104] 1. System; 2. Computer equipment;

[0105] 11. OPC module; 12. Etching module; 13. Identification module; 14. Calculation module; 15. AI model; 16. Processing module; 17. Output module; 21. Memory; 22. Processor; 23. Computer program. [Specific implementation method]

[0106] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0107] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0108] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0109] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0110] The flow chart and block diagram in the accompanying drawings of the present invention illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be particularly noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0111] The most core step in semiconductor chip manufacturing is to transfer the chip design pattern to the silicon wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching. In the current mainstream integrated circuit production process, photolithography technology is to chemically change the photoresist under exposure to light of a special wavelength, such as a wavelength of 193nm or 248nm, and then transfer the pattern designed on the mask to the photoresist morphology on the silicon wafer with the help of a developer. The etching process is based on selectively removing unnecessary materials with the help of the photoresist morphology, thereby ultimately creating the required fine pattern on the silicon wafer. That is, the designer can transfer the designed pattern to the mask template to form a mask pattern on the mask template, and after the light passes through the mask template, it can be exposed on the photoresist to form a photoresist pattern, and finally the photoresist pattern can be etched to form an etched pattern on the chip or wafer.

[0112] With the continuous evolution of chip technology nodes, the size of the design layout has been much smaller than the wavelength of photolithography (193nm), which leads to a strong diffraction effect, usually called the optical proximity effect, which causes a large deviation between the morphology of the chip design layout and the morphology printed on the photoresist by photolithography. In order to compensate for this deviation, during the manufacturing process of integrated circuits, the wafer fab (FAB) needs to obtain the optical proximity corrected (OPC) mask data from the original design layout, and then take the mask data to tape out. Optical proximity correction is based on the photolithography model to correct the layout. The range of the optical proximity effect is relatively small, generally a few microns, so the range considered by the photolithography model is also about a few microns.

[0113] Furthermore, etching after photolithography can cause etching deviation. For example, the line width of the photoresist pattern before etching is different from the line width of the etched pattern material after the photoresist is removed. The size of the etching deviation is related to many factors: substrate material, line width of the pattern on the photoresist, parameters of the etching process, etc. On the one hand, the etching deviation will cause the overall size after etching to change. On the other hand, the size of the pattern with the same size after photolithography will also become different after etching. At present, the common practice in the industry is to first modify the designed layout according to an etching bias table (Etching Bias Table) and compensate the etching deviation into the photolithography photoresist pattern. The above compensation can also be considered as a correction of the etching pattern with etching deviation, and in order to obtain the expected etching pattern, the photoresist pattern is usually not directly modified. Since the formation of the photoresist pattern is jointly determined by the mask pattern on the mask plate, the exposure conditions and the optical proximity correction (Optical Proximity Correction, also known as OPC) correction, compensation refers to modifying one or more combinations of the mask pattern, exposure conditions or OPC.

[0114] The target after photolithography, that is, the photoresist pattern is usually called ADITarget. The above compensation, that is, the action of changing ADITarget is usually called re-calibration in the industry. After re-calibration according to the etching deviation table, during the exposure process, due to changes in the mask pattern, exposure conditions or OPC, the image after exposure is considered as the target pattern according to the photoresist pattern after the etching deviation is corrected. In this way, in the subsequent etching process, the corrected photoresist pattern will take the etching deviation into account in advance, so that the expected etching pattern can be obtained after etching. It should be noted that the etching deviation table is usually obtained based on experience, that is, the engineer compares the actual etched pattern with the expected etching pattern, manually measures the errors in the line width (width) and spacing (space) of the two patterns, and finally obtains the etching deviation table.

[0115] However, there is an obvious loading effect in the actual etching process. For example, when the chip contains both sparse and dense patterns to be etched, the etching rate of the dense area is lower than that of the sparse area. This is also called the overload effect. This is because the dense area consumes more reactants during the etching process, and the reactants cannot reach the dense etching area in time. For example, in the etching of structures with high aspect ratios, such as deep holes or deep grooves, the etching rate of smaller holes or grooves is lower than that of larger holes or grooves. This is called the loading effect related to the aspect ratio, also called the aperture effect, because it is difficult for the etching gas to enter the deep part, and at the same time, it is difficult for the reaction products to overflow, resulting in a decrease in the etching rate at the bottom.

[0116] Specifically, if two photoresist patterns are assumed to have different local environments, then the etched patterns formed after etching must be different. The photoresist patterns can be recalibrated through the etching deviation table to compensate for the photoresist patterns. However, if two photoresist patterns are assumed to have the same local environment, but the environment is not the same in a larger range. Even if the photoresist pattern is compensated by the etching deviation table, since the local environment is the same, when only the etching deviation table is used to compensate, the photoresist pattern after exposure is still the same, and the size obtained after photolithography is the same. However, the photoresist pattern is affected by a larger range of environments during the etching process, which will lead to different etching load effects. That is, the size of the etched pattern obtained after etching will still be different. This phenomenon occurs because the photoresist pattern has the same local environment but different larger environment, and the etched pattern obtained by the final etching is different due to the load effect. It is usually called the problem of inconsistent uniformity of the key dimensions of the etched pattern. That is, the line width consistency (uniformity, also known as CDU) problem, and the CDU problem will seriously affect the yield of the wafer fab (FAB).

[0117] In process practice, in order to suppress the load effect, on the one hand, the actual etching parameters such as power, gas flow, gas pressure and temperature are adjusted to achieve a more uniform etching effect. However, after all, its adjustment has limitations. If more precise adjustments are to be made, it is necessary to find a way to improve the uniformity of the key dimensions of the etched graphics on the chip to compensate for the negative impact of the load effect.

[0118] To solve the above technical problems, please refer to Figure 1a The first embodiment of the present invention provides a method for improving the uniformity of critical dimensions of etching patterns on a chip, comprising the following steps:

[0119] S1, obtaining an initial etching pattern on the chip and extracting a photoresist pattern corresponding to the initial etching pattern;

[0120] S2, providing an etching deviation table, and performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern;

[0121] S3, obtaining a density distribution map of the initial etching pattern on the chip and obtaining a corresponding etching deviation map;

[0122] S4, establishing a mapping relationship between the density distribution map and the etching deviation map;

[0123] S5, performing a second compensation on the target graph based on the mapping relationship to obtain an optimized graph;

[0124] S6, etching the optimized pattern to obtain a final etched pattern.

[0125] It is understandable that in the photolithography process, the designer can manufacture the designed graphics onto the mask plate to form a mask pattern, and after the light passes through the mask pattern, it can be exposed on the photoresist to form a photoresist pattern, and finally the photoresist pattern can be etched to form an etched pattern on the chip or wafer. It should be noted that the above process can be simulated by means of a preset algorithm, program or software, that is, the process of simulating photolithography. Therefore, the initial etching pattern on the chip can be obtained first, and the photoresist pattern corresponding to the initial etching pattern can be extracted by means of a preset algorithm, program or software. Because two photoresist patterns, if their local environments are the same, but the environments are not the same in a larger range, it is easy to cause the problem of load effect during the etching process. The present invention can optimize the mask design through the above method to compensate for the negative impact of the load effect. It should be noted that since the photoresist pattern will not be directly modified during the photolithography process, the compensation of the photoresist pattern or the target pattern described in the method provided by the present invention refers to modifying one or more combinations of the corresponding mask pattern, exposure conditions or OPC. That is, the exposure process is optimized so that the morphology of the photoresist pattern with the same local environment is changed, and then the etched pattern obtained by the photoresist pattern after the etching process is close to the expected effect. Specifically, the purpose of compensation is to modify the morphology of the photoresist pattern or the target pattern so that the etched pattern after etching is also changed. Therefore, compensation only needs to change the morphology of the photoresist pattern or the target pattern. The specific steps of compensation will not be repeated in the following of the present invention.

[0126] Furthermore, after the photoresist pattern is extracted, the photoresist pattern can be compensated for the first time with the help of the etching deviation table to obtain the target pattern, that is, the morphology of the photoresist pattern corresponding to the initial etching pattern can be modified for the first time through the etching deviation table. There are two situations when the compensated photoresist pattern, that is, the target pattern is etched. One is that the local environment between the two target patterns is different, so there is no load effect in the etching process of the two target patterns, and processing patterns with different local environments is a problem considered by OPC. The other is the target pattern with the same local environment, but the environment is not the same in a larger range, and the load effect that exists cannot be eliminated only with the help of the etching deviation table. Specifically, the etching deviation table is obtained by engineers through experience and will not be elaborated on here.

[0127] Further, after obtaining the density distribution map of the initial etching pattern on the chip, the etching deviation map corresponding to the density distribution map can be obtained by calculation and measurement. It should be understood that the density distribution map refers to the density distribution state of the initial etching pattern on the chip, which can intuitively reflect the density of the etching pattern on the chip. What is considered in the aperture effect is the aspect ratio. Usually, the depth of the hole (the hole formed by the etching pattern) is the same, that is, the size of the hole is considered. Therefore, whether it is the overload effect in the load effect or the aperture effect in the load effect. The density distribution map of the etching pattern is directly related to it. When a position with the same local environment and a different larger environment is obtained, the density distribution map of the position is first obtained, and then the position can be etched to obtain the etching pattern. After calculating and measuring the contour of the etching pattern, the etching deviation value can be obtained by comparing the contour, and then the etching deviation map corresponding to the density distribution map of the initial etching pattern can be obtained by the position and the etching deviation value.

[0128] It should be noted that the establishment of the above-mentioned density distribution map can be achieved by manual measurement or by setting up an identification module to identify it. The density distribution map is used as an input value, and the calculation carrier can be an AI model or a polynomial algorithm model. The specific calculation carrier is not specifically limited, and its purpose is to output the corresponding etching deviation map. The density distribution map represents the density distribution of the etching pattern at a specific position or a certain area on the chip, and the etching deviation map represents: the numerical value of the etching deviation corresponding to a certain density distribution. It should be understood that in the process of calculating the etching deviation map by inputting the density distribution map, a certain amount of data can be accumulated to establish the mapping relationship between the density distribution map and the etching deviation map, and as the amount of data gradually increases, the mapping relationship between the density distribution map and the etching deviation map becomes more accurate. That is, the data accumulation process can be considered as an iterative optimization process of the mapping relationship.

[0129] Furthermore, since the above-mentioned target graphics have the same local environment but different larger environments, that is, the shapes of the two target graphics are exactly the same. At this time, the target graphics can be compensated for a second time based on the mapping relationship to obtain an optimized graphic. Specifically, since the mapping relationship can reflect the correspondence between the density distribution map and the etching deviation map, illustratively, in the second compensation process, the position of the target graphics with the same local environment but different larger environments on the chip can be obtained, and the density value of the position can be obtained based on the density distribution map, and then the corresponding etching deviation value can be obtained based on the mapping relationship, and then based on the etching deviation value, the morphology of the target graphics can be modified by optimizing the exposure process to obtain the optimized graphics.

[0130] It should be understood that the target graphics have the same local environment but different larger environments, which can be regarded as similar shapes of the target graphics in the local environment. If the target graphics are directly etched, they will be affected by the load effect, so that the etched graphics obtained are different. The result expected by the engineer is that the etched graphics obtained with the same local environment should be the same. Therefore, the optimized graphics are obtained by the second compensation of the target graphics. Unlike the target graphics, the shapes of the target graphics with the same local environment are similar, while the shapes of the optimized graphics are not similar, but the results of the final etched graphics obtained by the optimized graphics after etching are similar. That is, after the target graphics are compensated, its shape has changed. After the target graphics have undergone the second compensation and etching process, the influence of the load effect has been considered in the process of photolithography and etching, so the final etched graphics generated by its etching are closer to expectations. It should be noted that the etching process described in this embodiment is with the help of a preset algorithm, program or software, and will not be described in detail later.

[0131] In summary, the present invention takes into account the problem of load effect of photoresist patterns with the same local environment but different larger environment. By compensating the photoresist patterns twice, the load effect problem existing in the etching process is eliminated, and the uniformity of the key dimensions of the etched patterns on the chip is improved, thereby improving the yield of the wafer fab flow.

[0132] Furthermore, in the above step S1, providing an initial etching pattern on the chip includes:

[0133] Provide initial mask and exposure conditions;

[0134] The initial mask is subjected to simulated imaging processing under exposure conditions to obtain a photoresist pattern;

[0135] The photoresist pattern is etched to obtain an initial etched pattern.

[0136] It should be understood that the photolithography process of the present invention can be simulated with the help of a preset algorithm, program or software. For example, an OPC model or an etching model. Specifically, an initial mask and exposure conditions are first provided, and a photoresist pattern can be obtained by simulating the process of simulating imaging processing based on the initial mask under the exposure conditions with the help of the OPC model. Further, the initial etching model can be obtained by etching the photoresist pattern with the help of the etching model. In actual photolithography, it is usually impossible to modify the photoresist pattern, and the final etching pattern can only be viewed by adjusting the exposure conditions, mask parameters or OPC model. However, since the present invention adopts a simulated method for photolithography, the exposure process can be adjusted in real time by adjusting the parameters in the model used, which is simple and convenient.

[0137] Furthermore, in the above step S2, performing the first compensation on the photoresist pattern by using the etching deviation table includes:

[0138] The parameters of the photoresist pattern include spacing and line width. The etching deviation value is obtained through the etching deviation table. The line width of the photoresist pattern and / or the spacing between the photoresist patterns are modified based on the etching deviation value to perform the first compensation on the photoresist pattern.

[0139] It can be understood that the specific steps of modifying the photoresist pattern based on the etching deviation value are: inputting the etching deviation value into the OPC model, and changing the exposure process so that the line width of the photoresist pattern obtained after the simulated imaging process and / or the spacing between the photoresist patterns are modified, thereby completing the first compensation of the photoresist pattern and completing the modification of its morphology. It should be understood that the first compensation can preliminarily eliminate the etching deviation of the photoresist pattern.

[0140] Specifically, after the above step S2, after obtaining the target graphic, the following steps are further included:

[0141] Set a preset standard to determine whether the target pattern on the chip meets the preset standard;

[0142] If not, it indicates that the target pattern is a target pattern with a different local environment, and the target pattern that does not meet the preset standard is directly etched to obtain the final etched pattern;

[0143] If so, it indicates that the target graph is a target graph with the same local environment but a different larger environment.

[0144] If the target pattern does not meet the preset standard, it is a target pattern with different local environments, which means that there is no load effect, and OPC is used to solve the problem of different patterns in local environments. If it meets the preset standard, it means that the target pattern cannot be etched directly, and secondary compensation is required to eliminate the load effect. It should be understood that target patterns with the same local environment and the same larger environment may cause load effects due to process reasons, and such situations are not considered.

[0145] Specifically, when setting the preset standard, a certain position of the initial etching pattern on the chip can be selected, and then it is determined whether there is an initial etching pattern within a preset range outside the position;

[0146] If not, it means that the graphic corresponding to the position does not meet the preset standard, that is, the graphic corresponding to the position is a graphic with the same local environment but different larger environment.

[0147] As a variation, see Figure 2a , Figure 2a Shows a comparison of graphs that have the same local environment but a different larger environment. Figure 2a The chip is divided into n×n grid points, where the grid points represent small square blocks. The preset standard is set to 100 grid points. For example, if the grid point 2A still has the initial etching pattern within the range of 100 grid points, then the pattern corresponding to the grid point A is the pattern with the same local environment and the same larger environment. For another example, please refer to Figure 2b , there is no initial etching pattern at the 51st grid point on the left side of grid point 2B, so the pattern corresponding to grid point 2B is a pattern with the same local environment but different larger environment. It should be understood that the grid points corresponding to the patterns with the same local environment but different larger environment are often prone to appear at locations where the density of the etching pattern on the chip changes significantly.

[0148] The present invention has multiple possible implementations for obtaining the density distribution map of the initial etching pattern:

[0149] In a possible implementation, in the above step S3, obtaining a density distribution map of the initial etching pattern on the chip includes:

[0150] S31, dividing the chip into blocks;

[0151] S32, obtaining the area of ​​the initial etching pattern in a certain block;

[0152] S33, obtaining the initial etching pattern density of the block based on the area of ​​the initial etching pattern in the block and the area of ​​the block;

[0153] S34, obtaining the position of the block, and obtaining a density distribution map of the initial etching pattern on the chip based on the position of the block and the density of the initial etching pattern in the block.

[0154] Understandably, see Figure 3a , Figure 3aA flow chart for obtaining a density distribution map is shown. After the chip is divided into blocks, the area of ​​the initial etching pattern in each block is identified and obtained through a preset recognition module. The area of ​​the initial etching pattern in the block is divided by the area of ​​the block to obtain the density of the initial etching pattern in the block. Further, the position of the block is obtained, and the relationship between the position and the density can be obtained based on the block position and the density of the initial etching pattern in the block, so as to obtain the density distribution map of the initial etching pattern on the chip. This embodiment obtains the density of the initial etching pattern in each block, and then obtains the density distribution map of the initial etching pattern on the chip. The calculation process is simple and the processing efficiency is high. Figure 3b It is a schematic diagram of a density distribution diagram. It should be noted that in the above process of dividing the chip into blocks, the divided blocks can be blocks of equal size, or blocks of different or partially identical sizes, and the size of the blocks obtained by dividing the chip is not specifically limited.

[0155] Please also refer to Figure 3c , obtaining the density distribution map of the initial etching pattern on the chip also includes:

[0156] Duplicate the chip into multiple identical copies;

[0157] Divide each replica map into blocks of equal size, and the sizes of blocks on different replica maps are different;

[0158] Obtain a density distribution map of the initial etched pattern on each replica image.

[0159] It should be understood that in order to enrich the data of the density distribution map, a chip can be copied into multiple copies. Figure 3c As shown, the chip can be copied into a copy image 3A and a copy image 3B. The block size on the copy image 3A is 1000×1000, and the block size on the copy image 3B is 500×500. In the process of dividing the copy image, the block sizes of different copy images are different, that is, the copy images copied from a chip can eventually correspond to multiple density distribution images, enriching the data of the density distribution image.

[0160] In another possible implementation, in the above step S3, obtaining a density distribution map of the initial etching pattern on the chip includes:

[0161] Select a mark point on the initial etching pattern on the chip;

[0162] Select one or at least two preset distances outside the marking point as the marking area;

[0163] Obtaining the area of ​​the initial etching pattern in the marked area;

[0164] Obtaining the density of the initial etching pattern corresponding to the marking point based on the area of ​​the initial etching pattern in the marking area and the area in the marking area;

[0165] The above process of obtaining the density of the initial etching pattern is iterated to obtain a density distribution map of the initial etching pattern on the chip.

[0166] It should be understood that the method used in this embodiment obtains the density of the initial etching pattern at each marking point of the chip, and then obtains the density distribution map of the initial etching pattern on the entire chip, so that the density distribution map is more accurate, but its processing flow is relatively long.

[0167] Furthermore, in the case where it is not S3, the present invention has multiple possible implementations when obtaining the etching deviation map:

[0168] In a possible implementation manner, the density distribution diagram represents the relationship between the pattern position and the density, and after obtaining the density distribution diagram of the initial etching pattern on the chip, the method further includes:

[0169] Set the preset first density change value,

[0170] Determining whether the density difference between adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being greater than a preset first density change value;

[0171] If yes, then obtain the etching pattern corresponding to the position that meets the requirements, and cluster the etching pattern to obtain at least two categories of classification patterns;

[0172] Obtain the location of the etching pattern within the classification pattern for each category;

[0173] The density distribution map of the classification patterns of the same category is obtained based on the position of the etching pattern within the classification patterns of the same category and the density distribution map of the initial etching pattern.

[0174] It is understandable that since the data volume of the density distribution map of the initial etching pattern is too large, if the relationship between the density distribution map of the initial etching pattern and the etching deviation value is directly established, the model itself will not be able to cover a large amount of measurement data. Therefore, this implementation first determines whether the density difference between adjacent positions on the density distribution map of the initial etching pattern meets the requirement of being greater than the preset first density change value. If it meets the requirements, it means that the position that meets the requirements is the position where the density change is obvious on the density distribution map of the initial etching pattern. That is, these positions are more likely to have load effect problems. It should be noted that the position can be understood as an area, and the area of ​​the area is defined based on the same local environment but different larger environments, that is, the area size of the area is defined according to the above-mentioned preset standards. Therefore, there will be a situation where one area corresponds to multiple etching patterns, that is, one position corresponds to multiple etching patterns. Furthermore, the etching patterns corresponding to the positions that meet the requirements are clustered to obtain classified graphics of at least two categories. It should be understood that clustering refers to clustering graphics of the same shape into one category. Exemplarily, Figure 4 Several shapes of graphics are shown, such as "I", "L", "T", "mouth" or "Z". Clustering etching graphics of the same shape can greatly simplify the amount of calculation in the subsequent process, which helps to improve the efficiency of obtaining etching deviation maps. It should be noted that the shapes of the above-mentioned graphics are at least shown as examples, and their specific shapes are not specifically limited. In addition, graphics clustering can be assisted by algorithms, models or programs, and its purpose is to cluster etching graphics of the same type together to achieve the purpose of improving processing efficiency. The specific process of graphics clustering will not be described in detail.

[0175] Furthermore, after the etching patterns that meet the requirements are clustered, the position of the etching patterns in the classification patterns of each category can be obtained. Specifically, similar etching patterns on the chip can be matched according to the shape of the graphic clusters by a graphic matching method until the position of the etching patterns in the classification patterns of each category is obtained. Exemplarily, assuming that there are 100,000 etching patterns on the chip, and finally 1,000 positions meet the requirements, that is, 1,000 positions are screened out, and then the etching patterns in each of the 1,000 positions are clustered. In the clustering process, it is assumed that the clusters form 5 categories. When performing graphic matching on one of the categories, less than or equal to 1,000 positions with the same local environment but different larger environments may be matched in the 1,000 positions. Finally, based on the matched positions in this category and the density distribution map of the initial etching pattern, the density distribution map of the classification pattern of this category can be obtained. It should be noted that pattern matching can be performed with the aid of algorithms, models or programs, and its purpose is to obtain the positions of similar etching patterns and more accurately find the positions of etching patterns with the same local environment. The specific process of pattern matching will not be described in detail.

[0176] As a variation, the process of pattern matching is also omitted, and the position of the etching pattern in the classification pattern of the same category in the pattern cluster is directly obtained. For example, directly matching a certain category of graphics, assuming that 200 positions with the same local environment but different larger environments are matched, then based on the obtained positions and the density distribution map of the initial etching pattern, the density distribution map of the classification pattern of this category can be obtained. The process is simpler after omitting the pattern matching.

[0177] Furthermore, after obtaining the density distribution map of the classification graph, the following steps are also included:

[0178] Setting a preset second density change value;

[0179] Determine whether the density difference between adjacent positions on the density distribution diagram of the classification graphics of the same category is greater than a preset second density change value;

[0180] If so, set the position as a local similarity point;

[0181] Performing etching processing on the target pattern corresponding to the local similar point to obtain the actual etching pattern;

[0182] Obtain the etching deviation value between the actual etching patterns.

[0183] Understandably, directly analyzing the relationship between the density distribution map of the entire initial etching pattern and the etching deviation map will result in a large amount of calculation and a lot of measurement data. In this embodiment, after obtaining the density distribution map of the classification pattern, the relationship between the density distribution map of a certain category of classification patterns and the etching deviation can be analyzed separately, which simplifies the analysis process and improves the efficiency of the analysis.

[0184] Further, it is determined whether the density difference between adjacent positions on the density distribution diagram of the classification graphics of the same category is greater than the preset second density change value. If so, these positions are set as local similar points. It should be understood that the local similar point indicates that the position is a position where the density change is obvious on the density distribution diagram of the classification graphics. That is, these positions are more likely to have load effect problems. Further, the local type points should be graphics with similar shapes. After etching, due to the influence of the load effect, the shape of the actual etched graphics formed after etching is different.

[0185] Furthermore, by obtaining the contour of the actual etched pattern and comparing the contours of different actual etched patterns, the etching deviation value can be obtained. It should be noted that the contour of the etched pattern can be measured with the help of SEM (scanning electron microscope). It should be understood that engineers expect that the actual etched pattern shape after etching of local similar points is the same, so by comparing the contours, the relationship between the density distribution map of the classified pattern and the etching deviation value can be analyzed.

[0186] Understandably, Figure 5 The density distribution diagram of the classification graph is shown. It can be seen that the boxes 5A and 5B represent the positions with large density changes on the classification graph of the same type, and these positions are local similar points. It should be understood that the positions with large density changes on the density distribution diagram of the classification graph are often more prone to the problem of load effect. Therefore, these positions with large density changes are set as local similar points. This embodiment simplifies the difficulty of analyzing the relationship between the density distribution diagram and the etching deviation diagram by screening out local similar points.

[0187] In another possible implementation, the density distribution map represents the relationship between the pattern position and the density, and after obtaining the density distribution map of the initial etching pattern on the chip, the method further includes:

[0188] Select a center point on an initial etched pattern on the chip;

[0189] Taking the outline of the initial etched pattern as the boundary line, a deviation point is selected inside the boundary line and within a preset distance from the boundary line;

[0190] Performing etching processing on the target pattern corresponding to the center point to obtain an etching pattern;

[0191] Performing etching processing on the target pattern corresponding to the deviation point to obtain another etching pattern;

[0192] The two etching patterns are compared to obtain an etching deviation value.

[0193] It should be understood that in this embodiment, the center point of the initial etching pattern is used as the reference. The etching deviation value is obtained by the etching pattern of the center point and the deviation point. Compared with the above embodiment, the advantage of this embodiment is that the steps are simple, and the etching deviation value can be obtained by directly comparing the two points. The disadvantage is that the calculation is complicated and the position on the entire chip needs to be calculated. In addition, since the starting point is random, its accuracy is also poor.

[0194] Furthermore, in the step S4, establishing a mapping relationship between the density distribution map and the etching deviation map includes multiple implementations.

[0195] In a possible implementation manner, calculating and obtaining the corresponding etching deviation map includes:

[0196] An AI model is provided, and the density distribution map of the initial etching pattern on the chip is taken as input. The etching deviation map corresponding to the output density distribution map is calculated by the AI ​​model.

[0197] It can be understood that whether the etching deviation value is calculated by the density distribution map of the classified graphics, or the etching deviation value is calculated directly by the density distribution map of the initial etching graphics, a calculation process must be performed. Specifically, the calculation process can be calculated manually or by algorithm. During the calculation process, the density value of a certain position and its corresponding etching deviation value will be continuously accumulated. When a certain amount of data is accumulated, a large amount of measurement data can be generated to support AI modeling. Specifically, the AI ​​model can be trained with density values ​​and their corresponding etching deviation values. After the AI ​​model is trained, the mapping relationship between the density distribution map and the etching deviation map can be established. At this time, if the density distribution map of the initial etching graphic is used as input, the etching deviation map corresponding to the output density distribution map can be directly calculated with the help of the AI ​​model. It is simple and convenient.

[0198] Exemplarily, the chip is copied into multiple identical copy images; the copy images are divided into blocks of equal size of 1um, 5um, and 10um respectively; the density distribution maps of the above multiple blocks of different sizes are obtained, and the multiple density distribution maps are used as input of the AI ​​model to output an etching deviation map. Figure 6 An etching deviation map is shown. The blocks on the etching deviation map represent the positions, and the data in the blocks represent the etching deviation values ​​corresponding to the positions. It should be understood that the present embodiment uses an AI model to establish a mapping relationship between a density distribution map and an etching deviation map. In practical applications, the etching deviation map can be directly given according to the density distribution map of the etching pattern, which is simple and convenient. In addition, when establishing an etching deviation table, excessive manual intervention is required to continuously measure the etching pattern, and the overall efficiency is relatively low. It is also not conducive to obtaining data by measuring a large number of etching patterns on silicon wafers to improve the accuracy of the mapping relationship between the density distribution map and the etching deviation map. The AI ​​model used in this embodiment, the principle itself input is usually multiple input matrices (input matrix), and the output is a single point (point of interest). Therefore, the AI ​​model is innovatively applied to establish a mapping relationship between a density distribution map and an etching deviation map, which can greatly improve the accuracy of the mapping relationship, and at the same time, the high computing power of AI can also speed up the efficiency of calculation.

[0199] In another possible implementation, calculating the etching bias value corresponding to the density includes: fitting the polynomial relationship between the etching bias value and its corresponding multiple density values, and establishing a load bias model (bias loading mode). It should be understood that the input of the load bias model established in this implementation is the density value of a certain position, and the output is the etching bias of the position. Compared with the implementation of the AI ​​model, the advantage of this implementation is the fast calculation speed, and the disadvantage is that the ability to fit using a polynomial relationship is limited. Even if the fitting ability of the polynomial is limited, even if the load bias model is subsequently established, the model itself still has a large residual. If the load bias model is subsequently used to compensate the target graphic, the accuracy of the compensation process is not enough. In addition, the framework of the load bias model itself cannot cover a large amount of measurement data.

[0200] Furthermore, in the above step S5, performing a second compensation on the target graphic based on the mapping relationship includes:

[0201] The target graphics include spacing and line width;

[0202] Performing etching processing on the target pattern to obtain its corresponding target etching pattern;

[0203] Obtaining a density distribution map of a target etching pattern on a chip, and obtaining an etching deviation map based on the density distribution map of the target etching pattern and a mapping relationship;

[0204] The exposure process is optimized based on the etching deviation map to modify the line width of the target pattern and / or the spacing between the target patterns, and complete the second compensation of the target pattern.

[0205] It should be understood that the etching deviation map corresponding to the density distribution map at the current target graphic can be obtained through the mapping relationship. And through the etching deviation map, the exposure process can be optimized. Specifically, the purpose of the second compensation is also to modify the morphology of the target graphic. That is, to modify the line width of the target graphic and / or the spacing between the target graphics. Further, when the target graphic is compensated for the second time to become an optimized graphic, the optimized graphic has taken into account the load effect during the etching process. The principle is to change the morphology of the same target graphic into an optimized graphic with a different morphology, and then etch the optimized graphic. Since the optimized graphic has taken into account the load effect, the final etching graphic generated by its etching is closer to the expected.

[0206] Furthermore, please combine Figure 1a and Figure 1b , etching the optimized pattern in the above step S6 includes:

[0207] S61, providing a local etching model, and using the local etching model to etch the optimized pattern obtained after the second compensation to obtain a final etching pattern;

[0208] S62, determining whether there is an etching deviation in the final etching pattern;

[0209] S63, if it exists, iterating the optimized graph as the target graph;

[0210] S64, until the finally obtained etching pattern has no etching deviation, the finally obtained etching pattern is output.

[0211] It is understandable that in the actual etching process, even if the target pattern is compensated according to the etching deviation map to obtain an optimized pattern, it cannot be fully guaranteed that the final etched pattern obtained after etching the optimized pattern can achieve the effect expected by the engineer. Because the load effect is only a part of the many effects in etching. The prerequisite for fully achieving the expected effect is that other effects that appear in the etching process have been completely eliminated by the first compensation and the second compensation. Of course, at least in an ideal state, the two compensation processes can only eliminate the load effect, but cannot completely eliminate the CDU problem. Therefore, the current solution can only alleviate the CDU problem caused by the load effect in principle. It should be understood that the present invention provides a local etching model, and uses the local etching model to etch the optimized pattern obtained after the second compensation to obtain the final etching pattern. It should be noted that the local etching model can well eliminate other effects and avoid the influence of other effects on the etching process, so that the finally obtained etching pattern can well eliminate the CDU problem.

[0212] Further, after obtaining the final etching pattern, it is determined whether the final etching pattern has an etching deviation; if so, the optimized pattern is iterated as the target pattern until the final etching pattern does not have an etching deviation, and the final etching pattern is output. It should be understood that the present invention also introduces a mechanism loading proximity correction (Loading Proximity Correction, also known as LPC) mechanism. The general process applied to the actual photolithography in the present invention is as follows: designing the layout, exposing to obtain the photoresist pattern, etching to obtain the initial etching pattern, performing the first compensation for the photoresist pattern corresponding to the initial etching pattern according to the etching deviation table, calculating the density distribution map of the initial etching pattern, obtaining the etching deviation map based on the density distribution map, performing the second compensation based on the etching deviation map, applying the local etching model, and obtaining the final etching pattern. It should be understood that the final etching pattern obtained may still have a CDU problem in the later stage. At this time, the density distribution map of the final etching pattern can be obtained, and the steps of performing the second compensation based on the etching deviation map are iterated to continuously optimize it until the final etching pattern that meets the expectations is output after the CDU problem is eliminated. That is, the density distribution map of the final etching pattern is re-substituted into the AI ​​model to obtain the etching deviation map, and the second compensation process based on the etching deviation map can continuously optimize the results.

[0213] For example, assuming that the photoresist pattern is pattern P1, after the first compensation it becomes pattern P2, and after the second compensation it becomes pattern P3. After etching P3, it is found that the etched pattern corresponding to pattern P3 still has a CDU problem, then a second compensation is performed on pattern P3 to obtain P4. If the etched pattern corresponding to pattern P4 does not have a CDU problem, then pattern P4 is output.

[0214] It should be noted that the multiple implementation methods provided in each step of the method for improving the uniformity of key dimensions of etched patterns on a chip provided by the present invention can be freely combined, and the specific combination method is not limited.

[0215] Exemplarily, the present invention can adopt a combination of density distribution map, graph clustering and graph matching to obtain an etching deviation map, and generate an AI model by combining the collected density distribution map and etching deviation map data with an AI modeling method, thereby significantly improving the expressiveness of the AI ​​model and reducing the residual error of the model. Furthermore, the present invention can add a local etching model on the basis of a second compensation through an etching deviation map, and construct an iterative optimization LPC mechanism similar to the OPC iterative optimization mask on the basis of obtaining the final etching pattern to iteratively optimize the CDU problem of the final etching pattern, thereby directly and more thoroughly solving the CDU problem.

[0216] See also Figure 7 The second embodiment of the present invention further provides a system 1 for improving the uniformity of critical dimensions of etching patterns on a chip, the system 1 comprising:

[0217] OPC module 11: used for performing analog imaging processing to obtain photoresist patterns;

[0218] Etching module 12: used for etching the photoresist pattern to obtain an initial etching pattern;

[0219] Identification module 13: used to obtain a density distribution map of the initial etching pattern on the chip;

[0220] Calculation module 14: used to calculate and obtain an etching deviation map corresponding to the initial etching pattern;

[0221] AI module 15: used to establish a mapping relationship between a density distribution map and an etching deviation map;

[0222] Processing module 16: used for performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern, and performing a second compensation on the target pattern based on the mapping relationship to obtain an optimized pattern;

[0223] Output module 17: used for outputting the final etching pattern.

[0224] The embodiment of the present invention further provides a system 1, which can be applied to the above method for improving the uniformity of key dimensions of etched patterns on chips, and has the same beneficial effects as the above method for improving the uniformity of key dimensions of etched patterns on chips, which will not be described in detail here.

[0225] The third embodiment of the present invention also provides a computer device 2, which is applied to the method for improving the uniformity of key dimensions of etched patterns on chips as mentioned above, including a memory 21, a processor 22 and a computer program 23 stored in the memory 21, and the processor 22 executes the computer program 23 to implement the method for improving the uniformity of key dimensions of etched patterns on chips.

[0226] The embodiment of the present invention further provides a computer device 2, which has the same beneficial effects as the above-mentioned method for improving the uniformity of key dimensions of etched patterns on a chip, and will not be described in detail here.

[0227] In order to solve the above technical problems, the fourth embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer device to execute the above method for improving the uniformity of key dimensions of etched patterns on chips.

[0228] It should be noted that a computer-readable storage medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may be a machine-readable signal medium or a machine-readable storage medium. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. More specific examples of computer-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0229] The above is a detailed introduction to a method, system and device for improving the uniformity of key dimensions of etched graphics on chips disclosed in an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention, and any modifications, equivalent substitutions and improvements made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for improving the uniformity of key dimensions of etched patterns on a chip, characterized by: The following steps are involved: Obtaining an initial etching pattern on the chip, and extracting a photoresist pattern corresponding to the initial etching pattern; Providing an etching deviation table, after extracting the photoresist pattern, performing a first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern; Obtaining a density distribution map of an initial etching pattern on a chip and obtaining a corresponding etching deviation map; Establishing a mapping relationship between a density distribution map and an etching deviation map; Performing a second compensation on the target graph based on the mapping relationship to obtain an optimized graph; The optimized pattern is etched to obtain a final etched pattern.

2. The method for improving the uniformity of critical dimensions of etching patterns on a chip according to claim 1, characterized in that: The first compensation of the photoresist pattern through the etching deviation table includes: The parameters of the photoresist pattern include spacing and line width. The etching deviation value is obtained through the etching deviation table. The line width of the photoresist pattern and / or the spacing between the photoresist patterns are modified based on the etching deviation value to perform the first compensation on the photoresist pattern.

3. The method for improving the uniformity of critical dimensions of etching patterns on a chip according to claim 1, characterized in that: Obtaining the density distribution map of the initial etched pattern on the chip includes: Divide the chip into blocks; Get the area of ​​the initial etching pattern in a certain block; Obtaining an initial etching pattern density of the block based on the area of ​​the initial etching pattern in the block and the area of ​​the block; The position of the block is obtained, and the density distribution map of the initial etching pattern on the chip is obtained based on the position of the block and the density of the initial etching pattern in the block.

4. The method for improving the uniformity of critical dimensions of etching patterns on a chip as claimed in claim 3, characterized in that: After obtaining the density distribution map of the initial etching pattern on the chip, it also includes: Set the preset first density change value, Determining whether the density difference between adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being greater than a preset first density change value; If yes, then obtain the etching pattern corresponding to the position that meets the requirements, and cluster the etching pattern to obtain at least two categories of classification patterns; Obtain the location of the etching pattern within the classification pattern for each category; The density distribution map of the classification patterns of the same category is obtained based on the position of the etching pattern within the classification patterns of the same category and the density distribution map of the initial etching pattern.

5. The method for improving the uniformity of critical dimensions of etching patterns on a chip as claimed in claim 4, characterized in that: After obtaining the density distribution map of the classification graphics, it also includes: Set the preset second density change value, Determine whether the density difference between adjacent positions on the density distribution diagram of the classification graphics of the same category is greater than a preset second density change value; If so, set the position as a local similarity point; Performing etching processing on the target pattern corresponding to the local similar point to obtain the actual etching pattern; Obtain the etching deviation value between the actual etching patterns.

6. The method for improving the uniformity of critical dimensions of etching patterns on a chip according to claim 1, characterized in that: Calculating and obtaining the corresponding etching deviation map includes: An AI model is provided, and the density distribution map of the initial etching pattern on the chip is taken as input. The etching deviation map corresponding to the output density distribution map is calculated by the AI ​​model.

7. The method for improving the uniformity of critical dimensions of etching patterns on a chip according to claim 1, characterized in that: The second compensation of the target graphics based on the mapping relationship includes: The target graphics include spacing and line width; Performing etching processing on the target pattern to obtain its corresponding target etching pattern; Obtaining a density distribution map of a target etching pattern on a chip, and obtaining an etching deviation value based on the density distribution map of the target etching pattern and a mapping relationship; The line width of the target pattern and / or the spacing between the target patterns are modified based on the etching deviation value to perform a second compensation on the target pattern.

8. The method for improving the uniformity of critical dimensions of etching patterns on a chip according to claim 6, characterized in that: Etching the optimized pattern includes: Providing a local etching model, and using the local etching model to etch the optimized pattern obtained after the second compensation to obtain a final etching pattern; Determine whether there is etching deviation in the final etching pattern; If it exists, the optimized pattern is taken as the target pattern for iteration until the etching pattern finally obtained does not have etching deviation, and the etching pattern finally obtained is output.

9. A system for improving the uniformity of critical dimensions of etched patterns on a chip, characterized by: The system comprises: OPC module: used to perform analog imaging processing to obtain photoresist patterns; Etching module: used for etching the photoresist pattern to obtain the initial etching pattern; Identification module: used to obtain the density distribution map of the initial etching pattern on the chip; Calculation module: used to calculate and obtain the etching deviation map corresponding to the initial etching pattern; AI module: used to establish the mapping relationship between density distribution map and etching deviation map; Processing module: used for performing a first compensation on the photoresist pattern through an etching deviation table to obtain a target pattern after the photoresist pattern is extracted, and performing a second compensation on the target pattern based on a mapping relationship to obtain an optimized pattern; Output module: used to output the final etching pattern.

10. A computer device, applied to the method for improving the uniformity of critical dimensions of etching patterns on a chip as claimed in any one of claims 1 to 8, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to realize the method for improving the uniformity of the key dimension of the etched pattern on the chip.

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