A fast-start crystal oscillator circuit

Abstract

The present invention belongs to the technical field of radio frequency chips, and specifically relates to a fast-starting crystal oscillator circuit, including a crystal oscillator core circuit, an automatic amplitude control circuit, an output buffer circuit, a startup circuit, a counter, a clock source calibration logic circuit, and a logic circuit. The present invention designs a startup circuit to excite the crystal circuit with a clock having the same resonant frequency as the crystal, and automatically increases the current of the crystal core circuit when the crystal is started, the size of the amplifier tube, and reduces the crystal load capacitance in the startup phase of the crystal circuit to improve the crystal amplification gain in the startup phase, thereby reducing the crystal startup time by up to 70%. The clock source signal of the startup circuit is reused to initialize the clock source of the chip when the radio frequency chip just starts working, thereby greatly reducing the startup time and power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency chips, and in particular relates to a fast-starting crystal oscillator circuit. Background Art

[0002] Most of the existing crystal circuits use analog automatic amplitude control circuits (such as Figure 1 As shown in the figure, when the crystal starts to work, the current Ibias of the crystal circuit is automatically adjusted through the automatic amplitude control circuit to speed up the start-up time of the crystal oscillator circuit. The start-up time of the current technology crystal oscillator circuit is greater than 1 second for 32.768KHZ crystals and greater than 1 millisecond for 8MHZ crystal circuits.

[0003] The start-up time of the existing crystal is too slow. In the low-power RF system, the chip system works periodically. Therefore, each time the chip switches from sleep mode to working mode, the crystal must go through the process of switching from shutdown mode to working mode. If the start-up time of the crystal is too slow, the power consumption of the system will increase. In addition, when the crystal starts to work, the oscillation amplitude of xo_n and xo_p at both ends of the crystal is very small. Figure 1 The signal quality of the clock clk_out is very poor, for example, the duty cycle of the signal clk_out is very poor, and even clk_out has glitches. Summary of the invention

[0004] The purpose of the present invention is to provide a fast-starting crystal oscillator circuit, which accelerates the start-up time of the crystal circuit by designing some auxiliary oscillator circuits, and another oscillator source signal provides a temporary signal source for the system operation, so as to fully reuse the system initialization time from sleep to work. In this way, the power consumption of the radio frequency system is optimized, and by counting the crystal output signal, a qualified clock is output after the crystal clock is stable, so as to solve the problem that the prior art is not only inefficient but also wastes a lot of manpower in the above background technology.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: a fast-start crystal oscillator circuit, comprising: a crystal oscillator core circuit, including crystal connection terminals xo_n and xo_p; an automatic amplitude control circuit, connected to the xo_p, for detecting the crystal oscillation amplitude and controlling the current Ibias of the crystal circuit; a startup circuit, connected to the xo_p, for generating a signal close to the crystal resonant frequency during the startup phase to stimulate the crystal to start oscillating quickly; an output buffer circuit, connected to the xo_p, for amplifying the xo_p signal into a square wave; a counter, connected to the output terminal buff_out of the output buffer circuit, for counting the number of cycles of the buff_out signal; a clock source calibration logic circuit, for adjusting the output frequency of the clock source inside the startup circuit to match the crystal oscillation frequency.

[0006] It also includes a selector, which includes a first input terminal, a second input terminal and a control terminal; the first input terminal receives the output signal boot_clk of the startup circuit, the second input terminal receives the output signal XT_out of the output buffer circuit, and the control terminal receives the clock switching control signal CLK_SEL.

[0007] It also includes an AND gate, whose input end is respectively connected to the output end buff_out of the output buffer circuit and the delay circuit, and whose output end is connected to the first input end of the selector.

[0008] It also includes a delay circuit, whose input end is connected to the output end En_clk_ctl of the counter, and is used to perform delay processing on the En_clk_ctl.

[0009] It also includes a D trigger, whose D terminal and CLR terminal both receive the En_clk_ctl, the CK terminal receives the boot_clk signal processed by the inverter, and the Q terminal outputs a signal to the control terminal of the selector.

[0010] Preferably, the crystal oscillator core circuit includes an NMOS tube NM2 as an amplifier tube, a resistor R0 is connected between the gate and drain of NM2, the gate of NM2 is also connected to one end of a capacitor c0 and one end of a capacitor c1, the other end of c1 is grounded, the other end of c0 is connected to the drain of the NMOS tube NM1, the source of NM1 is grounded, and the gate of NM1 is controlled by st_ctl;

[0011] It also includes NMOS tubes NM3, NM5 and NM4, the gate of NM3 is connected to xo_p, the drain is connected to the source of NM5, the source of NM3 is grounded, the gate of NM5 is controlled by the reverse control signal ctl_n of st_ctl, and the drain of NM5 is connected to xo_n; the gate of NM4 is controlled by st_ctl, the source is grounded, the drain is connected to one end of the capacitor C3, and the other end of C3 is connected to xo_n; and

[0012] PMOS tubes PM0, PM1, PM2 and PM3, the drain of PM2 is connected to xo_n as a fixed bias current source, the gate of PM3 is controlled by st_ctl, and the drain is connected to xo_n. The gates of PM0, PM1, PM2 and the drain of PM0 are connected together and connected to one end of the bias current IS, the other end of IS is grounded, the sources of PM0, PM1, PM2 are connected to the power supply, and the drain of PM1 is connected to the source of PM3;

[0013] Among them, St_ctl comes from the output of the counter. When the counter counts the Buff_out clock signal for a preset counting cycle, St_ctl changes from "0" to "1".

[0014] Preferably, the startup circuit includes: an RC oscillator, used to generate a target frequency clock boot_clk that matches the crystal resonant frequency; a NAND gate nand1, whose input end is connected to the boot_clk; a plurality of D flip-flops d1-d6 connected in series, used to generate a control signal, wherein the D output end of d6 is connected to a power supply, the output Q- of d6 is connected to the input of the NAND gate nand1, and when the clock input of d6 jumps from low to high, the NAND gate nand1 outputs a fixed high level, and the output of the nand1 NAND gate is connected to two inverters not1 and not2; the output Ck_1 of the inverter not2 is connected to the clock end of the D flip-flop d1, the Q- of d1 is connected to its own D end, and the Q- is connected to the clock end of the next D flip-flop; the reset clear ends CLR of the plurality of D flip-flops all receive a CLR clear signal, which is used to reset the D flip-flops when the crystal is not working.

[0015] Preferably, the clock source calibration logic circuit outputs f_ctl<7:0> frequency adjustment control bits for adjusting the output frequency of the internal clock source of the startup circuit to match the crystal clock frequency.

[0016] Preferably, the output buffer circuit includes an input DC isolation capacitor Cb0, an inverter INVb1, a resistor Rb0 and an inverter INVb2, wherein the resistor Rb0 is connected between the input and output of INVb1, and the output of INVb2 is connected to buff_out. xo_p is connected to the positive end of the input DC isolation capacitor Cb0, the other end of the capacitor Cb0 is connected to the input end of the inverter INVb1, the resistor Rb0 is connected between the input and output of the inverter INVb1, the output of the inverter INVb1 is connected to the input end of the inverter INVb2, and the output of INVb2 is connected to the output end of buff_out.

[0017] Preferably, the selector outputs the output signal boot_clk of the startup circuit when En_clk_ctl is "0", and outputs the output signal XT_out of the output buffer circuit when En_clk_ctl is "1".

[0018] Technical effects and advantages of the present invention: Compared with the prior art, the fast-start crystal oscillator circuit proposed by the present invention has the following advantages:

[0019] The present invention reduces the crystal startup time by up to 70% by designing a startup circuit to excite the crystal circuit with a clock having the same resonant frequency as the crystal, and automatically increases the current of the crystal core circuit and the size of the amplifier tube when the crystal is started, and reduces the crystal load capacitance in the startup phase of the crystal circuit to improve the crystal amplification gain in the startup phase. The clock source signal of the startup circuit is reused to initialize the clock source of the chip when the radio frequency chip just starts working, thereby greatly reducing the startup time and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A circuit diagram of a crystal oscillator circuit in the prior art;

[0021] Figure 2 A circuit diagram of the crystal oscillator overall circuit of the present invention;

[0022] Figure 3 A circuit diagram of the crystal oscillator core circuit of the present invention;

[0023] Figure 4 is a circuit diagram of an output buffer circuit of the present invention;

[0024] Figure 5 A circuit diagram of a starting circuit of the present invention;

[0025] Figure 6 This is the main signal waveform diagram of the crystal oscillator circuit of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] The present invention provides a fast-start crystal oscillator circuit, such as Figure 2 As shown, the crystal oscillator circuit includes: a crystal oscillator core circuit, an automatic amplitude control circuit, a startup circuit, an output buffer circuit, a counter, a clock source calibration logic circuit, a selector, an AND gate, a delay circuit and a D flip-flop.

[0028] In this embodiment, the crystal oscillator core circuit includes crystal connection terminals xo_n and xo_p.

[0029] In this embodiment, an automatic amplitude control circuit is connected to the xo_p to detect the crystal oscillation amplitude and control the current Ibias of the crystal circuit.

[0030] In this embodiment, the startup circuit is connected to the xo_p and is used to generate a signal close to the crystal resonant frequency during the startup phase to stimulate the crystal to oscillate quickly.

[0031] In this embodiment, an output buffer circuit is connected to the xo_p to amplify the xo_p signal into a square wave.

[0032] In this embodiment, a counter is connected to the output terminal buff_out of the output buffer circuit, and is used to count the number of cycles of the buff_out signal.

[0033] In this embodiment, the clock source calibration logic circuit is used to adjust the output frequency of the clock source inside the startup circuit to match the crystal oscillation frequency.

[0034] In this embodiment, the selector includes a first input terminal, a second input terminal and a control terminal; the first input terminal receives the output signal boot_clk of the startup circuit, the second input terminal receives the output signal XT_out of the output buffer circuit, and the control terminal receives the clock switching control signal CLK_SEL.

[0035] In this embodiment, the input end of the AND gate is connected to the output end buff_out of the output buffer circuit and the delay circuit respectively, and the output end is connected to the first input end of the selector.

[0036] In this embodiment, the input end of the delay circuit is connected to the output end En_clk_ctl of the counter, and is used to perform delay processing on the En_clk_ctl.

[0037] In this embodiment, the D-terminal and CLR-terminal of the D-type flip-flop both receive the En_clk_ctl, the CK-terminal receives the boot_clk signal processed by the inverter, and the Q-terminal outputs a signal to the control-terminal of the selector.

[0038] The specific embodiments are as follows:

[0039] like Figure 2 As shown, xo_n and xo_p of the crystal oscillator core circuit are connected to the crystal.

[0040] Among them, xo_p is also connected to the input of the automatic amplitude control circuit to detect the oscillation amplitude of the crystal, thereby controlling the size of the output current Ibias of the automatic amplitude control circuit. xo_p is also connected to the output of the startup circuit.

[0041] Furthermore, the startup circuit is the core. When the circuit starts working, it stimulates the crystal to start quickly by outputting a signal with a frequency close to the crystal resonant frequency. The xo_p output is connected to the input of the output buffer circuit. The buffer circuit amplifies the xo_p signal into a square wave and outputs it to buff_out. buff_out is connected to the input of the AND gate and the input of the counter.

[0042] Furthermore, the function implemented by the counter is to count the clock input to buff_out, and the number of counts is configurable according to the crystal. After counting 1024 cycles, this design uses a high level for st_ctl to turn off the PM3 and NM5 tubes of the crystal oscillation core circuit, and turn on the NM1 and NM4 tubes, so that the capacitance at both ends of the crystal is at the normal required load capacitance. During the crystal start-up phase, the crystal oscillation core circuit reduces the crystal load capacitance and increases the crystal bias current and amplifier tube to reduce the crystal start-up time.

[0043] Specifically, after the counter counts 1536 clock cycles, the output En_clk_ctl of the counter outputs a high level. After passing through the delay circuit and delaying for about 3 clocks, En_clk_ctl is connected to the input of the AND gate to enable the clock output of the crystal.

[0044] En_clk_ctl is also connected to the D terminal and CLR terminal of the D flip-flop D_lock, and the Boot_clk signal is connected to the CK terminal of the D flip-flop D_lock through the inverter NOT_0. The Q output terminal of the D flip-flop D_lock is connected to the control terminal of the selector and the clock switching control signal CLK_SEL.

[0045] The output XT_out of the AND gate is connected to a signal input terminal of the selector, and another signal input terminal of the selector is connected to boot_clk output by the startup circuit.

[0046] When En_clk_ctl=“0”, the selector's signal switching control signal CLK_SEL causes the dual-way selector to output the boot_clk signal.

[0047] When En_clk_ctl = "1", the signal switching control signal CLK_SEL causes the dual selector to output the XT_out signal. That is, before the crystal circuit works stably, the crystal circuit outputs the boot clock boot_clk signal output by the boot circuit for system initialization. When the crystal works stably, it switches to the crystal clock.

[0048] Figure 2 The function implemented by the clock source calibration logic circuit of the circuit shown is to use the crystal clock as the reference frequency, and to make the clock frequency of the output boot_clk of the clock source in the startup circuit match the crystal clock frequency by outputting the f_ctl<7:0> frequency adjustment control bit. The closer the clock frequency of boot_clk is to the crystal clock frequency, the larger the initial signal of the crystal resonance is, and the shorter the start-up time of the crystal oscillator circuit is.

[0049] Crystal core circuit such as Figure 3As shown: NM2NMOS tube is the amplifier tube of the crystal oscillator circuit, and a resistor R0 is connected between its gate xo_p and drain xo_n. The xo_p node is also connected to capacitors c0 and c1. The other end of c1 is grounded, and the other end of c0 is connected to the drain of NMOS tube NM1. Its source is grounded, and the gate of NM1 is controlled by st_ctl.

[0050] The gate of NM3 is connected to xo_p, and its drain is connected to the source of NM5. The gate of NM5 is controlled by the reverse control signal ctl_n of st_ctl, and the drain of NM5 is connected to xo_n. Capacitors C2 and C3 are connected to the input and output node xo_n, and the other end of capacitor C2 is grounded.

[0051] The other end of C3 is connected to the drain of NMOS tube NM4, the source of NM4 is grounded, and the gate of NM4 is controlled by the control signal st_ctl. PMOS tubes PM0, PM1, and PM2 form a current mirror tube, in which the drain of PM1 is connected to the source of PM3, the drain of PM3 is connected to the node xo_n, and the gate of PM3 is controlled by the control signal st_ctl. The drain of PM2 is connected to the node xo_n, which serves as a fixed bias current of the crystal oscillator core circuit.

[0052] The bias current of PM2 is the bias current driven by the oscillation circuit. During the startup phase of the crystal oscillation circuit, the output current is given to the amplifier tube NM2.

[0053] When the crystal outputs a sufficiently large clock signal, st_ctl changes from "0" to "1" to turn off PM3, thereby turning off the startup current. At the same time, the added startup amplifier NM3 will also be turned off by turning off NM5. Capacitors C0 and C3 will also change from extremely small capacitance to the rated capacitance value of C0 and C4 themselves due to the conduction of NM1 and NM4.

[0054] Output buffer circuit such as Figure 4 As shown: its input is connected to xo_p, which is cascaded with input DC blocking capacitor Cb0, inverter INVb1, resistor Rb0 between input and output of inverter INVb1, and inverter INVb2. The output of INVb2 is connected to buff_out.

[0055] The startup circuit is the core of the crystal oscillator circuit's quick startup. Its design principle is: a common crystal oscillator amplifies the noise in the circuit into a clock signal through the crystal's frequency selection characteristics, which is equal to the crystal's resonant frequency.

[0056] In this embodiment, a calibrated RC oscillator is designed in the startup circuit as the clock source. The deviation between its calibrated frequency and the oscillation frequency of the crystal is controlled within 1%. Each time the crystal oscillator circuit works normally, the RC oscillator circuit will be calibrated to ensure that the clock source outputs a clock with a sufficiently accurate frequency the next time the crystal is started. The clock source calibration logic circuit is a control circuit that realizes the calibration of the clock source frequency.

[0057] Startup circuit such as Figure 5 As shown, the clock source outputs the target frequency clock boot_clk connected to the nand1 NAND gate, and boot_clk outputs to Figure 2 Selector for the system clock signal when the crystal oscillator circuit is started.

[0058] The output of nand1 is connected to two inverters not1 and not2. The output of inverter not2 is connected to capacitor Ct0, and the other end of Ct0 is connected to xo_p. The output Ck_1 of inverter not2 is connected to the clock end of D flip-flop d1. D flip-flops d1, d2, d3, d4, and d5 form a cascade counter, that is, the Q- of each D flip-flop is connected to its own D end, and Q- is connected to the clock end of the next D flip-flop. The Q- of D flip-flop d5 is connected to the clock end of D flip-flop d6, and the D output end of d6 is connected to the power supply.

[0059] The output Q- of d6 is connected to the input of the NAND gate nand1. When the clock input of d6 jumps from low to high, the NAND gate nand1 outputs a fixed high level. Thus, one end of the capacitor Ct0 is pulled to the ground through the inverter not2. The reset and clear terminals CLR of the D flip-flops d1, d2, d3, d4, d5, and d6 are all connected to the CLR clear signal. When the crystal is not working, CLR is "0", that is, the D flip-flop is reset and cleared. When the crystal oscillator circuit is working, it is "1", and the D flip-flop works normally.

[0060] D flip-flops d1, d2, d3, d4, d5, and d6 form a short-time control signal that controls the clock source to excite the crystal. That is, when the crystal oscillator circuit is enabled and starts working, the startup circuit will excite 16 signals on xo_p that are almost the same as the target crystal's resonant frequency to excite the crystal to start quickly. Figure 6 Shown is the main signal waveform of the crystal oscillator circuit.

[0061] In summary, the present invention reduces the crystal startup time by up to 70% by designing a startup circuit to excite the crystal circuit with a clock having the same resonant frequency as the crystal, and automatically increases the current of the crystal core circuit when the crystal is started, the size of the amplifier tube, and reduces the crystal load capacitance of the crystal circuit during the startup phase to improve the crystal amplification gain during the startup phase, and reuses the clock source signal of the startup circuit to initialize the clock source of the chip when the radio frequency chip just starts working, thereby greatly reducing the startup time and power consumption.

[0062] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A fast-start crystal oscillator circuit, characterized in that: include: A crystal oscillator core circuit, including crystal connection terminals xo_n and xo_p; An automatic amplitude control circuit, connected to the xo_p, for detecting the crystal oscillation amplitude and controlling the current Ibias of the crystal circuit; A startup circuit, connected to the xo_p, is used to generate a signal close to the crystal resonant frequency during the startup phase to stimulate the crystal to oscillate quickly; An output buffer circuit, connected to the xo_p, for amplifying the xo_p signal into a square wave; A counter connected to the output terminal buff_out of the output buffer circuit, and used for counting the number of cycles of the buff_out signal; A clock source calibration logic circuit is used to adjust the output frequency of the clock source inside the startup circuit to match the crystal oscillation frequency; Also includes a selector, the selector includes a first input terminal, a second input terminal and a control terminal; The first input terminal receives the output signal boot_clk of the startup circuit, the second input terminal receives the output signal XT_out of the output buffer circuit, and the control terminal receives the clock switching control signal CLK_SEL; It also includes an AND gate, whose input end is respectively connected to the output end buff_out of the output buffer circuit and the delay circuit, and whose output end is connected to the first input end of the selector; It also includes a delay circuit, whose input end is connected to the output end En_clk_ctl of the counter, and is used for delaying the En_clk_ctl.

2. A fast-start crystal oscillator circuit according to claim 1, characterized in that: It also includes a D trigger, whose D terminal and CLR terminal both receive En_clk_ctl, the CK terminal receives the boot_clk signal processed by the inverter, and the Q terminal outputs a signal to the control terminal of the selector.

3. A fast-start crystal oscillator circuit according to claim 2, characterized in that: The crystal oscillator core circuit includes an NMOS tube NM2 as an amplifier tube, a resistor R0 is connected between the gate and drain of NM2, the source of NM2 is grounded, the gate of NM2 is also connected to one end of the capacitor c0 and one end of the capacitor c1, the other end of c1 is grounded, the other end of c0 is connected to the drain of the NMOS tube NM1, the source of NM1 is grounded, and the gate of NM1 is controlled by st_ctl; It also includes NMOS tubes NM3, NM5 and NM4, the gate of NM3 is connected to xo_p, the drain is connected to the source of NM5, the source of NM3 is grounded, the gate of NM5 is controlled by the reverse control signal ctl_n of st_ctl, and the drain of NM5 is connected to xo_n; the gate of NM4 is controlled by st_ctl, the source is grounded, the drain is connected to one end of the capacitor C3, and the other end of C3 is connected to xo_n; and PMOS tubes PM0, PM1, PM2 and PM3, the drain of PM2 is connected to xo_n as a fixed bias current source, the gate of PM3 is controlled by st_ctl, and the drain is connected to xo_n; the gates of PM0, PM1, PM2 and the drain of PM0 are connected together and connected to one end of the bias current IS, the other end of IS is grounded, the sources of PM0, PM1, PM2 are connected to the power supply, and the drain of PM1 is connected to the source of PM3; Among them, st_ctl comes from the output of the counter. When the counter counts the Buff_out clock signal for a preset counting cycle, st_ctl changes from "0" to "1".

4. A fast-start crystal oscillator circuit according to claim 3, characterized in that: The startup circuit comprises: RC oscillator, used to generate the target frequency clock boot_clk matching the crystal resonant frequency; A NAND gate nand1, a first input terminal of which is connected to the boot_clk; A plurality of D flip-flops d1-d6 connected in series are used to generate control signals, wherein the D output terminal of d6 is connected to a power supply, the Q- terminal of d6 is connected to the second input terminal of the NAND gate nand1, when the clock input of d6 jumps from low to high, the NAND gate nand1 outputs a fixed high level, and the output of the NAND gate nand1 is connected to two inverters not1 and not2; the output Ck_1 of the inverter not2 is connected to the clock terminal of the D flip-flop d1, the Q- of d1 is connected to its own D terminal, and the Q- is connected to the clock terminal of the next D flip-flop, and the inverter not1 is connected to the xo_p; The reset and clearing terminals CLR of the plurality of D flip-flops all receive a CLR clearing signal, and are used to reset the D flip-flops when the crystal is not working; The clock source calibration logic circuit outputs f_ctl<7:0> frequency adjustment control bits for adjusting the output frequency of the internal clock source of the startup circuit to match the crystal clock frequency.

5. A fast-start crystal oscillator circuit according to claim 4, characterized in that: The output buffer circuit includes an input DC blocking capacitor Cb0, an inverter INVb1, a resistor Rb0 and an inverter INVb2, wherein the resistor Rb0 is connected between the input and output of INVb1, and the output of INVb2 is connected to buff_out; xo_p is connected to one end of the input DC blocking capacitor Cb0, and the other end of the capacitor Cb0 is connected to the input end of the inverter INVb1, the resistor Rb0 is connected between the input and output of the inverter INVb1, the output of the inverter INVb1 is connected to the input end of the inverter INVb2, and the output of INVb2 is connected to the output end of buff_out.

6. A fast-start crystal oscillator circuit according to claim 5, characterized in that: The selector outputs the output signal boot_clk of the boot circuit when En_clk_ctl is “0”, and outputs the output signal XT_out of the output buffer circuit when En_clk_ctl is “1”.

Images