Display Panel

Abstract

An embodiment of the present application discloses a display panel. The display panel of the embodiment of the present application reduces the impedance of the first level line by adding auxiliary wiring; therefore, after the selection module is turned off, the signal connected to the first level line is pulled high as the data signal jumps high. Since the impedance of the first level line is reduced, the time for the signal of the first level line to return to normal can be accelerated, thereby reducing the risk of dark lines caused by overcharging of the third node.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] In an organic light-emitting display panel, the organic light-emitting display panel includes a pixel circuit. After the data writing stage, the data signal jumps high to couple the high-level power line (VGH), so that the signal of the high-level power line jumps high. Since the high-level power line generates coupling capacitance with the A node and the B node of the pixel circuit, the A node and the B node are pulled high, and then the Q node is overcharged. The potential of the Q node is higher than the value in the normal area, resulting in dark lines. Among them, the A node is the connection node of the input electrode of the driving thin film transistor, the B node is the connection node of the output electrode of the driving thin film transistor, and the Q node is the connection node of the gate of the driving thin film transistor and the storage capacitor (Cst). Summary of the invention

[0003] The embodiment of the present application provides a display panel that can improve dark lines.

[0004] An embodiment of the present application provides a display panel, comprising:

[0005] A first driving circuit includes a first level line and a first thin film transistor, wherein an input electrode of the first thin film transistor is connected to the first level line;

[0006] A pixel circuit, comprising a gating module, a driving thin film transistor, a threshold compensation module and a storage capacitor, wherein a control end of the gating module is connected to an output electrode of the first thin film transistor, an input end of the gating module is connected to a data line, an output end of the gating module and an input electrode of the driving thin film transistor are connected to a first node, an input end of the threshold compensation module and an output electrode of the driving thin film transistor are connected to a second node, and an output end of the threshold compensation module, a gate electrode of the driving thin film transistor and the storage capacitor are connected to a third node;

[0007] The first level line includes a signal line and an auxiliary line, the signal line is connected to the input electrode of the first thin film transistor, and the auxiliary line is connected to the signal line.

[0008] Optionally, in some embodiments of the present application, the display panel further includes a second driving circuit, a third driving circuit, a fourth driving circuit and a fifth driving circuit, and the pixel circuit includes a first control module, a second control module, a first initialization module, a second initialization module and a third initialization module;

[0009] The control end of the threshold compensation module is connected to the output end of the second driving circuit, the control end of the first initialization module is connected to the output end of the third driving circuit, the input end of the first initialization module is connected to the first voltage end, and the output end of the first initialization module is connected to the third node; the control end of the first control module is connected to the output end of the fourth driving circuit, the input end of the first control module is connected to the first potential end, and the output end of the first control module is connected to the first node; the control end of the second control module is connected to the output end of the fourth driving circuit, the input end of the second control module is connected to the second node, and the output end of the second control module is connected to the fourth node; the control end of the second initialization module is connected to the output end of the fifth driving circuit, the input end of the second initialization module is connected to the second voltage end, and the output end of the second initialization module is connected to the fourth node; the control end of the third initialization module is connected to the output end of the fifth driving circuit, the input end of the third initialization module is connected to the third voltage end, and the output end of the third initialization module is connected to the first node; the first plate of the storage capacitor is connected to the third node, and the second plate of the storage capacitor is connected to the first potential end; the anode of the display element is connected to the fourth node, and the cathode of the display element is connected to the second potential end;

[0010] In the thickness direction of the display panel, the signal routing and the auxiliary routing are arranged in different layers, and the auxiliary routing is located on a side of the signal routing away from the substrate; the auxiliary routing at least covers at least one of the first driving circuit, the second driving circuit, the third driving circuit, the fourth driving circuit and the fifth driving circuit.

[0011] Optionally, in some embodiments of the present application, the display panel further includes a clock signal line, and in a plan view of the display panel, the auxiliary wiring is located outside the clock signal line.

[0012] Optionally, in some embodiments of the present application, the first driving circuit further includes a second thin film transistor, the clock signal line includes a first clock signal line, an input electrode of the second thin film transistor is connected to the first clock signal line, and an output electrode of the second thin film transistor is connected to the control end of the gating module;

[0013] The auxiliary wiring includes a first auxiliary portion, and in a plan view of the display panel, the first auxiliary portion covers the first thin film transistor and the second thin film transistor.

[0014] Optionally, in some embodiments of the present application, the first auxiliary portion includes a first sub-line, a second sub-line and a third sub-line, the first sub-line is connected to the signal line through a via, and the second sub-line is connected to the first sub-line and the third sub-line;

[0015] In a plan view of the display panel, the clock signal line, the signal routing line, the first sub-line and the third sub-line are extended along a second direction, the second sub-line is extended along a first direction intersecting the second direction, a plurality of the first driving circuits are arranged along the second direction, the first thin film transistor and the second thin film transistor are arranged along the second direction, and the second sub-line and the third sub-line are located on a side of the first sub-line away from the clock signal line;

[0016] The first sub-line overlaps with the signal wiring, the second sub-line is located between two adjacent first driving circuits, and the third sub-line covers the first thin film transistor and the second thin film transistor.

[0017] Optionally, in some embodiments of the present application, in the plan view of the display panel, in the first direction, the distance from the first sub-line to the clock signal line closest to it is a first distance, and the distance from the first sub-line to the third sub-line closest to it is a second distance, and the second distance is greater than the first distance.

[0018] Optionally, in some embodiments of the present application, in a plan view of the display panel, a total area of ​​the third sub-lines is greater than a total area of ​​the first sub-lines.

[0019] Optionally, in some embodiments of the present application, the first driving circuit further includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a first capacitor and a second capacitor, and the clock signal line includes a second clock signal line;

[0020] Optionally, in some embodiments of the present application, in a plan view of the display panel, in the first direction, the first clock signal line is located on a side of the second clock signal line away from the first sub-line, and the third sub-line and the first sub-line are interposed between the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, the eighth thin film transistor and the second capacitor.

[0021] Optionally, in some embodiments of the present application, the fourth driving circuit further includes a ninth thin film transistor and a tenth thin film transistor, the input electrode of the ninth thin film transistor is connected to the third level line, the input electrode of the tenth thin film transistor is connected to the fourth level line, and the output electrode of the ninth thin film transistor and the output electrode of the tenth thin film transistor are connected to form an output end of the fourth driving circuit;

[0022] The auxiliary wiring includes a second auxiliary portion, and in a plan view of the display panel, the second auxiliary portion covers the ninth thin film transistor and the tenth thin film transistor.

[0023] Optionally, in some embodiments of the present application, in a plan view of the display panel, the third level line, the fourth level line and the second auxiliary portion extend along the second direction, the ninth thin film transistor and the tenth thin film transistor are arranged along the second direction, and the third level line and the second auxiliary portion are configured to be connected to the same voltage;

[0024] In a first direction intersecting with the second direction, the ninth thin film transistor, the tenth thin film transistor and the second auxiliary part are located between the third level line and the fourth level line, and a distance from the third level line to the second auxiliary part is smaller than a distance from the second auxiliary part to the fourth level line.

[0025] Optionally, in some embodiments of the present application, the fourth driving circuit further includes an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, a twentieth thin film transistor, a twenty-first thin film transistor, a third capacitor, a fourth capacitor and a fifth capacitor, and the clock signal line includes a third clock signal line and a fourth clock signal line;

[0026] In the plan view of the display panel, in the first direction, the third clock signal line and the fourth clock signal line are arranged adjacent to each other, and the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor, the sixteenth thin film transistor, the seventeenth thin film transistor, the eighteenth thin film transistor, the nineteenth thin film transistor, the twentieth thin film transistor, the twenty-first thin film transistor, the third capacitor, the fourth capacitor and the fifth capacitor are interposed between the third clock signal line and the second auxiliary portion.

[0027] Optionally, in some embodiments of the present application, the fifth driving circuit further includes a twenty-second thin film transistor and a twenty-third thin film transistor, the input electrode of the twenty-second thin film transistor is connected to the fifth level line, the input electrode of the twenty-third thin film transistor is connected to the sixth level line, and the output electrode of the twenty-second thin film transistor and the output electrode of the twenty-third thin film transistor are connected to form an output end of the fifth driving circuit;

[0028] The auxiliary wiring includes a third auxiliary portion, and in a plan view of the display panel, the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor.

[0029] Optionally, in some embodiments of the present application, in a plan view of the display panel, the fifth level line, the sixth level line and the third auxiliary portion extend along the second direction, the twenty-second thin film transistor and the twenty-third thin film transistor are arranged along the second direction, and the fifth level line and the third auxiliary portion are configured to be connected to the same voltage;

[0030] In a first direction intersecting with the second direction, the twenty-second thin film transistor, the twenty-third thin film transistor and the third auxiliary part are located between the fifth level line and the sixth level line, and the distance from the fifth level line to the third auxiliary part is smaller than the distance from the third auxiliary part to the sixth level line.

[0031] Optionally, in some embodiments of the present application, the fifth driving circuit further includes a twenty-fourth thin film transistor, a twenty-fifth thin film transistor, a twenty-sixth thin film transistor, a twenty-seventh thin film transistor, a twenty-eighth thin film transistor, a twenty-ninth thin film transistor, a thirtieth thin film transistor, a thirty-first thin film transistor, a thirty-second thin film transistor, a thirty-third thin film transistor, a thirty-fourth thin film transistor, a sixth capacitor, a seventh capacitor and an eighth capacitor, and the clock signal line includes a fifth clock signal line and a sixth clock signal line;

[0032] In the plan view of the display panel, in the first direction, the fifth clock signal line and the sixth clock signal line are arranged adjacent to each other, and the fifth clock signal line and the third auxiliary portion are interposed with the twenty-fourth thin film transistor, the twenty-fifth thin film transistor, the twenty-sixth thin film transistor, the twenty-seventh thin film transistor, the twenty-eighth thin film transistor, the twenty-ninth thin film transistor, the thirtieth thin film transistor, the thirty-first thin film transistor, the thirty-second thin film transistor, the thirty-third thin film transistor, the thirty-fourth thin film transistor, the sixth capacitor, the seventh capacitor and the eighth capacitor.

[0033] Optionally, in some embodiments of the present application, the auxiliary routing also includes a first connecting portion and a second connecting portion, the auxiliary routing also includes a second auxiliary portion and a third auxiliary portion, in a plan view of the display panel, the second auxiliary portion covers the ninth thin film transistor and the tenth thin film transistor in the fourth driving circuit, the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor in the fifth driving circuit, the first connecting portion connects the second auxiliary portion and the third auxiliary portion, and the second connecting portion connects the third auxiliary portion and the first auxiliary portion.

[0034] Optionally, in some embodiments of the present application, the first level line is configured to access a high level signal, the first thin film transistor is a P-type thin film transistor, and the gating module is configured to access the high level signal and turn on.

[0035] The display panel of the embodiment of the present application reduces the impedance of the first level line by adding auxiliary wiring; therefore, after the selection module is turned off, the signal based on the first level line is pulled high as the data signal jumps high. Since the impedance of the first level line is reduced, the time for the signal of the first level line to return to normal can be accelerated, thereby reducing the risk of dark lines caused by overcharging of the third node. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a plan view of a display panel provided in an embodiment of the present application;

[0037] Figure 2 is an equivalent circuit diagram of a first driving circuit of a display panel provided in an embodiment of the present application;

[0038] Figure 3 is an equivalent circuit diagram of a pixel circuit of a display panel provided in an embodiment of the present application;

[0039] Figure 4 is a timing diagram of a pixel circuit of a display panel provided in an embodiment of the present application;

[0040] Figure 5 is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present application;

[0041] Figure 6 is a plan view schematic diagram of a first driving circuit of a display panel provided in an embodiment of the present application;

[0042] Figure 7 yes Figure 6 A magnified schematic diagram of part A;

[0043] Figure 8 is an equivalent circuit diagram of a fourth driving circuit of a display panel provided in an embodiment of the present application;

[0044] Fig. 9 is a schematic plan view of a fourth driving circuit of a display panel provided in an embodiment of the present application;

[0045] Fig.10 yes Fig. 9 A magnified schematic diagram of part B;

[0046] Fig.11 is an equivalent circuit diagram of a fifth driving circuit of a display panel provided in an embodiment of the present application;

[0047] Fig.12 is a plan view of a fifth driving circuit of a display panel provided in an embodiment of the present application;

[0048] Fig.13 yes Fig.12 Enlarged schematic diagram of part C. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0050] The present application provides a display panel, which is described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0051] Figure 11 is a schematic view of a display panel 100 of an exemplary embodiment of the present application. The display panel 100 of the exemplary embodiment of the present application may be an electroluminescent display panel such as an organic light-emitting display panel, a micro-light-emitting diode display panel, a sub-millimeter-level light-emitting diode display panel, or a quantum dot light-emitting diode display panel. The display panel of the embodiment of the present application may be assembled and implemented as an electronic device such as a smart phone, a mobile phone, a navigation device, a game console, a television (TV), a vehicle host, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), a personal digital assistant (PDA), etc. In addition, the electronic device may be a flexible device.

[0052] like Figure 1 As shown, the first direction F1 may be a direction parallel to one side of the display panel 100 in a plan view, and may be, for example, a transverse direction of the display panel 100. The second direction F2 may be a direction parallel to the other side of the display panel 100 in a plan view, and may be a longitudinal direction of the display panel 100.

[0053] The display panel 100 of the exemplary embodiment of the present application has a display area AA and a non-display area NA. The non-display area NA may surround the display area AA. In an embodiment, the display area AA includes pixels for displaying an image, and the non-display area NA does not include pixels.

[0054] A plurality of display elements may be arranged in the display area AA. For example, the display element may be an organic light emitting diode, and may emit red light, green light, blue light, or white light. Figure 1 The (sub) pixels in the display area AA of the display panel 100 include such an organic light emitting diode, and also include a pixel circuit 10 configured to control the degree of light emission of the organic light emitting diode. The pixel circuit 10 is arranged in the display area AA. The driving circuit is configured to control the pixel circuit 10, and the driving circuit may be arranged in the non-display area NA.

[0055] The driving circuit includes a first driving circuit 20 a , a second driving circuit 20 b , a third driving circuit 20 c , a fourth driving circuit 20 d and a fifth driving circuit 20 e , and the first driving circuit 20 a to the fifth driving circuit 20 e are all connected to the pixel circuit 10 .

[0056] Optionally, in the first direction F1, the fourth driving circuit 20d, the fifth driving circuit 20e, the third driving circuit 20c, the second driving circuit 20b and the first driving circuit 20a are sequentially arranged in the non-display area NA.

[0057] The plurality of first driving circuits 20a are arranged along the second direction F2, the plurality of fourth driving circuits 20d are arranged along the second direction F2, and the plurality of fifth driving circuits 20e are arranged along the second direction F2.

[0058] It should be noted that both the pixel circuit 10 and the driving circuit include a plurality of thin film transistors, wherein the thin film transistors can be replaced according to their types (p-type or n-type) and / or operating conditions. For example, if the thin film transistor is p-type, it is cut off when connected to a high level and is turned on when connected to a low level, its source is the output electrode and its drain is the input electrode; if the thin film transistor is n-type, it is cut off when connected to a low level and is turned on when connected to a high level, its source is the input electrode and its drain is the output electrode.

[0059] Please refer to Figure 2 , Figure 2 FIG. 2 is an equivalent circuit of a first driving circuit 20 a of a display panel 100 according to an exemplary embodiment of the present application. The first driving circuit 20 a includes a plurality of thin film transistors and a capacitor. The first driving circuit 20 a is configured to control the on and off of a gating module 10 a of a pixel circuit 10 .

[0060] In an exemplary embodiment, Figure 2 As shown, the thin film transistors include first to eighth thin film transistors M1 to M8, and the capacitors include a first capacitor C1 and a second capacitor C2.

[0061] It should be noted that the first driving circuit 20a of the display panel 100 of the exemplary embodiment of the present application will be referred to as Figure 2 To illustrate, but not limited to.

[0062] The clock signal lines CK include a first clock signal line CK1 and a second clock signal line CK2.

[0063] The gate electrode of the first thin film transistor M1 and the first end of the second capacitor C2 are connected to the fifth node P5, the input electrode of the first thin film transistor M1 and the second end of the second capacitor C2 are connected to the first level line VGH, and the output electrode of the first thin film transistor M1 is connected to the control end of the gating module 10a of the pixel circuit 10. The input electrode of the second thin film transistor M2 is connected to the first clock signal line CK1, the output electrode of the second thin film transistor M2 is connected to the control end of the gating module 10a, the gate electrode of the second thin film transistor M2 and the first end of the first capacitor C1 are connected to the sixth node P6, and the second end of the first capacitor C1 is connected to the output electrode of the second thin film transistor M2.

[0064] The gate of the third thin film transistor M3 is connected to the output electrode of the seventh thin film transistor M7, the input electrode of the third thin film transistor M3 is connected to the second clock signal line CK2, and the output electrode of the third thin film transistor M3 is connected to the fifth node P5. The gate of the fourth thin film transistor M4 is connected to the first clock signal line CK1, the input electrode of the fourth thin film transistor M4 is connected to the output electrode of the fifth thin film transistor M5, and the output electrode of the fourth thin film transistor M4 is connected to the output electrode of the seventh thin film transistor M7.

[0065] The gate of the fifth thin film transistor M5 is connected to the fifth node P5, and the input electrode of the fifth thin film transistor M5 is connected to the first level line VGH. The gate of the sixth thin film transistor M6 is connected to the second clock signal line CK2, the input electrode of the sixth thin film transistor M6 is connected to the second level line VGL, and the output electrode of the sixth thin film transistor M6 is connected to the fifth node P5.

[0066] A gate of the seventh thin film transistor M7 is connected to the second clock signal line CK2 , and an input electrode of the seventh thin film transistor M7 serves as an input terminal of the first driving circuit 20 a .

[0067] A gate electrode of the eighth thin film transistor M8 is connected to the second level line VGL, an input electrode of the eighth thin film transistor M8 is connected to the output electrode of the seventh thin film transistor M7, and an output electrode of the eighth thin film transistor M8 is connected to the sixth node P6.

[0068] It should be noted that the first driving circuit 20a controls the on and off of the first thin film transistor M1 and the second thin film transistor M2 to control the on and off of the gating module 10a of the pixel circuit 10. That is, the output electrodes of the first thin film transistor M1 and the second thin film transistor M2 are connected and serve as the output terminal Pscan of the first driving circuit 20a.

[0069] exist Figure 2 In the embodiment, the first thin film transistor M1 to the eighth thin film transistor M8 are all p-type transistors, and accordingly, the first level line VGH is configured to access a high level signal, and the gating module 10a is set to access the high level signal for conduction. The second level line VGL is configured to access a low level signal. However, this is only exemplary, and at least one of the first thin film transistor M1 to the eighth thin film transistor M8 may also be an n-type transistor. And when the transistor is replaced with an n-type, the corresponding control signal also changes accordingly. For example, if the first thin film transistor M1 is an n-type transistor, the first level line VGH is configured to access a low level signal.

[0070] Please refer to Figure 3 , Figure 3 1 is a pixel equivalent circuit of a display panel 100 of an exemplary embodiment of the present application. The pixel circuit 10 includes a plurality of thin film transistors and a storage capacitor. The thin film transistor may include a first transistor T1 to an eighth transistor T8. The first transistor T1 is a driving thin film transistor.

[0071] It should be noted that the pixel circuit 10 of the display panel 100 of the exemplary embodiment of the present application will be referred to as Figure 3 To illustrate, but not limited to.

[0072] The pixel circuit 10 includes a gate module 10a, a driving thin film transistor T1, a threshold compensation module 10b and a storage capacitor Cst, a first control module 10c, a second control module 10d, a first initialization module 10e, a second initialization module 10f and a third initialization module 10g.

[0073] The gating module 10a is configured to control the data signal to be written into the third node Q and charge the third node Q. The control end of the gating module 10a is connected to the output end Pscan of the first driving circuit 20a, the input end of the gating module 10a is connected to the data line data, and the output end of the gating module 10a and the input electrode of the driving thin film transistor T1 are connected to the first node A.

[0074] The threshold compensation module 10b is configured to control the voltage input to the third node Q. The input terminal of the threshold compensation module 10b and the output electrode of the driving thin film transistor T1 are connected to the second node B, and the output terminal of the threshold compensation module 10b, the gate of the driving thin film transistor T1 and the storage capacitor Cst are connected to the third node Q. The control terminal of the threshold compensation module 10b is connected to the output terminal Nscan1 of the second driving circuit 20b.

[0075] The first control module 10c and the second control module 10d are configured to control the display element EL to light up. The control end of the first control module 10c is connected to the output end EM of the fourth drive circuit 20d, the input end of the first control module 10c is connected to the first potential end VDD, and the output end of the first control module 10c is connected to the first node A. The control end of the second control module 10d is connected to the output end EM of the fourth drive circuit 20d, the input end of the second control module 10d is connected to the second node B, and the output end of the second control module 10d is connected to the fourth node C. The anode of the display element EL is connected to the fourth node C, and the cathode of the display element EL is connected to the second potential end VSS.

[0076] The first initialization module 10e is configured to initialize the third node Q. The control end of the first initialization module 10e is connected to the output end of the third driving circuit 20c Nscan2, the input end of the first initialization module 10e is connected to the first voltage end Vi1, and the output end of the first initialization module 10e is connected to the third node Q. The second initialization module 10f is configured to initialize the fourth node C. The control end of the second initialization module 10f is connected to the output end Pscan2 of the fifth driving circuit 20e, the input end of the second initialization module 10f is connected to the second voltage end Vi2, and the output end of the second initialization module 10f is connected to the fourth node C. The third initialization module 10g is configured to initialize the first node A. The control end of the third initialization module 10g is connected to the output end Pscan2 of the fifth driving circuit 20e, the input end of the third initialization module 10g is connected to the third voltage end Vi3, and the output end of the third initialization module 10g is connected to the first node A. The first plate of the storage capacitor Cst is connected to the third node Q, and the second plate of the storage capacitor Cst is connected to the first potential end VDD.

[0077] It should be noted that the voltage level connected to the first potential terminal VDD may be higher than the voltage level of the second potential terminal VSS. The first voltage terminal Vi1 may be configured to connect to the first initialization voltage, the second voltage terminal Vi2 may be configured to connect to the second initialization voltage, and the third voltage terminal Vi3 may be configured to connect to the third initialization voltage.

[0078] exist Figure 3 In the embodiment, the gating module 10a includes a second transistor T2. The threshold compensation module 10b includes a third transistor T3. The first control module 10c includes a fifth transistor T5. The second control module 10d includes a sixth transistor T6. The first initialization module 10e includes a fourth transistor T4. The second initialization module 10f includes a seventh transistor T7. The third initialization module 10g includes an eighth transistor T8.

[0079] The gate of the second transistor T2 is connected to the output terminal Pscan of the first driving circuit 20a, the input of the second transistor T2 is connected to the data line data, and the output of the second transistor T2 and the input of the driving thin film transistor T1 are connected to the first node A. The input of the third transistor T3 and the output of the driving thin film transistor T1 are connected to the second node B, and the output of the third transistor T3, the gate of the driving thin film transistor T1 and the storage capacitor Cst are connected to the third node Q. The gate of the third transistor T3 is connected to the output terminal Nscan1 of the second driving circuit 20b.

[0080] The gate of the fifth transistor T5 is connected to the output terminal EM of the fourth driving circuit 20d, the input electrode of the fifth transistor T5 is connected to the first potential terminal VDD, and the output electrode of the fifth transistor T5 is connected to the first node A. The gate of the sixth transistor T6 is connected to the output terminal EM of the fourth driving circuit 20d, the input electrode of the sixth transistor T6 is connected to the second node B, and the output electrode of the sixth transistor T6 is connected to the fourth node C.

[0081] The gate of the fourth transistor T4 is connected to the output terminal Nscan2 of the third driving circuit 20c, the input electrode of the fourth transistor T4 is connected to the first voltage terminal Vi1, and the output electrode of the fourth transistor T4 is connected to the third node Q. The gate of the seventh transistor T7 is connected to the output terminal Pscan2 of the fifth driving circuit 20e, the input electrode of the seventh transistor T7 is connected to the second voltage terminal Vi2, and the output electrode of the seventh transistor T7 is connected to the fourth node C. The gate of the eighth transistor T8 is connected to the output terminal Pscan2 of the fifth driving circuit 20e, the input electrode of the eighth transistor T8 is connected to the third voltage terminal Vi3, and the output electrode of the eighth transistor T8 is connected to the first node A.

[0082] In addition, according to an embodiment, the pixel circuit 10 may further include a boost capacitor Cboost including a first terminal connected to the third node Q and a second terminal connected to the gate of the second transistor T2. The boost capacitor Cboost may increase the voltage of the third node Q.

[0083] like Figure 3 As shown, the third transistor T3 and the fourth transistor T4 may be n-type transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be p-type transistors. However, this is only exemplary, and at least one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may also be an n-type transistor.

[0084] Please refer to Figure 4The timing of the pixel circuit 10 includes a data writing phase R1. In the data writing phase R1, the first transistor T1 is configured to be turned on under the control of the voltage of the third node Q, the second transistor T2 is configured to be turned on under the control of the low level signal output by the output terminal Pscan of the first driving circuit 20a, and the third transistor T3 is configured to be turned on under the control of the high potential signal output by the output terminal Nscan1 of the second driving circuit 20b. The fourth transistor T4 is configured to be turned off under the control of the low potential signal output by the output terminal Nscan2 of the third driving circuit 20c, the fifth transistor T5 and the sixth transistor T6 are configured to be turned off under the control of the high potential signal output by the output terminal EM of the fourth driving circuit 20d, and the seventh transistor T7 and the eighth transistor T8 are configured to be turned off under the control of the high potential signal output by the output terminal Pscan2 of the fifth driving circuit 20e.

[0085] In the data writing phase R1, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the other transistors are turned off. The voltage of the data line data is written to the third node Q through the first node A and the second node B, and the third transistor T3 performs threshold capture on the first transistor T1.

[0086] The time when the data signal connected to the data line data jumps occurs after the data writing stage R1, and the third transistor T3 is still in the on state after the data signal jumps high. In other words, the data signal jumps high and couples, so that the signal (Pscan) of the first level line VGH jumps high at the moment R2, and because the first level line VGH and the first node A and the second node B of the pixel circuit 10 generate coupling capacitance, the first node A and the second node B are pulled high, and then the third node Q is charged with more charge.

[0087] It can be understood that the conduction time of the third transistor T3 includes a continuous first time, a second time and a third time, the first time is before the data writing stage R1, the second time is in the data writing stage R1, and the third time is after the data writing stage. The signal of the first level line VGH is coupled and pulled high in the stage corresponding to the third time.

[0088] It should be noted that Figure 4 The recovery time after Pscan is pulled high is only an example. The recovery time of the first level line VGH can be determined according to the area of ​​the auxiliary wiring vg2. The larger the area of ​​the auxiliary wiring vg2, the shorter the signal recovery time of the first level line VGH, and the shorter the time when the first node A and the second node B are pulled high. That is, the faster the signal of the first level line VGH that is pulled high drops, the faster the voltage of the first node A and the second node B that are pulled high drops, thereby reducing the overcharge charge.

[0089] Optionally, in some embodiments, the moment when the signal of the first level line VGH is pulled up by the data signal high jump coupling to be fully restored is the restoration moment, and the restoration moment is before the turning-off moment of the third transistor T3.

[0090] Please combine Figures 1 to 4 , a display panel 100 provided in an embodiment of the present application includes a first driving circuit 20 a, a first level line VGH and a pixel circuit 10 .

[0091] The first level line VGH includes a signal wiring vg1 and an auxiliary wiring vg2 . The signal wiring vg1 is connected to the input electrode of the first thin film transistor M1 , and the auxiliary wiring vg2 is connected to the signal wiring vg1 .

[0092] The display panel 100 of the embodiment of the present application reduces the impedance of the first level line VGH by adding an auxiliary wiring vg2; therefore, after the data writing stage, the signal connected to the first level line VGH is pulled high as the data signal jumps high. Since the impedance of the first level line VGH is reduced, the time for the signal of the first level line VGH to return to normal can be accelerated, thereby reducing the risk of dark lines caused by overcharging of the third node Q.

[0093] Please refer to Figure 5 The display panel 100 includes a substrate 11, a circuit structure layer 12 and a display element EL. The circuit structure layer 12 is disposed on the substrate 11, and the display element EL is disposed on a side of the circuit structure layer 12 away from the substrate 11.

[0094] The circuit structure layer 12 includes a pixel circuit 10 and a first driving circuit 20 a to a fifth driving circuit 20 e. The display element EL is connected to the pixel circuit 10.

[0095] The circuit structure layer 12 includes a light shielding layer Ls, a buffer layer buf, a first active layer py1, a first insulating layer jy1, a first metal layer js1, a second insulating layer jy2, a second metal layer js2, a third insulating layer jy3, a second active layer py2, a fourth insulating layer jy4, a third metal layer js3, a fifth insulating layer jy5, a fourth metal layer js4, a sixth insulating layer jy6, a fifth metal layer js5, a seventh insulating layer jy7, a sixth metal layer js6 and an eighth insulating layer jy8, which are arranged in sequence. The display element EL includes an anode y1, a light emitting layer y2 and a cathode y3.

[0096] Optionally, in some embodiments of the present application, the signal trace vg1 is formed in the fifth metal layer js5, and the auxiliary trace vg2 is formed in the sixth metal layer js6. The pixel circuit 10 and the first to fifth driving circuits 20a to 20e are formed between the first active layer py1 and the sixth insulating layer jy6.

[0097] It should be noted that the auxiliary routing vg2 is arranged above the first driving circuit 20a to the fifth driving circuit 20e to avoid the auxiliary routing vg2 being connected thereto and to allow the auxiliary routing vg2 to have more layout space; in addition, the auxiliary routing vg2 is arranged on the sixth metal layer js6 which is farthest from the substrate 11, which can increase the distance between the auxiliary routing vg2 and other signal lines in the thickness direction, thereby reducing the risk of interfering with other signal lines.

[0098] Optionally, the first metal layer js1 to the sixth metal layer js6 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements. In addition, the first metal layer js1 to the sixth metal layer js6 can have a single-layer structure or a stacked structure of two or more layers.

[0099] The materials of the first active layer py1 and the second active layer py2 may include single crystal silicon, polycrystalline silicon or oxide semiconductor. The materials of the first active layer py1 and the second active layer py2 are different, but not limited thereto, for example, the materials of the two may be the same.

[0100] Optionally, in some embodiments of the present application, the signal wiring vg1 and the auxiliary wiring vg2 are arranged in different layers in the thickness direction of the display panel 100. The auxiliary wiring vg2 is located on the side of the signal wiring vg1 away from the substrate; the auxiliary wiring vg2 at least covers at least one of the first driving circuit 20a, the second driving circuit 20b, the third driving circuit 20c, the fourth driving circuit 20d and the fifth driving circuit 20e.

[0101] It should be noted that as long as the first to fifth driving circuits 20a to 20e are not short-circuited with the auxiliary wiring vg2, in some embodiments, the thin film transistors of the first to fifth driving circuits 20a to 20e are arranged in different layers from the auxiliary wiring vg2, for example, the auxiliary wiring vg2 is arranged above the film layer where all the thin film transistors are located.

[0102] Secondly, it can be understood that the larger the coverage of the auxiliary wiring vg2, the lower the impedance of the first level line VGH, and the better the effect of improving the dark pattern. Therefore, the coverage of the auxiliary wiring vg2 can be adjusted according to actual needs. For example, the auxiliary wiring vg2 can be set in the area of ​​any one of the first drive circuit 20a to the fifth drive circuit 20e; it can also be set in the area of ​​any two of the first drive circuit 20a to the fifth drive circuit 20e; it can also be set in the area of ​​any three or four of the first drive circuit 20a to the fifth drive circuit 20e; or the auxiliary wiring vg2 can be set in the area of ​​the first drive circuit 20a to the fifth drive circuit 20e.

[0103] Optionally, in some embodiments of the present application, the display panel 100 further includes a clock signal line CK, and in a plan view of the display panel 100 , the auxiliary wiring vg2 is located outside the clock signal line CK.

[0104] It is understandable that the clock signal line CK is arranged in the circuit structure layer 12. The auxiliary line vg2 is arranged outside the clock signal line CK to avoid the auxiliary line vg2 and the clock signal line CK overlapping to generate parasitic capacitance, which will increase power consumption. Therefore, in some embodiments of the present application, the auxiliary line vg2 is arranged outside the clock signal line CK, which reduces the risk of generating parasitic capacitance, thereby reducing the risk of increased power consumption.

[0105] Please refer to Figure 6 and Figure 7 In some embodiments of the present application, the auxiliary trace vg2 includes a first auxiliary portion f1 , and in a plan view of the display panel 100 , the first auxiliary portion f1 covers the first thin film transistor M1 and the second thin film transistor M2 .

[0106] It can be understood that the first thin film transistor M1 and the second thin film transistor M2 are arranged adjacent to each other, and the layout area of ​​any one of them in the plan view is much larger than the area of ​​the third thin film transistor M3 to the eighth thin film transistor M8. Therefore, a first auxiliary part f1 with a larger area can be arranged in the area where the first thin film transistor M1 and the second thin film transistor M2 are located, and the first auxiliary part f1 is arranged directly above the first thin film transistor M1 and the second thin film transistor M2, which can reduce the risk of the first auxiliary part f1 coupling with other signal lines.

[0107] Secondly, when the first thin film transistor M1 is turned on, the high level signal of the first level line VGH is connected. At this time, the first auxiliary part f1 is also connected to the same high level signal, and the second thin film transistor M2 is turned off. Therefore, the first auxiliary part f1 has almost no interference with the first thin film transistor M1 and the second thin film transistor M2; therefore, the first auxiliary part f1 at least covers the first thin film transistor M1 and the second thin film transistor M2 to reduce the interference with the first driving circuit 20a.

[0108] Optionally, the first auxiliary portion f1 extends along the second direction F2 and covers a plurality of first thin film transistors M1 and second thin film transistors M2 of the first driving circuit 20a to increase the area of ​​the auxiliary wiring vg2 and further reduce the impedance of the first level line VGH.

[0109] Optionally, in some embodiments, the input electrode of the second thin film transistor M2 includes a first input bus s1 and a plurality of first input branch lines s2, the first input bus s1 extends along the second direction F2, the first input branch lines s2 extend along the first direction F1, and the plurality of first input branch lines s2 are arranged at intervals along the second direction F2 and connected to the first input bus s1. The output electrode of the second thin film transistor M2 includes a first output bus h1 and a plurality of first output branch lines h2, the first output bus h1 extends along the second direction F2, the first output branch lines h2 extend along the first direction F1, and the plurality of first output branch lines h2 are arranged at intervals along the second direction F2. The first direction F1 and the second direction F2 intersect.

[0110] The first input branch lines s2 and the first output branch lines h2 are alternately arranged along the second direction F2, and the first input bus s1 and the first output bus are separated by the first input branch lines s2 and the first output branch lines h2.

[0111] The input electrode sr2 of the first thin film transistor M1 is extended along the first direction F1 , and the first output branch line h2 of the second thin film transistor M2 is multiplexed as the output electrode of the first thin film transistor M1 .

[0112] Optionally, in some embodiments of the present application, the first auxiliary part f1 includes a first sub-line f11, a second sub-line f12 and a third sub-line f13, the first sub-line f11 is connected to the signal trace vg1 through a via k1, and the second sub-line f12 is connected to the first sub-line f11 and the third sub-line f13.

[0113] In a plan view of the display panel 100, the clock signal line CK, the signal routing line vg1, the first sub-line f11 and the third sub-line f13 are extended along the second direction F2, and the second sub-line f12 is extended along the first direction F1 intersecting the second direction F2. A plurality of first driving circuits 20a are arranged along the second direction F2. The first thin film transistors M1 and the second thin film transistors M2 are arranged along the second direction F2, and the second sub-line f12 and the third sub-line f13 are located on a side of the first sub-line f11 away from the clock signal line CK.

[0114] The first sub-line f11 overlaps with the signal wiring vg1 , the second sub-line f12 is located between two adjacent first driving circuits 20 a , and the third sub-line f13 covers the first thin film transistor M1 and the second thin film transistor M2 .

[0115] It can be understood that the first sub-line f11 is connected to the signal line vg1 through multiple vias k1, further reducing the impedance of the first level line VGH. Secondly, the second sub-line f12 and the third sub-line f13 are kept away from the clock signal line CK, which not only avoids the vertical parasitic capacitance with the clock signal line CK, but also reduces the risk of lateral parasitic capacitance with the clock signal line CK, further reducing power consumption.

[0116] Optionally, the third sub-line f13 extends along the second direction F2 and covers a plurality of first thin film transistors M1 and second thin film transistors M2 of the first driving circuit 20a, so as to increase the area of ​​the auxiliary wiring vg2 and further reduce the impedance of the first level line VGH.

[0117] Optionally, in some embodiments, a third sub-line f13 can be used to cover the entire area of ​​the first thin film transistor M1 and the second thin film transistor M2, which can increase the area of ​​the auxiliary wiring vg2 and thereby reduce the impedance of the first level line VGH; or a plurality of third sub-lines f13 can be arranged at intervals and cover the areas of the first thin film transistor M1 and the second thin film transistor M2, which can reduce interference with the first thin film transistor M1 and the second thin film transistor M2.

[0118] Optionally, in some embodiments, all the third sub-lines f13 are arranged between the first input bus s1 and the first output bus h1 to further reduce interference to other signal lines.

[0119] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, in a first direction F1, a distance from the first sub-line f11 to the nearest clock signal line CK is a first distance L1, and a distance from the first sub-line f11 to the nearest third sub-line f13 is a second distance L2, and the second distance L2 is greater than the first distance L1.

[0120] It can be understood that in the area of ​​the first driving circuit 20a, the second distance L2 is greater than the first distance L1, so that the third sub-line f13 is far away from the clock signal line CK, thereby reducing the interference of the third sub-line f13 on the clock signal line CK, that is, reducing the risk of forming parasitic capacitance.

[0121] Optionally, in some embodiments of the present application, in a plan view of the display panel 100 , a total area of ​​the third sub-lines f13 is greater than a total area of ​​the first sub-lines f11 .

[0122] It can be understood that since the third sub-line f13 is far away from the clock signal line CK, the total area of ​​the third sub-line f13 is set to be larger, which can not only reduce the risk of forming parasitic capacitance with the clock signal line CK, but also increase the area of ​​the auxiliary routing vg2, and further reduce the impedance of the first level line VGH.

[0123] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, in the first direction F1, the first clock signal line CK1 is located on a side of the second clock signal line CK2 away from the first sub-line f11, and the third sub-line f13 and the first sub-line f11 are interposed with the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, the sixth thin film transistor M6, the seventh thin film transistor M7, the eighth thin film transistor and the second capacitor C2.

[0124] It can be understood that by arranging the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, the sixth thin film transistor M6, the seventh thin film transistor M7, the eighth thin film transistor and the second capacitor C2 between the second clock signal line CK2 and the first thin film transistor M1, the distance between the first thin film transistor M1 and the second thin film transistor M2 and the second clock signal line CK2 can be increased respectively. Based on the fact that the third sub-line f13 is arranged above the area of ​​the first thin film transistor M1 and the second thin film transistor M2, the risk of parasitic capacitance generated by the third sub-line f13 and the second clock signal line CK2 can be reduced.

[0125] Please refer to Figures 8 to 10 , Figure 8 FIG. 2 shows an equivalent circuit diagram of an exemplary fourth driving circuit 20 d of the present application. Fig. 9 FIG. 2 is a schematic plan view of an exemplary fourth driving circuit 20 d of the present application. Fig.10 It shows Fig. 9 FIG. 2 is a plan view of a single fourth driving circuit 20 d.

[0126] In an exemplary embodiment, if Figure 8 As shown, the thin film transistors of the fourth driving circuit 20d include ninth to twenty-first thin film transistors M9 to M21, the capacitors include third capacitor C3, fourth capacitor C4 and fifth capacitor C5, and the clock signal line CK includes a third clock signal line CK3 and a fourth clock signal line CK4.

[0127] It should be noted that the fourth driving circuit 20d of the display panel 100 of the exemplary embodiment of the present application will be referred to as Figure 8 To illustrate, but not limited to.

[0128] The input electrode of the ninth thin film transistor M9 is connected to the third level line VGH1, the input electrode of the tenth thin film transistor M10 is connected to the fourth level line VGL1, and the output electrode of the ninth thin film transistor M9 and the output electrode of the tenth thin film transistor M10 are connected to form the output terminal EM of the fourth driving circuit 20d. The gate of the ninth thin film transistor M9 is connected to the seventh node P7, and the gate of the tenth thin film transistor M10 is connected to the eighth node P8. The first end of the fifth capacitor C5 is connected to the seventh node P7, and the second end of the fifth capacitor C5 is connected to the third level line VGH1.

[0129] The gate of the eleventh thin film transistor M11 is connected to the ninth node P9, the input of the eleventh thin film transistor M11 is connected to the third level line VGH1, and the output of the eleventh thin film transistor M11 is connected to the tenth node P10. The gate of the twelfth thin film transistor M12 is connected to the eighth node P8, the input of the twelfth thin film transistor M12 is connected to the third clock signal line CK3, and the output of the twelfth thin film transistor M12 is connected to the tenth node P10; the first end of the third capacitor C3 is connected to the tenth node P10, and the second end of the third capacitor C3 is connected to the eighth node P8.

[0130] The gate of the thirteenth thin film transistor M13 is connected to the fourth clock signal line CK4, the input electrode of the thirteenth thin film transistor M13 serves as the input terminal of the fourth driving circuit 20d, and the output electrode of the thirteenth thin film transistor M13 is connected to the eleventh node P11. The gate of the fourteenth thin film transistor M14 is connected to the fourth clock signal line CK4, the input electrode of the fourteenth thin film transistor M14 is connected to the fourth level line VGL1, and the output electrode of the fourteenth thin film transistor M14 is connected to the ninth node P9.

[0131] A gate electrode of the fifteenth thin film transistor M15 is connected to the eleventh node P11 , an input electrode of the fifteenth thin film transistor M15 is connected to the fourth clock signal line CK4 , and an output electrode of the fifteenth thin film transistor M15 is connected to the ninth node P9 .

[0132] The gate of the sixteenth thin film transistor M16 is connected to the twelfth node P12, the input electrode of the sixteenth thin film transistor M16 is connected to the third clock signal line CK3, and the output electrode of the sixteenth thin film transistor M16 is connected to the thirteenth node P13. The first end of the fourth capacitor C4 is connected to the twelfth node P12, and the second end of the fourth capacitor C4 is connected to the thirteenth node P13.

[0133] A gate electrode of the seventeenth thin film transistor M17 is connected to the third clock signal line CK3 , an input electrode of the seventeenth thin film transistor M17 is connected to the thirteenth node P13 , and an output electrode of the seventeenth thin film transistor M17 is connected to the seventh node P7 .

[0134] The gate of the eighteenth thin film transistor M18 is connected to the eleventh node P11, the input electrode of the eighteenth thin film transistor M18 is connected to the third level line VGH1, and the output electrode of the eighteenth thin film transistor M18 is connected to the seventh node P7. The gate of the nineteenth thin film transistor M19 is connected to the fourth level line VGL1, the input electrode of the nineteenth thin film transistor M19 is connected to the ninth node P9, and the output electrode of the nineteenth thin film transistor M19 is connected to the twelfth node P12.

[0135] The gate of the twentieth thin film transistor M20 is connected to the fourth level line VGL1, the input electrode of the twentieth thin film transistor M20 is connected to the eleventh node P11, and the output electrode of the twentieth thin film transistor M20 is connected to the eighth node P8. The gate of the twenty-first thin film transistor M21 is connected to the first control signal line Control1, the input electrode of the twenty-first thin film transistor M21 is connected to the third level line VGH1, and the output electrode of the twenty-first thin film transistor M21 is connected to the eleventh node P11.

[0136] It should be noted that the fourth driving circuit 20d controls the on and off of the first control module 10c and the second control module 10d of the pixel circuit 10 by controlling the on and off of the ninth thin film transistor M9 and the tenth thin film transistor M10. That is, the output electrodes of the ninth thin film transistor M9 and the tenth thin film transistor M10 are connected and serve as the output terminal EM of the fourth driving circuit 20d.

[0137] exist Figure 8 In the embodiment, the ninth thin film transistor M9 to the twenty-first thin film transistor M21 are all p-type transistors, and in response, the third level line VGH1 is configured to access a high level signal, and the first control module 10c and the second control module 10d are set to access the high level signal to be turned off. The fourth level line VGL1 is configured to access a low level signal. However, this is only exemplary, and at least one of the ninth thin film transistor M9 to the twenty-first thin film transistor M21 can also be an n-type transistor. And when the transistor is replaced with an n-type, the corresponding control signal also changes accordingly.

[0138] Optionally, in some embodiments of the present application, the auxiliary wiring vg2 includes a second auxiliary portion f2. In a plan view of the display panel 100, the second auxiliary portion f2 covers the ninth thin film transistor M9 and the tenth thin film transistor M10.

[0139] It can be understood that the ninth thin film transistor M9 and the tenth thin film transistor M10 are arranged adjacent to each other, and the layout area of ​​either of them in the plan view is much larger than the area of ​​the eleventh to twenty-first thin film transistors M11 to M21. Therefore, a second auxiliary part f2 with a larger area can be set in the area where the ninth thin film transistor M9 and the tenth thin film transistor M10 are located, and the second auxiliary part f2 is set directly above the ninth thin film transistor M9 and the tenth thin film transistor M10, which can reduce the risk of the second auxiliary part f2 coupling other signal lines.

[0140] Optionally, the second auxiliary portion f2 extends along the second direction F2 and covers the ninth thin film transistor M9 and the tenth thin film transistor M10 of the fourth driving circuit 20d to increase the area of ​​the second auxiliary portion f2 and further reduce the impedance of the first level line VGH.

[0141] Optionally, in some embodiments, the input electrode of the ninth thin film transistor M9 includes a plurality of third input branch lines s3, the third input branch lines s3 extend along the first direction F1, and the plurality of third input branch lines s3 are arranged at intervals along the second direction F2 and connected to the third level line VGH1. The output electrode of the ninth thin film transistor M9 includes a third output bus h3 and a plurality of third output branch lines h4, the third output bus h3 extends along the second direction F2, the third output branch lines h4 extend along the first direction F1, and the plurality of third output branch lines h4 are arranged at intervals along the second direction F2. The first direction F1 intersects with the second direction F2. Among them, the third input branch lines s3 and the third output branch lines h4 are alternately arranged along the second direction F2, and the third level line VGH1 and the third output bus h3 are spaced apart by the third input branch lines s3 and the third output branch lines h4.

[0142] The input electrode of the tenth thin film transistor M10 includes a plurality of fourth input branch lines s4 extending along the first direction F1 , and the plurality of fourth input branch lines s4 are arranged at intervals along the second direction F2 and connected to the fourth level line VGL1 .

[0143] The output electrode of the tenth thin film transistor M10 includes a fourth output bus h5 and a plurality of fourth output branch lines h6, the fourth output bus h5 extends along the second direction F2 and is connected to the third output bus h3. The fourth output branch line h6 extends along the first direction F1, and the plurality of fourth output branch lines h6 are arranged at intervals along the second direction F2. The first direction F1 intersects the second direction F2. Among them, the fourth input branch line s4 and the fourth output branch line h6 are alternately arranged along the second direction F2, and the ninth thin film transistor M9 and the tenth thin film transistor M10 are spaced between the third level line VGH1 and the fourth level line VGL1.

[0144] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, the third level line VGH1, the fourth level line VGL1 and the second auxiliary part f2 extend along the second direction F2, the ninth thin film transistor M9 and the tenth thin film transistor M10 are arranged along the second direction F2, and the third level line VGH1 and the second auxiliary part f2 are set to be connected to the same voltage.

[0145] In the first direction F1 intersecting with the second direction F2, the ninth thin film transistor M9, the tenth thin film transistor M10 and the second auxiliary part f2 are located between the third level line VGH1 and the fourth level line VGL1, and the distance L3 from the third level line VGH1 to the second auxiliary part f2 is smaller than the distance L4 from the second auxiliary part f2 to the fourth level line VGL1.

[0146] It is understandable that, since the third level line VGH1 and the second auxiliary part f2 are connected to the same voltage, the risk of the second auxiliary part f2 interfering with other signal lines can be reduced by placing the second auxiliary part f2 closer to the third level line VGH1 .

[0147] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, in the first direction, the third clock signal line CK3 and the fourth clock signal line CK4 are adjacent to each other, and the third clock signal line CK3 and the second auxiliary portion f2 are interposed with the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, the fifteenth thin film transistor M15, the sixteenth thin film transistor M16, the seventeenth thin film transistor M17, the eighteenth thin film transistor M18, the nineteenth thin film transistor M19, the twentieth thin film transistor M20, the twenty-first thin film transistor M21, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5.

[0148] It can be understood that by arranging the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, the fifteenth thin film transistor M15, the sixteenth thin film transistor M16, the seventeenth thin film transistor M17, the eighteenth thin film transistor M18, the nineteenth thin film transistor M19, the twentieth thin film transistor M20, the twenty-first thin film transistor M21, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 between the third clock signal line CK3 and the ninth thin film transistor M9, the distance between the ninth thin film transistor M9 and the tenth thin film transistor M10 and the third clock signal line CK can be increased respectively, and based on the second auxiliary part f2 being arranged above the area of ​​the ninth thin film transistor M9 and the tenth thin film transistor M10, the risk of parasitic capacitance generated by the second auxiliary part f2 and the third clock signal line CK3 can be reduced.

[0149] Please refer to Figures 11 to 13 , Fig.11 FIG. 2 shows an equivalent circuit diagram of an exemplary fifth driving circuit 20 e of the present application. Fig.12 FIG. 2 is a schematic plan view of an exemplary fifth driving circuit 20 e of the present application. Fig.13 It is shown that Fig.12 FIG. 2 is a plan view of a single fifth driving circuit 20 e.

[0150] In an exemplary embodiment, Fig.11 As shown, the thin film transistors of the fifth driving circuit 20e include the 22nd to 34th thin film transistors M22 to M34, the capacitors include the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8. The clock signal line CK includes the fifth clock signal line CK5 and the sixth clock signal line CK6.

[0151] It should be noted that the fifth driving circuit 20e of the display panel 100 of the exemplary embodiment of the present application will be referred to as Fig.11 To illustrate, but not limited to.

[0152] The input electrode of the twenty-second thin film transistor M22 is connected to the fifth level line VGH2, the input electrode of the twenty-third thin film transistor M23 is connected to the sixth level line VGL2, and the output electrode of the twenty-second thin film transistor M22 and the output electrode of the twenty-third thin film transistor M23 are connected to form the output terminal Pscan2 of the fifth driving circuit 20e. The gate of the twenty-second thin film transistor M22 is connected to the fourteenth node P14, and the gate of the twenty-third thin film transistor M23 is connected to the fifteenth node P15. The first end of the eighth capacitor C8 is connected to the fourteenth node P14, and the second end of the eighth capacitor C8 is connected to the fifth level line VGH2.

[0153] A gate electrode of the twenty-fourth thin film transistor M24 is connected to the sixteenth node P16 , an input electrode of the twenty-fourth thin film transistor M24 is connected to the fifth level line VGH2 , and an output electrode of the twenty-fourth thin film transistor M24 is connected to the seventeenth node P17 .

[0154] The gate of the twenty-fifth thin film transistor M25 is connected to the fifteenth node P15, the input electrode of the twenty-fifth thin film transistor M25 is connected to the fifth clock signal line CK5, and the output electrode of the twenty-fifth thin film transistor M25 is connected to the seventeenth node P17. The first end of the sixth capacitor C6 is connected to the seventeenth node P17, and the second end of the sixth capacitor C6 is connected to the fifteenth node P15.

[0155] The gate of the twenty-sixth thin film transistor M26 is connected to the sixth clock signal line CK6, the input electrode of the twenty-sixth thin film transistor M26 serves as the input terminal of the fifth driving circuit 20e, and the output electrode of the twenty-sixth thin film transistor M26 is connected to the eighteenth node P18. The gate of the twenty-seventh thin film transistor M27 is connected to the sixth clock signal line CK6, the input electrode of the twenty-seventh thin film transistor M27 is connected to the sixth level line VGL2, and the output electrode of the twenty-seventh thin film transistor M27 is connected to the sixteenth node P16.

[0156] A gate of the twenty-eighth thin film transistor M28 is connected to the eighteenth node P18 , an input electrode of the twenty-eighth thin film transistor M28 is connected to the sixth clock signal line CK6 , and an output electrode of the twenty-eighth thin film transistor M28 is connected to the sixteenth node P16 .

[0157] The gate of the twenty-ninth thin film transistor M29 is connected to the nineteenth node P19, the input electrode of the twenty-ninth thin film transistor M29 is connected to the fifth clock signal line CK5, and the output electrode of the twenty-ninth thin film transistor M29 is connected to the twentieth node P20; the first end of the seventh capacitor C7 is connected to the nineteenth node P19, and the second end of the seventh capacitor C7 is connected to the twentieth node P20.

[0158] The gate of the 30th thin film transistor M30 is connected to the fifth clock signal line CK5, the input electrode of the 30th thin film transistor M30 is connected to the 20th node P20, and the output electrode of the 30th thin film transistor M30 is connected to the 14th node P14. The gate of the 31st thin film transistor M31 is connected to the 18th node P18, the input electrode of the 31st thin film transistor M31 is connected to the fifth level line VGH2, and the output electrode of the 31st thin film transistor M31 is connected to the 14th node P14.

[0159] The gate of the thirty-second thin film transistor M32 is connected to the sixth level line VGL2, the input electrode of the thirty-second thin film transistor M32 is connected to the sixteenth node P16, and the output electrode of the thirty-second thin film transistor M32 is connected to the nineteenth node P19. The gate of the thirty-third thin film transistor M33 is connected to the sixth level line VGL2, the input electrode of the thirty-third thin film transistor M33 is connected to the eighteenth node P18, and the output electrode of the thirty-third thin film transistor M33 is connected to the fifteenth node P15.

[0160] A gate of the thirty-fourth thin film transistor M34 is connected to the second control signal line Control2 , an input electrode of the thirty-fourth thin film transistor M34 is connected to the fifth level line VGH2 , and an output electrode of the thirty-fourth thin film transistor M34 is connected to the eighteenth node P18 .

[0161] It should be noted that the fifth driving circuit 20e controls the on and off of the second initialization module 10f and the third initialization module 10g of the pixel circuit 10 by controlling the on and off of the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23. That is, the output electrodes of the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are connected and serve as the output terminal Pscan2 of the fifth driving circuit 20e.

[0162] exist Fig.11 In the embodiment, the 22nd thin film transistor M22 to the 34th thin film transistor M34 are all p-type transistors, and in response, the fifth level line VGH2 is configured to access a high level signal, and the second initialization module 10f and the third initialization module 10g are set to access the high level signal to be turned off. The sixth level line VGL2 is configured to access a low level signal. However, this is only exemplary, and at least one of the 22nd thin film transistor M22 to the 34th thin film transistor M34 may also be an n-type transistor. And when the transistor is replaced with an n-type, the corresponding control signal also changes accordingly.

[0163] Optionally, in some embodiments of the present application, the auxiliary wiring vg2 includes a third auxiliary portion f3. In a plan view of the display panel 100, the third auxiliary portion f3 covers the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23.

[0164] It can be understood that the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are arranged adjacent to each other, and the layout area of ​​either of them in the plan view is much larger than the area of ​​the twenty-fourth thin film transistor M24 to the thirty-fourth thin film transistor M34. Therefore, a third auxiliary part f3 with a larger area can be set in the area where the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are located, and the third auxiliary part f3 is set directly above the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23, which can reduce the risk of the third auxiliary part f3 coupling with other signal lines.

[0165] Optionally, the third auxiliary portion f3 extends along the second direction F2 and covers the twenty-second thin film transistors M22 and the twenty-third thin film transistors M23 of the fifth driving circuit 20e to increase the area of ​​the third auxiliary portion f3 and further reduce the impedance of the first level line VGH.

[0166] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, the fifth level line VGH2, the sixth level line VGL2 and the third auxiliary part f3 extend along the second direction F2, and the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are arranged along the second direction F2. The fifth level line VGH2 and the third auxiliary part f3 are set to be connected to the same voltage.

[0167] In the first direction F1 intersecting with the second direction F2, the twenty-second thin film transistor M22, the twenty-third thin film transistor M23 and the third auxiliary part f3 are located between the fifth level line VGH2 and the sixth level line VGL2, and the distance L5 from the fifth level line VGH2 to the third auxiliary part f3 is smaller than the distance L6 from the third auxiliary part f3 to the sixth level line VGL2.

[0168] It is understandable that, since the fifth level line VGH2 and the third auxiliary part f3 are connected to the same voltage, the third auxiliary part f3 is closer to the fifth level line VGH2, which can reduce the risk of the third auxiliary part f3 interfering with other signal lines.

[0169] Optionally, in some embodiments of the present application, in a plan view of the display panel 100, in the first direction F1, the fifth clock signal line CK5 and the sixth clock signal line CK6 are adjacent to each other, and the fifth clock signal line CK5 and the third auxiliary portion f3 are interposed with the twenty-fourth thin film transistor M24, the twenty-fifth thin film transistor M25, the twenty-sixth thin film transistor M26, the twenty-seventh thin film transistor M27, the twenty-eighth thin film transistor M28, the twenty-ninth thin film transistor M29, the thirtieth thin film transistor M30, the thirty-first thin film transistor M31, the thirty-second thin film transistor M32, the thirty-third thin film transistor M33, the thirty-fourth thin film transistor M34, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8.

[0170] It can be understood that by arranging the twenty-fourth thin film transistor M24, the twenty-fifth thin film transistor M25, the twenty-sixth thin film transistor M26, the twenty-seventh thin film transistor M27, the twenty-eighth thin film transistor M28, the twenty-ninth thin film transistor M29, the thirtieth thin film transistor M30, the thirty-first thin film transistor M31, the thirty-second thin film transistor M32, the thirty-third thin film transistor M33, the thirty-fourth thin film transistor M34, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 between the fifth clock signal line CK5 and the twenty-second thin film transistor M22, the distance between the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 and the fifth clock signal line CK5 can be increased respectively, and based on the third auxiliary part f3 being arranged above the area of ​​the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23, the risk of parasitic capacitance generated by the third auxiliary part f3 and the fifth clock signal line CK5 can be reduced.

[0171] Optionally, in some embodiments of the present application, the circuit structure of the fifth driving circuit 20e may be the same as the circuit structure of the fourth driving circuit 20d, for example Fig.13 and Fig.10 Same, but not limited to this.

[0172] Optionally, in some embodiments of the present application, the auxiliary wiring vg2 further includes a first connection portion f4 and a second connection portion f5, and the auxiliary wiring vg2 further includes a second auxiliary portion f2 and a third auxiliary portion f3. In a plan view of the display panel 100, the second auxiliary portion f2 covers the ninth thin film transistor M9 and the tenth thin film transistor M10 in the fourth drive circuit 20d, and the third auxiliary portion f3 covers the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 in the fifth drive circuit 20e. The first connection portion f4 connects the second auxiliary portion f2 and the third auxiliary portion f3, and the second connection portion f5 connects the third auxiliary portion f3 and the first auxiliary portion f1.

[0173] That is, the auxiliary wiring vg2 is arranged in the area of ​​the first driving circuit 20a, the fourth driving circuit 20d and the fifth driving circuit 20e, and is connected into one through the first connecting portion f4 and the second connecting portion f5 to increase the area of ​​the auxiliary wiring vg2, thereby greatly reducing the impedance of the first level line VGH.

[0174] Optionally, in some embodiments, the first level line VGH, the third level line VGH1 and the fifth level line VGH2 can be connected and connected to the same signal, but not limited to this, for example, the three can also be connected to the level signal independently. The second level line VGL, the fourth level line VGL1 and the sixth level line VGL2 can be connected and connected to the same signal, but not limited to this, for example, the three can also be connected to the level signal independently.

[0175] The display panel of the embodiment of the present application reduces the impedance of the first level line by adding auxiliary wiring; therefore, after the first thin film transistor is turned off, the signal connected to the first level line is pulled high as the data signal jumps high. Since the impedance of the first level line is reduced, the time for the signal of the first level line to return to normal can be accelerated, thereby reducing the risk of dark lines caused by overcharging of the Q node.

[0176] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: A first driving circuit comprises a first thin film transistor, wherein an input electrode of the first thin film transistor is connected to a first level line; A pixel circuit, comprising a gating module, a driving thin film transistor, a threshold compensation module and a storage capacitor, wherein a control end of the gating module is connected to an output electrode of the first thin film transistor, an input end of the gating module is connected to a data line, an output end of the gating module and an input electrode of the driving thin film transistor are connected to a first node, an input end of the threshold compensation module and an output electrode of the driving thin film transistor are connected to a second node, and an output end of the threshold compensation module, a gate electrode of the driving thin film transistor and the storage capacitor are connected to a third node; The first level line includes a signal line and an auxiliary line, the signal line is connected to the input electrode of the first thin film transistor, the auxiliary line is connected to the signal line, and the auxiliary line is configured to reduce the impedance of the first level line.

2. The display panel according to claim 1, characterized in that: The display panel further includes a second driving circuit, a third driving circuit, a fourth driving circuit and a fifth driving circuit, and the pixel circuit includes a first control module, a second control module, a first initialization module, a second initialization module and a third initialization module; The control end of the threshold compensation module is connected to the output end of the second driving circuit, the control end of the first initialization module is connected to the output end of the third driving circuit, the input end of the first initialization module is connected to the first voltage end, and the output end of the first initialization module is connected to the third node; the control end of the first control module is connected to the output end of the fourth driving circuit, the input end of the first control module is connected to the first potential end, and the output end of the first control module is connected to the first node; the control end of the second control module is connected to the output end of the fourth driving circuit, the input end of the second control module is connected to the second node, and the output end of the second control module is connected to the fourth node; the control end of the second initialization module is connected to the output end of the fifth driving circuit, the input end of the second initialization module is connected to the second voltage end, and the output end of the second initialization module is connected to the fourth node; the control end of the third initialization module is connected to the output end of the fifth driving circuit, the input end of the third initialization module is connected to the third voltage end, and the output end of the third initialization module is connected to the first node; the first plate of the storage capacitor is connected to the third node, and the second plate of the storage capacitor is connected to the first potential end; The anode of the display element is connected to the fourth node, and the cathode of the display element is connected to the second potential terminal; In the thickness direction of the display panel, the signal routing and the auxiliary routing are arranged in different layers, and the auxiliary routing is located on the side of the signal routing away from the substrate; the auxiliary routing at least covers at least one of the first driving circuit, the second driving circuit, the third driving circuit, the fourth driving circuit and the fifth driving circuit.

3. The display panel according to claim 2, characterized in that: The display panel further includes a clock signal line, and in a plan view of the display panel, the auxiliary wiring is located outside the clock signal line.

4. The display panel according to claim 3, characterized in that: The first driving circuit further includes a second thin film transistor, the clock signal line includes a first clock signal line, an input electrode of the second thin film transistor is connected to the first clock signal line, and an output electrode of the second thin film transistor is connected to the control end of the gating module; The auxiliary wiring includes a first auxiliary portion, and in a plan view of the display panel, the first auxiliary portion covers the first thin film transistor and the second thin film transistor.

5. The display panel according to claim 4, characterized in that: The first auxiliary part includes a first sub-line, a second sub-line and a third sub-line, the first sub-line is connected to the signal line through a via, and the second sub-line is connected to the first sub-line and the third sub-line; In a plan view of the display panel, the clock signal line, the signal routing line, the first sub-line and the third sub-line are extended along a second direction, the second sub-line is extended along a first direction intersecting the second direction, a plurality of the first driving circuits are arranged along the second direction, the first thin film transistor and the second thin film transistor are arranged along the second direction, and the second sub-line and the third sub-line are located on a side of the first sub-line away from the clock signal line; The first sub-line overlaps with the signal wiring, the second sub-line is located between two adjacent first driving circuits, and the third sub-line covers the first thin film transistor and the second thin film transistor.

6. The display panel according to claim 5, characterized in that: In the plan view of the display panel, in the first direction, the distance from the first sub-line to the nearest clock signal line is a first distance, the distance from the first sub-line to the nearest third sub-line is a second distance, and the second distance is greater than the first distance.

7. The display panel according to claim 6, characterized in that: In a plan view of the display panel, a total area of ​​the third sub-lines is greater than a total area of ​​the first sub-lines.

8. The display panel according to claim 5, characterized in that: The first driving circuit further includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a first capacitor and a second capacitor, and the clock signal line includes a second clock signal line; In the plan view of the display panel, in the first direction, the first clock signal line is located on the side of the second clock signal line away from the first sub-line, and the third sub-line and the first sub-line are separated by the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, the eighth thin film transistor and the second capacitor.

9. The display panel according to claim 3, characterized in that: The fourth driving circuit further includes a ninth thin film transistor and a tenth thin film transistor, the input electrode of the ninth thin film transistor is connected to the third level line, the input electrode of the tenth thin film transistor is connected to the fourth level line, and the output electrode of the ninth thin film transistor and the output electrode of the tenth thin film transistor are connected to form an output end of the fourth driving circuit; The auxiliary wiring includes a second auxiliary portion, and in a plan view of the display panel, the second auxiliary portion covers the ninth thin film transistor and the tenth thin film transistor.

10. The display panel according to claim 9, characterized in that: In a plan view of the display panel, the third level line, the fourth level line and the second auxiliary portion extend along a second direction, the ninth thin film transistor and the tenth thin film transistor are arranged along the second direction, and the third level line and the second auxiliary portion are configured to be connected to the same voltage; In a first direction intersecting with the second direction, the ninth thin film transistor, the tenth thin film transistor and the second auxiliary part are located between the third level line and the fourth level line, and a distance from the third level line to the second auxiliary part is smaller than a distance from the second auxiliary part to the fourth level line.

11. The display panel according to claim 10, characterized in that: The fourth driving circuit further includes an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, a twentieth thin film transistor, a twenty-first thin film transistor, a third capacitor, a fourth capacitor and a fifth capacitor, and the clock signal line includes a third clock signal line and a fourth clock signal line; In the plan view of the display panel, in the first direction, the third clock signal line and the fourth clock signal line are arranged adjacent to each other, and the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor, the sixteenth thin film transistor, the seventeenth thin film transistor, the eighteenth thin film transistor, the nineteenth thin film transistor, the twentieth thin film transistor, the twenty-first thin film transistor, the third capacitor, the fourth capacitor and the fifth capacitor are interposed between the third clock signal line and the second auxiliary portion.

12. The display panel according to claim 3, characterized in that: The fifth driving circuit further includes a twenty-second thin film transistor and a twenty-third thin film transistor, the input electrode of the twenty-second thin film transistor is connected to the fifth level line, the input electrode of the twenty-third thin film transistor is connected to the sixth level line, and the output electrode of the twenty-second thin film transistor and the output electrode of the twenty-third thin film transistor are connected to form an output end of the fifth driving circuit; The auxiliary wiring includes a third auxiliary portion, and in a plan view of the display panel, the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor.

13. The display panel according to claim 12, characterized in that: In a plan view of the display panel, the fifth level line, the sixth level line and the third auxiliary portion extend along the second direction, the twenty-second thin film transistor and the twenty-third thin film transistor are arranged along the second direction, and the fifth level line and the third auxiliary portion are configured to be connected to the same voltage; In a first direction intersecting with the second direction, the twenty-second thin film transistor, the twenty-third thin film transistor and the third auxiliary part are located between the fifth level line and the sixth level line, and the distance from the fifth level line to the third auxiliary part is smaller than the distance from the third auxiliary part to the sixth level line.

14. The display panel according to claim 13, characterized in that: The fifth driving circuit further includes a twenty-fourth thin film transistor, a twenty-fifth thin film transistor, a twenty-sixth thin film transistor, a twenty-seventh thin film transistor, a twenty-eighth thin film transistor, a twenty-ninth thin film transistor, a thirtieth thin film transistor, a thirty-first thin film transistor, a thirty-second thin film transistor, a thirty-third thin film transistor, a thirty-fourth thin film transistor, a sixth capacitor, a seventh capacitor and an eighth capacitor, and the clock signal line includes a fifth clock signal line and a sixth clock signal line; In the plan view of the display panel, in the first direction, the fifth clock signal line and the sixth clock signal line are arranged adjacent to each other, and the fifth clock signal line and the third auxiliary portion are interposed with the twenty-fourth thin film transistor, the twenty-fifth thin film transistor, the twenty-sixth thin film transistor, the twenty-seventh thin film transistor, the twenty-eighth thin film transistor, the twenty-ninth thin film transistor, the thirtieth thin film transistor, the thirty-first thin film transistor, the thirty-second thin film transistor, the thirty-third thin film transistor, the thirty-fourth thin film transistor, the sixth capacitor, the seventh capacitor and the eighth capacitor.

15. The display panel according to claim 4, characterized in that: The auxiliary wiring also includes a first connecting portion and a second connecting portion, and the auxiliary wiring also includes a second auxiliary portion and a third auxiliary portion. In a plan view of the display panel, the second auxiliary portion covers the ninth thin film transistor and the tenth thin film transistor in the fourth driving circuit, and the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor in the fifth driving circuit. The first connecting portion connects the second auxiliary portion and the third auxiliary portion, and the second connecting portion connects the third auxiliary portion and the first auxiliary portion.

16. The display panel according to any one of claims 1 to 15, characterized in that: The first level line is configured to be connected to a high level signal, the first thin film transistor is a P-type thin film transistor, and the gating module is configured to be connected to the high level signal for conduction.

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