Pulse signal generating circuit, method, data reading circuit and device
By designing a pulse signal generation circuit including a delay circuit, an inverter, an AND gate operator and a D flip-flop, the problem of low clock signal operating frequency and eFuse data reading speed is solved, and an efficient data reading rate is achieved.
CN119010847BActive Publication Date: 2025-03-25RONGXIN SEMICON (HUAIAN) CO LTD
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Patent Information
- Application Number
- CN202411180151.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2044-08-26
AI Technical Summary
Technical Problem
In the prior art, the operating frequency of the clock signal and the readout speed of the eFuse data are relatively low, making it difficult to meet the requirements of dynamic real-time reprogramming.
Method used
A pulse signal generation circuit is designed, including a delay circuit, an inverter, an AND gate operator and a D flip-flop. By adjusting the delay time of the delay circuit and the inverter, the target frequency of the clock signal is determined, thereby generating a pulse signal of the target width.
Benefits of technology
It effectively increases the operating frequency of the clock signal, thereby significantly improving the read speed of eFuse data, and achieving a data reading rate of almost twice the speed.
✦ Generated by Eureka AI based on patent content.
Abstract
The present application provides a pulse signal generating circuit, method, data reading circuit and device. The pulse signal generating circuit includes a delay circuit, an inverter, a NAND gate operator and a D flip-flop; the input end of the delay circuit is connected to the clock signal end of the D flip-flop, and the clock signal end and the input end of the delay circuit are used to input the clock signal; the output end of the delay circuit is respectively connected to the input end of the inverter and the first input end of the NAND gate operator, the output end of the inverter is connected to the second input end of the NAND gate operator, and the output end of the NAND gate operator is connected to the reset end of the D flip-flop. Through this circuit, when the pulse width is constant, the operating frequency of the clock signal can be effectively increased, thereby increasing the readout speed of the eFuse data.
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