Descriptor chain management method, flash memory controller, electronic device, and storage medium

Abstract

The present application discloses a descriptor chain management method and a flash memory controller, an electronic device, and a storage medium, and relates to the field of flash memory technology. The method includes: receiving N flash memory atomic operations, obtaining N first free descriptor chains; N is a positive integer greater than three; configuring based on each flash memory atomic operation and the first free descriptor chain, obtaining the target descriptor node of each flash memory atomic operation and N target descriptor chains to be executed; scheduling the target descriptor chain to execute each target descriptor node in the target descriptor chain in turn; when a target descriptor chain is executed, generating node status information and descriptor chain status information; traversing the node status information of each target descriptor node of the executed target descriptor chain, and performing release processing to obtain the second free descriptor chain. The present application scheme can manage multiple descriptor chains at the same time, and effectively utilize the hardware performance of the flash memory controller.

Description

Technical Field

[0001] The present application relates to the field of flash memory technology, and in particular to a descriptor chain management method, a flash memory controller, an electronic device, and a storage medium. Background Art

[0002] The flash memory controller consists of two parts: the front end and the back end. The front end is responsible for managing the command queue to be sent, and the back end is responsible for data interaction with the flash memory device. Currently, the flash memory controllers on the market generally use the descriptor linked list method to manage the command queue to be sent. The traditional descriptor node and descriptor chain resource management scheme only allows three descriptor chains to exist at the same time. These three descriptor chains are: an executing descriptor chain x, a configuring descriptor chain y, and a waiting to be released descriptor chain z. When the executing descriptor chain x and the waiting to be released descriptor chain z are not executed, the configured descriptor chain y needs to wait for the descriptor chain x and descriptor chain z to be executed before it can enter the core processing module of the flash memory controller and wait to be executed. Under this management method, the management amount of the descriptor chain of the flash memory controller is small, resulting in a waste of the performance of the flash memory controller. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a descriptor chain management method and a flash memory controller, an electronic device, and a storage medium, which can manage multiple descriptor chains at the same time, effectively utilize the hardware performance of the flash memory controller, and improve the performance utilization of the flash memory controller.

[0004] In a first aspect, an embodiment of the present application provides a descriptor chain management method, which is applied to a flash memory controller, wherein the flash memory controller includes an address cache unit; the method includes:

[0005] Receiving N flash atomic operations, obtaining N first free descriptor chains from preconfigured descriptor chain resources; wherein N is a positive integer greater than three;

[0006] Perform descriptor node configuration processing according to each of the flash atomic operations to obtain a target descriptor node for each of the flash atomic operations;

[0007] According to the target descriptor node corresponding to each of the flash memory atomic operations, each of the first idle descriptor chains is configured accordingly to obtain N target descriptor chains to be executed;

[0008] Cache the first addresses of the N target descriptor chains, schedule the target descriptor chains in sequence according to the first addresses, and execute each of the target descriptor nodes in the target descriptor chains; after executing one target descriptor chain, generate node status information of each target descriptor node and descriptor chain status information;

[0009] The target descriptor chain that has been executed is determined according to the descriptor chain status information, the node status information of each target descriptor node of the target descriptor chain that has been executed is traversed, and node release processing and descriptor chain release processing are performed to obtain a second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain.

[0010] According to some embodiments of the present application, each of the flash atomic operations includes at least one sub-operation; performing descriptor node configuration processing according to each of the flash atomic operations to obtain a target descriptor node for each of the flash atomic operations includes:

[0011] Determining a first number of said sub-operations in each said flash atomic operation;

[0012] Take out a first number of first free descriptor nodes from the top of the free descriptor stack;

[0013] Configure a corresponding first idle descriptor node according to the type of the sub-operation to obtain a configured target descriptor node;

[0014] The first idle descriptor nodes are configured one by one to obtain the target descriptor node of each flash memory atomic operation.

[0015] According to some embodiments of the present application, the target descriptor node corresponding to each of the flash atomic operations is configured accordingly for each of the first idle descriptor chains to obtain N target descriptor chains to be executed, including:

[0016] Mounting all the target descriptor nodes corresponding to one of the flash memory atomic operations to the end of one of the first free descriptor chains to obtain one of the target descriptor chains;

[0017] The N first idle descriptor chains are configured one by one to obtain N target descriptor chains.

[0018] According to some embodiments of the present application, the flash memory controller includes a register unit; when executing one of the target descriptor chains, generating node status information of each of the target descriptor nodes and descriptor chain status information includes:

[0019] After executing each target descriptor node, a corresponding node execution result is obtained;

[0020] Storing the corresponding node execution result in the node status information of each target descriptor node;

[0021] When all the target descriptor nodes are executed, the descriptor chain status information is generated; wherein the descriptor chain status information is used to indicate that the corresponding target descriptor chain has been executed and completed;

[0022] The descriptor chain status information and the node status information are cached in the register unit.

[0023] According to some embodiments of the present application, the traversal executes the node status information of each target descriptor node of the target descriptor chain, performs node release processing and descriptor chain release processing to obtain a second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain, including:

[0024] Traversing the node status information of each target descriptor node of the target descriptor chain that has completed execution, and obtaining the node execution result from the node status information;

[0025] When the node execution result is correct, the configuration of the target descriptor node is cleared to obtain a second idle descriptor node; the second idle descriptor node is used to be configured as a new target descriptor node;

[0026] After the traversal is completed, a descriptor chain release process is performed on the target descriptor chain that has been executed to obtain the second free descriptor chain.

[0027] According to some embodiments of the present application, performing a descriptor chain release process on the target descriptor chain that has been executed to obtain the second idle descriptor chain includes:

[0028] Marking the state of the target descriptor chain that has been executed as an idle state, to obtain the second idle descriptor chain;

[0029] The second idle descriptor chain is placed back into the descriptor chain resource to be re-called and configured as a new target descriptor chain.

[0030] According to some embodiments of the present application, after performing the node release process and the descriptor chain release process to obtain the second idle descriptor chain, the method further includes:

[0031] Determining the target descriptor chain to be executed;

[0032] The descriptor chain status information and the node status information corresponding to the target descriptor chain that has been executed in the register unit are deleted.

[0033] In a second aspect, an embodiment of the present application provides a flash memory controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the descriptor chain management method as described in any one of the embodiments of the first aspect.

[0034] In a third aspect, an embodiment of the present application provides an electronic device, comprising a flash memory controller as described in the embodiment of the second aspect.

[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the descriptor chain management method as described in any one of the embodiments of the first aspect.

[0036] The embodiment of the present application includes: when the flash memory controller is working and receives N flash memory atomic operations, N first idle descriptor chains are obtained from the preconfigured descriptor chain resources; wherein N is a positive integer greater than three; then, descriptor node configuration processing is performed according to each flash memory atomic operation to obtain a target descriptor node for each flash memory atomic operation; then, each first idle descriptor chain is configured accordingly according to the target descriptor node corresponding to each flash memory atomic operation to obtain N target descriptor chains to be executed; then, the first addresses of the N target descriptor chains are cached, and the target descriptor chains are scheduled in sequence according to the first addresses to execute. Each target descriptor node in the target descriptor chain is executed; when a target descriptor chain is executed, the node status information of each target descriptor node and the descriptor chain status information are generated; finally, the target descriptor chain that has been executed is determined according to the descriptor chain status information, the node status information of each target descriptor node of the target descriptor chain that has been executed is traversed, and the node release processing and the descriptor chain release processing are performed to obtain the second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain; in this way, the flash memory controller can manage multiple descriptor chains at the same time, thereby improving its own hardware performance utilization. That is to say, the solution provided by the embodiment of the present application can manage multiple descriptor chains at the same time, effectively utilize the hardware performance of the flash memory controller, and improve the performance utilization of the flash memory controller.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1is a schematic diagram of functional units of a flash memory controller provided by an embodiment of the present application;

[0039] Figure 2 It is a flowchart of a descriptor chain management method provided by an embodiment of the present application;

[0040] Figure 3 This is an embodiment of the present application. Figure 2 A flowchart of a specific method of step S140;

[0041] Figure 4 This is an embodiment of the present application. Figure 2 A flowchart of a specific method of step S150;

[0042] Figure 5 It is a hardware structure diagram of a flash memory controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0044] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0045] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0047] The present application provides a descriptor chain management method and a flash memory controller, an electronic device and a computer-readable storage medium, and relates to the field of flash memory technology. The method includes: receiving N flash memory atomic operations, obtaining N first free descriptor chains; N is a positive integer greater than three; configuring based on each flash memory atomic operation and the first free descriptor chain, obtaining the target descriptor node of each flash memory atomic operation and N target descriptor chains to be executed; scheduling the target descriptor chain to execute each target descriptor node in the target descriptor chain in turn; when a target descriptor chain is executed, generating node status information and descriptor chain status information; traversing the node status information of each target descriptor node of the executed target descriptor chain, and performing release processing to obtain the second free descriptor chain. The present application scheme can manage multiple descriptor chains at the same time, and effectively utilize the hardware performance of the flash memory controller.

[0048] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0049] like Figure 1 As shown, Figure 1 The flash memory controller includes a front end and a back end which are communicatively connected, wherein the front end includes a processing unit, an address cache unit and a register unit which are electrically connected to the processing unit.

[0050] It can be understood that the flash memory controller consists of two parts, the front end and the back end. The front end is responsible for managing the command queue to be sent, and the back end is responsible for data interaction with the flash memory device. Specifically, the front end will take the descriptors from the descriptor waiting queue in sequence for field parsing, and then perform specified atomic operations on the flash memory device through the back end. For example: erase operation command group (60H+ADDR+D0H), write operation command group (80H+ADDR+DATA+10H), a command group can be configured into a descriptor node. After the flash memory controller obtains the descriptor node and parses the descriptor node, it will send the specified command combination and address, and if necessary, data will be transferred.

[0051] Specifically, the address cache unit is used to cache the first addresses of N target descriptor chains to be executed.

[0052] Specifically, the register unit is used to cache the node status information of each target descriptor node and the descriptor chain status information generated during the execution of N target descriptor chains.

[0053] Specifically, the processing unit is used to: receive N flash atomic operations, obtain N first free descriptor chains from preconfigured descriptor chain resources; wherein N is a positive integer greater than three; perform descriptor node configuration processing according to each flash atomic operation to obtain a target descriptor node for each flash atomic operation; configure each first free descriptor chain accordingly according to the target descriptor node corresponding to each flash atomic operation to obtain N target descriptor chains to be executed; cache the first addresses of the N target descriptor chains, and schedule the target descriptor chains in sequence according to the first addresses, and execute each target descriptor node in the target descriptor chain; when a target descriptor chain is executed, generate node status information of each target descriptor node and descriptor chain status information; determine the target descriptor chain that has been executed according to the descriptor chain status information, traverse the node status information of each target descriptor node of the target descriptor chain that has been executed, perform node release processing and descriptor chain release processing to obtain a second free descriptor chain, and the second free descriptor chain is used to be called and configured as a new target descriptor chain; in this way, the flash controller can manage multiple descriptor chains at the same time, thereby improving its own hardware performance utilization.

[0054] It is understandable that the traditional descriptor node and descriptor chain resource management scheme only allows three descriptor chains to exist at the same time. These three descriptor chains are: an executing descriptor chain x, a configuring descriptor chain y, and a descriptor chain z waiting to be released. When the executing descriptor chain x and the descriptor chain z waiting to be released have not been executed, the configured descriptor chain y needs to wait for the descriptor chain x and the descriptor chain z to be executed before it can enter the core processing module of the flash memory controller and wait to be executed. The embodiment of the present application supports the management of up to N (N>3) descriptor chains at the same time, reaching the limit of hardware design, and reducing the probability of waiting for the previous descriptor chain to be completed before processing other descriptor chains.

[0055] The flash memory controller provided according to the embodiment of the present application can manage multiple descriptor chains at the same time, effectively utilize the hardware performance of the flash memory controller, and improve the performance utilization of the flash memory controller.

[0056] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0057] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0058] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0059] Based on the above system structure, various embodiments of the descriptor chain management method of the present application are proposed below.

[0060] First, as Figure 2 As shown, the descriptor chain management method can be applied to Figure 1 The processing unit in the flash memory controller shown, the flash memory controller also includes an address cache unit; the descriptor chain management method may include but is not limited to steps S110 to S150.

[0061] Step S110: Receive N flash atomic operations, and obtain N first free descriptor chains from preconfigured descriptor chain resources; wherein N is a positive integer greater than three.

[0062] Step S120: Perform descriptor node configuration processing according to each flash atomic operation to obtain a target descriptor node for each flash atomic operation.

[0063] Step S130: According to the target descriptor node corresponding to each flash memory atomic operation, each first idle descriptor chain is configured accordingly to obtain N target descriptor chains to be executed.

[0064] Step S140: Cache the first addresses of N target descriptor chains, schedule the target descriptor chains in sequence according to the first addresses, and execute each target descriptor node in the target descriptor chain; when a target descriptor chain is executed, generate node status information of each target descriptor node and descriptor chain status information.

[0065] Step S150: Determine the target descriptor chain that has been executed according to the descriptor chain status information, traverse the node status information of each target descriptor node of the target descriptor chain that has been executed, perform node release processing and descriptor chain release processing to obtain a second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain.

[0066] It is understandable that the management objects of the embodiments of the present application are descriptor nodes and descriptor chains. In some embodiments, before step S110, the descriptor chain management method further includes: performing resource allocation processing for initialization in the global variable space to obtain pre-configured descriptor chain resources. This specifies the location of all resource storage and the size of the occupied space, and determines the complete process of constructing, executing, and releasing each descriptor.

[0067] Specifically, the descriptor chain resources include but are not limited to: descriptor chain resources, descriptor resources, descriptor node resources, descriptor node status information resources, free descriptor stacks, and descriptor chain end node resources.

[0068] The descriptor chain resources are used to store and manage multiple descriptor chains (including free descriptor chains and target descriptor chains). The embodiment of the present application allows a maximum of N (N>3) descriptor chains to exist simultaneously, so the resources of each chain are managed by configuring the descriptor chain resources.

[0069] The descriptor resource is used to store the specific configuration information of each descriptor, where the specific configuration information includes but is not limited to: flash memory operation type, descriptor status information address, CE (Chip Enable) number, block number and page number, etc.

[0070] Descriptor node resources are used to manage descriptor nodes and node information. The entity mounted on the descriptor chain is the descriptor node. Each descriptor node records important node information. Descriptor node resources are configured to facilitate subsequent management of the descriptor chain.

[0071] The descriptor node status information resource is used to configure a descriptor node status information address for each descriptor node, which is used to receive the node execution result of the descriptor node returned by the flash memory controller.

[0072] The free descriptor stack is used to store all free descriptor nodes. When a new descriptor node needs to be configured, the free descriptor node is popped from the stack; when a descriptor node that has been used is released as a free descriptor node, the free descriptor node is pushed into the stack.

[0073] The descriptor chain end node resource is used to record the last descriptor node of each descriptor chain, from which information such as the length of the specified descriptor chain can be directly obtained.

[0074] Through step S110, the same number of first free descriptor chains are obtained from preconfigured descriptor chain resources according to the number of received flash memory atomic operations, laying a data foundation for subsequent construction of a target descriptor chain to be executed.

[0075] In some embodiments, each flash atomic operation includes at least one sub-operation. The operation types of the sub-operation include but are not limited to: read operation and write operation. This application does not make specific restrictions on the operation type of the sub-operation.

[0076] It should be noted that the flash memory controllers currently on the market generally use a descriptor linked list to manage the command queue to be sent, and most of them support no more than 3 descriptor linked lists. In order to support more flash memory chip selects and higher product performance, flash memory controllers that support more descriptor chains have appeared on the market, but the difficulty of software management has increased accordingly. Therefore, in the embodiment of the present application, through steps S110 to S150, when the flash memory controller is working and receives N flash memory atomic operations, it obtains N first free descriptor chains from the preconfigured descriptor chain resources; wherein N is a positive integer greater than three; then, according to each flash memory atomic operation, the descriptor node configuration processing is performed to obtain the target descriptor node of each flash memory atomic operation; then, according to the target descriptor node corresponding to each flash memory atomic operation, each first free descriptor chain is configured accordingly to obtain N target descriptor chains to be executed; then, the first addresses of the N target descriptor chains are cached, and scheduled in sequence according to the first addresses. Target descriptor chain, execute each target descriptor node in the target descriptor chain; when a target descriptor chain is executed, the node status information of each target descriptor node and the descriptor chain status information are generated; finally, the target descriptor chain that has been executed is determined according to the descriptor chain status information, the node status information of each target descriptor node of the target descriptor chain that has been executed is traversed, and the node release processing and the descriptor chain release processing are performed to obtain the second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain; in this way, the flash memory controller can manage multiple descriptor chains at the same time, thereby improving its own hardware performance utilization. Therefore, the embodiment of the present application can manage multiple descriptor chains at the same time, effectively utilize the hardware performance of the flash memory controller, and improve the performance utilization of the flash memory controller. The embodiment of the present application implements a resource management mechanism for descriptors and descriptor chains, thereby maximizing the performance of the flash memory controller.

[0077] According to some embodiments of the present application, each flash atomic operation includes at least one sub-operation; further describing step S120, step S120: performing descriptor node configuration processing according to each flash atomic operation to obtain a target descriptor node for each flash atomic operation, including but not limited to steps S121 to S124.

[0078] Step S121: Determine a first number of sub-operations in each flash atomic operation.

[0079] Step S122: taking out a first number of first free descriptor nodes from the top of the free descriptor stack.

[0080] Step S123: configuring a corresponding first idle descriptor node according to the type of a sub-operation to obtain a configured target descriptor node.

[0081] Step S124: configure the first idle descriptor nodes one by one to obtain the target descriptor node of each flash atomic operation.

[0082] It can be understood that the number of sub-operations of a single flash atomic operation reflects the operation complexity of the single flash atomic operation.

[0083] Through step S121 to step S122, a corresponding number of first idle descriptor nodes are adaptively acquired according to the operation complexity of the flash memory atomic operation, laying a foundation for constructing the target descriptor node.

[0084] Specifically, step S124 also includes: after each target descriptor node is configured, the configured target descriptor nodes are numbered in the order in which the configuration is completed, so as to facilitate subsequent traversal of the target descriptor nodes to determine whether the nodes are executed, thereby achieving effective management of the target descriptor nodes.

[0085] Through steps S121 to S124, a corresponding number of first idle descriptor nodes can be adaptively obtained according to the operational complexity of the flash memory atomic operation, and the first idle descriptor nodes can be configured to obtain configured target descriptor nodes to be executed, laying a data foundation for the subsequent construction of the target descriptor chain.

[0086] According to some embodiments of the present application, step S130 is further described. Step S130: according to the target descriptor node corresponding to each flash memory atomic operation, each first free descriptor chain is configured accordingly to obtain N target descriptor chains to be executed, including but not limited to steps S131 to S132.

[0087] Step S131: mount all target descriptor nodes corresponding to a flash memory atomic operation to the end of a first free descriptor chain to obtain a target descriptor chain.

[0088] Step S132: configure the N first idle descriptor chains one by one to obtain N target descriptor chains.

[0089] Specifically, step S132 also includes: after each target descriptor chain is configured, the configured target descriptor chains are numbered in the order in which the configuration is completed; this facilitates the subsequent scheduling of different target descriptor chains, as well as searching and recording the executed target descriptor chains, so as to achieve effective management of the target descriptor chains.

[0090] Through step S131 to step S132 , N target descriptor chains can be configured to facilitate execution and management by the flash memory controller.

[0091] According to some embodiments of the present application, the flash memory controller includes a register unit; Figure 3 As shown, step S140 is further described, wherein, when a target descriptor chain is executed, node status information of each target descriptor node and descriptor chain status information are generated, including but not limited to steps S141 to S144.

[0092] Step S141: After executing each target descriptor node, a corresponding node execution result is obtained.

[0093] Step S142: storing the corresponding node execution result into the node status information of each target descriptor node.

[0094] Step S143: after all target descriptor nodes are executed, descriptor chain status information is generated; wherein the descriptor chain status information is used to indicate that the corresponding target descriptor chain has been executed and completed.

[0095] Step S144: Cache the descriptor chain status information and the node status information into the register unit.

[0096] Specifically, in step S142, each time a node execution result is obtained, the node execution result is automatically transmitted to the configured corresponding descriptor status information address, so that the node execution result is stored in the node status information.

[0097] It can be understood that in step S141 to step S142, in the process of executing each target descriptor node of the target descriptor chain, each node execution result is stored in the node status information to facilitate checking the node execution status in subsequent traversals.

[0098] It should be noted that the node execution result of each descriptor node is stored in the node status information of the corresponding descriptor node. This operation is automatically returned by the flash memory controller, not by software operation. The software operation only needs to configure the cache address of the node status information to the corresponding field before executing the descriptor node. After the flash memory controller completes the execution of the descriptor node, it will automatically update the node execution result to the node status information.

[0099] Specifically, step S143 includes: when all target descriptor nodes in a target descriptor chain are executed, it is determined that the execution of the target descriptor chain is completed.

[0100] Through steps S141 to S144, each target descriptor node of the target descriptor chain is executed. After the execution is completed, the descriptor chain status information and node status information generated in the process are cached in the register unit for easy calling. The node execution status and the descriptor chain execution status are reflected in subsequent traversals, so as to better manage the target descriptor nodes and the target descriptor chain.

[0101] According to some embodiments of the present application, Figure 4 As shown, step S150 is further described, the node status information of each target descriptor node of the completed target descriptor chain is traversed, and node release processing and descriptor chain release processing are performed to obtain a second idle descriptor chain, and the second idle descriptor chain is used to be called and configured as a new target descriptor chain, including but not limited to steps S151 to S153.

[0102] Step S151: traverse the node status information of each target descriptor node of the target descriptor chain that has been executed, and obtain the node execution result from the node status information.

[0103] Step S152: when the node execution result is correct, the configuration of the target descriptor node is cleared to obtain a second idle descriptor node; the second idle descriptor node is used to be configured as a new target descriptor node.

[0104] Step S153: after the traversal is completed, a descriptor chain release process is performed on the target descriptor chain that has been executed to obtain a second free descriptor chain.

[0105] Specifically, the node execution results include: error and no error.

[0106] Specifically, step S150 further includes: when the node execution result is incorrect, creating an error handling task according to the operation type of the sub-operation corresponding to the target descriptor node. Specifically, when the node execution result is incorrect and the operation type of the sub-operation corresponding to the target descriptor node is a read operation, the created error handling task is a reread process.

[0107] Specifically, after each target descriptor node is traversed, it is determined whether it is the last target descriptor node in the target descriptor chain according to the number of the target descriptor node; if so, it is determined that the traversal of the target descriptor chain is completed, and the traversal of this target descriptor chain ends; if not, the node status information of the next target descriptor node is accessed in the order of the number until the traversal of this target descriptor chain is completed. Then the next target descriptor chain is scheduled according to the number.

[0108] According to some embodiments of the present application, step S153 is further described, wherein a descriptor chain release process is performed on the target descriptor chain that has been executed to obtain a second idle descriptor chain, including: marking the state of the target descriptor chain that has been executed as an idle state to obtain a second idle descriptor chain; and putting the second idle descriptor chain back into the descriptor chain resources to be re-called and configured as a new target descriptor chain.

[0109] Through step S151 to step S153, after checking the node execution result of each target descriptor node and the execution status of the target descriptor chain one by one, the target descriptor node is released as the second free descriptor node and the target descriptor chain is released as the second free descriptor chain in an orderly manner, so as to realize the recycling of descriptor nodes and descriptor chains and achieve effective management of descriptor nodes and descriptor chains.

[0110] According to some embodiments of the present application, after performing node release processing and descriptor chain release processing to obtain a second free descriptor chain, the method further includes steps S210 to S220.

[0111] Step S210: determining the target descriptor chain that has been executed;

[0112] Step S220: deleting the descriptor chain status information and the node status information corresponding to the executed target descriptor chain in the register unit.

[0113] Through steps S210 to S220, after releasing the executed target descriptor node and target descriptor chain, the related descriptor chain status information and node status information stored in the register unit are cleared, which is conducive to the subsequent reuse of the register unit space and reduces the risk of abnormal use of the register unit due to complex information.

[0114] like Figure 5 As shown, Figure 5 1 is a schematic diagram of the hardware structure of a flash memory controller provided by an embodiment of the present application. The present invention also provides a flash memory controller, including:

[0115] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0116] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the descriptor chain management method of the embodiment of this application;

[0117] Input / output interface 503, used to implement information input and output;

[0118] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0119] A bus 505 that transmits information between various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0120] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via the bus 505 .

[0121] An embodiment of the present application also provides an electronic device, comprising the flash memory controller as described above.

[0122] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned descriptor chain management method is implemented.

[0123] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0124] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0125] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A descriptor chain management method, characterized in that: Applied to a flash memory controller; the method comprises: Receiving N flash atomic operations, obtaining N first free descriptor chains from preconfigured descriptor chain resources; wherein N is a positive integer greater than three; Perform descriptor node configuration processing according to each of the flash atomic operations to obtain a target descriptor node for each of the flash atomic operations; According to the target descriptor node corresponding to each of the flash memory atomic operations, each of the first idle descriptor chains is configured accordingly to obtain N target descriptor chains to be executed; Cache the first addresses of the N target descriptor chains, schedule the target descriptor chains in sequence according to the first addresses, and execute each of the target descriptor nodes in the target descriptor chains; after executing one target descriptor chain, generate node status information of each target descriptor node and descriptor chain status information; Determine the target descriptor chain that has been executed according to the descriptor chain status information, traverse the node status information of each target descriptor node of the target descriptor chain that has been executed, perform node release processing and descriptor chain release processing to obtain a second idle descriptor chain, wherein the second idle descriptor chain is used to be called and configured as a new target descriptor chain; Each of the flash atomic operations includes at least one sub-operation; and performing descriptor node configuration processing according to each of the flash atomic operations to obtain a target descriptor node for each of the flash atomic operations includes: Determining a first number of said sub-operations in each said flash atomic operation; Take out a first number of first free descriptor nodes from the top of the free descriptor stack; Configure a corresponding first idle descriptor node according to the type of the sub-operation to obtain a configured target descriptor node; configuring the first idle descriptor nodes one by one to obtain the target descriptor node of each flash memory atomic operation; The flash memory controller includes a register unit; when executing one of the target descriptor chains, generating node status information of each of the target descriptor nodes and descriptor chain status information, including: After executing each target descriptor node, a corresponding node execution result is obtained; Storing the corresponding node execution result in the node status information of each target descriptor node; When all the target descriptor nodes are executed, the descriptor chain status information is generated; wherein the descriptor chain status information is used to indicate that the corresponding target descriptor chain has been executed and completed; The descriptor chain status information and the node status information are cached in the register unit.

2. The descriptor chain management method according to claim 1, characterized in that: The step of configuring each of the first idle descriptor chains according to the target descriptor node corresponding to each of the flash memory atomic operations to obtain N target descriptor chains to be executed includes: Mounting all the target descriptor nodes corresponding to one of the flash memory atomic operations to the end of one of the first free descriptor chains to obtain one of the target descriptor chains; The N first idle descriptor chains are configured one by one to obtain N target descriptor chains.

3. The descriptor chain management method according to claim 1, characterized in that: The traversing and executing the node status information of each target descriptor node of the target descriptor chain completed, performing node release processing and descriptor chain release processing to obtain a second idle descriptor chain, wherein the second idle descriptor chain is used to be called and configured as a new target descriptor chain, including: Traversing the node status information of each target descriptor node of the target descriptor chain that has completed execution, and obtaining the node execution result from the node status information; When the node execution result is correct, the configuration of the target descriptor node is cleared to obtain a second idle descriptor node; the second idle descriptor node is used to be configured as a new target descriptor node; After the traversal is completed, a descriptor chain release process is performed on the target descriptor chain that has been executed to obtain the second free descriptor chain.

4. The descriptor chain management method according to claim 3, characterized in that: The step of performing a descriptor chain release process on the target descriptor chain that has been executed to obtain the second idle descriptor chain includes: Marking the state of the target descriptor chain that has been executed as an idle state, to obtain the second idle descriptor chain; The second idle descriptor chain is placed back into the descriptor chain resource to be re-called and configured as a new target descriptor chain.

5. The descriptor chain management method according to claim 1, characterized in that: After performing the node release process and the descriptor chain release process to obtain the second idle descriptor chain, the method further includes: Determining the target descriptor chain to be executed; The descriptor chain status information and the node status information corresponding to the target descriptor chain that has been executed in the register unit are deleted.

6. A flash memory controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the descriptor chain management method as described in any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the flash memory controller as claimed in claim 6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the descriptor chain management method according to any one of claims 1 to 5.

Images