Task overload monitoring system and method for satellite communication

Abstract

The invention relates to a satellite communication task overload monitoring system and method. According to the system and the method, the programmable logic module is used for uniformly processing dog feeding of each processor and providing state information of all the processors, so that state interaction among the processors is facilitated, and when part of the processors are abnormal, the whole system can quickly respond to the abnormality and recover from the abnormal operation state according to the situation, so that the system is more convenient to use. The exception recovery capability of the whole system is improved, the exception time of the system is shortened, the use experience of a user is improved, and the problem that in the prior art, under an AMP architecture, when a certain processor of a multi-core multi-operation system is subjected to task overload or exception and the like is solved, the whole system can quickly respond and recover from the exception state.

Description

Technical Field

[0001] The present application relates to the field of satellite communications, and in particular to a mission overload monitoring system for satellite communications. Background Art

[0002] In satellite communication systems, in order to improve system performance, a multi-core operating system with AMP architecture is used. This multi-core system architecture can effectively increase the number of instructions executed per unit time, greatly improve system performance, and maximize the respective advantages of embedded systems and real-time operating systems, so as to independently and efficiently handle business functions with different needs at the same time. The AMP architecture, also known as a loosely coupled multi-CPU system, can contain multiple different or identical operating systems. Each processor has its own independent memory and devices, which is very suitable for application scenarios that require the simultaneous execution of multiple independent tasks. However, the hardware resources used by each operating system will be divided, and the cooperation between CPUs is very limited. This means that when some of the CPUs encounter problems such as task overload, they cannot respond in time, affecting the efficiency and stability of the system. Summary of the invention

[0003] In order to overcome the problems existing in the related technology, the present application provides a satellite communication task overload monitoring system and method. The task overload monitoring system is based on a logical monitoring scheme for task overload of an AMP architecture multi-core system, and a logic module control unit is designed. Together with a watchdog chip, it realizes rapid recovery when the processor task is overloaded or other abnormalities occur, thereby solving the problem in the prior art that a multi-core and multi-operating system under the AMP architecture has a task overload or abnormality in a certain processor.

[0004] On the one hand, the present application provides a satellite communication task overload monitoring system, which includes: a main processor, the main processor includes a system status monitoring module, a first configuration module and a first interrupt processing module; a coprocessor, the coprocessor includes a second configuration module and a second interrupt processing module; an FPGA programmable logic device, the FPGA programmable logic device includes a first configuration management module, a second configuration management module, a first state management module, a second state management module, a first watchdog management module, a second watchdog management module and a high-precision timing module; wherein the main processor is responsible for controlling the operation of the multiple coprocessors and the satellite communication system, and the system status monitoring module is used to monitor the status of the main processor and the multiple coprocessors; the first configuration module is used to configure the timer value of the first configuration management module, and the second configuration module is used to configure the timer value of the second configuration management module; the first interrupt processing module is used to send a dog feeding signal according to the timing period of the first configuration module to update the status of the first state management module; the second interrupt processing module sends a dog feeding signal according to the timing period of the second configuration module to update the status of the second state management module.

[0005] Preferably, the high-precision timing module is used to initiate an interrupt at a fixed time to notify the main processor and the coprocessor to feed the dog.

[0006] Preferably, it further includes a first watchdog chip and a second watchdog chip, wherein the first watchdog chip is used to reset the main processor according to the state of the first state management module, and the second watchdog chip is used to reset the coprocessor according to the state of the second state management module.

[0007] Preferably, the high-precision timing module is used to uniformly control the first watchdog management module and the second watchdog management module. The first watchdog management module is used to trigger the main processor interrupt according to the timing cycle, and control the first watchdog chip to feed the dog according to the processing situation of the main processor. The second watchdog management module is used to trigger the coprocessor interrupt according to the timing cycle, and control the second watchdog chip to feed the dog according to the processing situation of the coprocessor.

[0008] Preferably, the FPGA programmable logic device further includes an information exchange management module, and the information exchange management module serves as an expansion module for exchanging information between various processors.

[0009] On the other hand, the present application provides a task overload monitoring method for satellite communications, which includes: initializing a processor; configuring a dog feeding cycle of a configuration management module of an FPGA programmable logic device according to the initialization result of the processor; starting a high-precision timing module to control the watchdog management module of the FPGA programmable logic device to enter a periodic dog feeding state, and updating the operating state of the processor; calculating the dog feeding cycle of the configuration management module, and when the timer reaches a preset value in the timing cycle, accumulating the unfed dog count value of the configuration management module; judging whether the unfed dog count value of the configuration management module is abnormal; if the unfed dog count value of the configuration management module is not abnormal, sending a signal to the processor through the interrupt processing module of the processor, and if the unfed dog count value of the configuration management module is abnormal, updating the state of the state management module of the FPGA programmable logic device to be abnormal.

[0010] Preferably, if the unfed dog count value of the configuration management module is not abnormal, sending a signal to the processor through the interrupt processing module of the processor further includes: updating the status of the state management module of the FPGA programmable logic device to normal; activating the dog feeding thread of the processor; and clearing the unfed dog count value of the configuration management module through the dog feeding thread.

[0011] Preferably, if the unfed dog count value of the configuration management module is abnormal, then updating the state of the state management module of the FPGA programmable logic device as abnormal further includes: the processor includes a main processor and a coprocessor, the main processor includes a system state monitoring module, a first configuration module and a first interrupt processing module; the coprocessor includes a second configuration module and a second interrupt processing module; the configuration management module includes a first configuration management module and a second configuration management module, and the state management module includes a first state management module and a second state management module; if the unfed dog count of the first configuration management module is abnormal, updating the state of the first state management module to be abnormal, resetting the main processor through the first watchdog chip, and resetting the coprocessor through the second watchdog chip; if the unfed dog count of the second configuration management module is abnormal, updating the state of the second state management module to be abnormal, resetting the coprocessor through the second watchdog chip, and then detecting the state of the coprocessor through the system state monitoring module.

[0012] Preferably, the main processor also monitors the status of the coprocessor, and the steps include: starting the monitoring cycle of the system status monitoring module; reading the processor status value in the first status management module and the processor status value in the second status management module; judging whether the processor status value is abnormal, and if abnormal, suspending the services related to the coprocessor and waiting for the coprocessor to return to normal.

[0013] Preferably, the initialization of the processor further includes: system startup, powering on the processor; loading the logic program of the FPGA programmable logic device; creating a shared memory and writing the loading status of the FPGA programmable logic device; configuring the dog feeding cycle of the processor, initializing the dog feeding counter status, starting the dog feeding program of the processor, periodically feeding the dog, and updating the status of the processor.

[0014] The technical solution provided by the present application may include the following beneficial effects, by setting up the main processor and the coprocessor, and the FPGA programmable logic device. The FPGA programmable logic device implements a configuration management module, a status module, a watchdog management module, an extended information exchange management module, and a high-precision timer module. The control of the watchdog chip is to realize hierarchical processing to speed up the system abnormality recovery time. The watchdog chip of each coprocessor only controls the processor, while the watchdog corresponding to the main processor can control the reset of all processors. When the coprocessor is abnormal, only the abnormal processor is reset, and when the main processor is abnormal, the entire system is reset to achieve the purpose of optimizing the recovery speed. The system is based on the state recording module and information exchange module of the logic, which simplifies the state communication between multiple processors and improves efficiency.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0017] Figure 1 is a structural diagram of a satellite communication mission overload monitoring system shown in an embodiment of the present application;

[0018] Figure 2 is another structural diagram of a satellite communication mission overload monitoring system shown in one embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a satellite communication task overload monitoring method shown in an embodiment of the present application;

[0020] Figure 4 is another schematic diagram of a satellite communication mission overload monitoring method according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of the main processor initialization process shown in an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of a coprocessor initialization process shown in an embodiment of the present application;

[0023] Figure 7 is a schematic diagram of a main processor abnormal recovery process shown in an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a coprocessor abnormal recovery process shown in an embodiment of the present application;

[0025] Fig. 9 It is a schematic diagram of a main processor monitoring a coprocessor status process flow shown in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0027] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0028] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0029] The technical solution of the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0030] Figure 1 It is a structural diagram of a satellite communication mission overload monitoring system shown in one embodiment of the present application. Figure 2 This is another structural diagram of a satellite communication mission overload monitoring system shown in an embodiment of the present application.

[0031] See also Figure 1 to Figure 2 , a satellite communication mission overload monitoring system, the system comprising:

[0032] A main processor, the main processor includes a system status monitoring module, a first configuration module and a first interrupt processing module. A coprocessor, the coprocessor includes a second configuration module and a second interrupt processing module. An FPGA programmable logic device, the FPGA programmable logic device includes a first configuration management module, a second configuration management module, a first state management module, a second state management module, a first watchdog management module, a second watchdog management module, a first information exchange management module, a second information exchange management module and a high-precision timing module. In other embodiments, there can be one main processor and one coprocessor; or there can be one main processor and two coprocessors; or there can be one main processor and multiple coprocessors, etc., and the number of coprocessors is not limited.

[0033] The main processor is responsible for controlling the operation of the multiple coprocessors and the satellite communication system, and the system status monitoring module is used to monitor the status of the main processor and the multiple coprocessors. That is, the system status monitoring module is mainly responsible for monitoring the status of each processor, and when an abnormality occurs in the status of a processor, the exception handling program of the corresponding processor is started. The system status monitoring module obtains the status of the main processor by monitoring the first status management module, and obtains the status of the coprocessor by monitoring the second status management module.

[0034] The first configuration module is used to configure the timer value of the first configuration management module, and the second configuration module is used to configure the timer value of the second configuration management module. That is, after the main processor is powered on, the timed dog feeding cycle in the first configuration management module is initialized and set through the first configuration module; that is, after the coprocessor is powered on, the timed dog feeding cycle in the second configuration management module is initialized and set through the second configuration module. That is, in an FPGA programmable logic device, multiple configuration management modules are respectively set to correspond one-to-one with the configuration module of the main processor and the configuration module of the coprocessor.

[0035] The first interrupt processing module is used to send a dog feeding signal and update the state of the first state management module according to the timing cycle of the first configuration module. The second interrupt processing module sends a dog feeding signal and updates the state of the second state management module according to the timing cycle of the second configuration module, so that the system can uniformly process the dog feeding of multiple processors through a programmable logic module, and provide the state information of all processors, so as to facilitate the state interaction between processors. When an abnormality occurs in part, the entire system can respond to the abnormality quickly according to the situation and recover from the abnormal operation state, thereby improving the abnormal recovery ability of the entire system, shortening the system abnormality time, and improving the user experience.

[0036] In one of the embodiments, the high-precision timing module is used to initiate an interrupt at a fixed time to notify the main processor and the coprocessor to feed the dog.

[0037] In one embodiment, the system further comprises a first watchdog chip and a second watchdog chip, wherein the first watchdog chip is used to reset the main processor according to the state of the first state management module, and the second watchdog chip is used to reset the coprocessor according to the state of the second state management module. The first state management module is used to record the state information of the main processor of the current system, including normal and abnormal processing states; the second state management module is used to record the state information of the coprocessor of the current system, including normal and abnormal processing states.

[0038] In one embodiment, the high-precision timing module is used to uniformly control the first watchdog management module and the second watchdog management module. The first watchdog management module is used to trigger the main processor interrupt according to the timing cycle, and control the first watchdog chip to feed the dog according to the processing of the main processor. The second watchdog management module is used to trigger the coprocessor interrupt according to the timing cycle, and control the second watchdog chip to feed the dog according to the processing of the coprocessor. That is, in an FPGA programmable logic device, the following are respectively set: the first watchdog management module is used for the high-precision timing cycle, triggering the main processor interrupt, and controlling the first watchdog chip to feed the dog according to the processing of the main processor; and the second watchdog management module is used for the high-precision timing cycle, triggering the coprocessor interrupt, and controlling the second watchdog chip to feed the dog according to the processing of the coprocessor. That is, the system sets the first watchdog chip to start the relevant program for processing the main processor, and the second watchdog chip to start the relevant program for processing the coprocessor. If the processor cannot feed the dog regularly, the first watchdog chip and the second watchdog chip reset the specified processor as required.

[0039] In one embodiment, the FPGA programmable logic device further includes an information exchange management module, which is used as an extension module for information exchange between processors. That is, if there is a need for information exchange between processors, it can be processed through the information exchange management module in the FPGA.

[0040] This application uses an FPGA programmable logic device to set up a configuration management module, a status module, a watchdog management module, an extended information exchange management module, and a high-precision timer module on an FPGA programmable logic device. The FPGA programmable logic device controls multiple watchdog chips to achieve hierarchical processing to speed up the system abnormality recovery time. The watchdog chip of each coprocessor only controls the processor, while the watchdog corresponding to the main processor can control the reset of all processors. When the coprocessor is abnormal, only the abnormal processor is reset, and when the main processor is abnormal, the entire system is reset to achieve the purpose of optimizing the recovery speed. In this way, a programmable logic module is used to uniformly process the dog feeding program of each processor, and the status information of all processors is provided to facilitate the state interaction between processors. When an abnormality occurs in part, the entire system can respond to the abnormality quickly according to the situation and recover from the abnormal operation state, thereby improving the abnormal recovery ability of the entire system, shortening the system abnormality time, and improving the user experience.

[0041] The present application proposes a satellite communication task overload monitoring system including an FPGA programmable logic device, multiple processors, wherein CPU0 is the main processor, the others are coprocessors, and a watchdog chip module. The FPGA programmable logic device includes a high-precision timer, a configuration and status module. A satellite communication task overload monitoring method is as follows:

[0042] The first step is: system startup. After the main processor completes the loading of the FPGA logic program, it creates a shared memory, writes the FPGA loading status, configures the dog feeding cycle corresponding to the main processor in the FPGA, initializes the dog feeding counter status, and starts to periodically read the dog feeding counter status of other coprocessors in the configuration;

[0043] The second step is: after the coprocessor is started, open the shared memory. If the shared memory has not been created at this time, wait until it can be opened normally, read the loading completion status of the FPGA logic program, and if the status information of the FPGA logic program has not been written at this time, wait until the information of the FPGA logic program is written. After confirming that the FPGA loading is completed, configure the dog feeding cycle and initialize the status information;

[0044] The third step is: each processor starts a high-precision timer, enters a periodic dog feeding state, and updates the processor operation state;

[0045] The fourth step is: after the main processor obtains the configuration completion status of all coprocessors, it periodically reads the status information of each processor to grasp the operating status of each coprocessor;

[0046] The fifth step is: when the timing cycle of the corresponding timer of each processor is reached, the corresponding unfed dog count value is accumulated, and a signal is sent to the corresponding processor through an interrupt;

[0047] The sixth step is: if the processor runs normally, the corresponding dog feeding thread of the processor is scheduled, the dog feeding thread will clear the corresponding unfed dog count value, and set the automatic dog clearing control module to trigger dog feeding;

[0048] The seventh step is: the corresponding watchdog chip feeds the dog. If the coprocessor cannot feed the dog normally within the set period, the corresponding processor is reset to trigger system self-recovery.

[0049] The eighth step is: if the main processor cannot feed the dog normally, reset all processors and trigger the whole system to recover.

[0050] For details, see Figure 3 as well as Figure 4 , a satellite communication mission overload monitoring method, the method comprising:

[0051] S1, initialize the processor;

[0052] S2. According to the initialization result of the processor, configure a dog feeding cycle of a configuration management module of an FPGA programmable logic device;

[0053] S3, start the high-precision timing module, control the watchdog management module of the FPGA programmable logic device to enter the periodic dog feeding state, and update the operating state of the processor;

[0054] S4, calculating the dog feeding cycle of the configuration management module, and when the timer reaches a preset value in the timing cycle, accumulating the unfed dog feeding count value of the configuration management module;

[0055] S5, determining whether the unfed dog count value of the configuration management module is abnormal;

[0056] S6. If the unfed dog count value of the configuration management module is normal, a signal is sent to the processor through the interrupt processing module of the processor. If the unfed dog count value of the configuration management module is abnormal, the state of the state management module of the FPGA programmable logic device is updated to be abnormal.

[0057] In one embodiment, before step S1, initializing the processor further includes:

[0058] The system starts up and powers on the processor;

[0059] Load the logic program of the FPGA programmable logic device;

[0060] Create shared memory and write the loading status of the FPGA programmable logic device;

[0061] Configure the dog feeding cycle of the processor, initialize the dog feeding counter state, start the dog feeding program of the processor, feed the dog periodically, and update the state of the processor.

[0062] For details, see Figure 5 , Figure 5 This is a schematic diagram of the main processor initialization process. Initializing the main processor includes:

[0063] The system starts up and powers on the main processor;

[0064] Load the logic program of the FPGA programmable logic device;

[0065] Create shared memory and write the loading status of the FPGA programmable logic device;

[0066] Configure the dog feeding cycle of the main processor, initialize the dog feeding counter state of the first configuration management module, start the dog feeding program of the main processor, feed the dog periodically, and update the state of the main processor;

[0067] Determine whether the configuration of the coprocessor is completed. If completed, the dog feeding program is periodically executed to update the main processor status and obtain the coprocessor status regularly.

[0068] For details, see Figure 6 , Figure 6 This is a schematic diagram of the coprocessor initialization process. Initializing the coprocessor includes:

[0069] The system starts and powers on the coprocessor;

[0070] Open shared memory;

[0071] Determine whether the logic program loading of the FPGA programmable logic device is normal;

[0072] If the loading status of the FPGA programmable logic device is normal, configure the coprocessor's dog feeding cycle, initialize the dog feeding counter status of the second configuration management module, start the coprocessor's dog feeding program, feed the dog periodically, and update the coprocessor's status.

[0073] In one embodiment, if the unfed dog count value of the configuration management module is not abnormal, sending a signal to the processor through the interrupt processing module of the processor further includes:

[0074] Update the status of the state management module of the FPGA programmable logic device to normal;

[0075] Activate the dog feeding thread of the processor;

[0076] The unfed dog count value of the configuration management module is cleared by the dog feeding thread.

[0077] The above steps are called the processor interrupt handling function flow, which mainly include: first, starting the interrupt handling function, updating the status management module in the FPGA programmable logic device to the normal processor status, second, activating the dog feeding thread, and third, clearing the corresponding unfed dog counter value in the FPGA programmable logic device.

[0078] In one embodiment, if the unfed dog count value of the configuration management module is abnormal, then updating the state of the state management module of the FPGA programmable logic device as abnormal further includes: the processor includes a main processor and a coprocessor, the main processor includes a system state monitoring module, a first configuration module and a first interrupt processing module. The coprocessor includes a second configuration module and a second interrupt processing module. The configuration management module includes a first configuration management module and a second configuration management module, and the state management module includes a first state management module and a second state management module.

[0079] If the unfed watchdog count of the first configuration management module is abnormal, the state of the first state management module is updated to be abnormal, the main processor is reset through the first watchdog chip, and the coprocessor is reset through the second watchdog chip. This step is the abnormal recovery process of the main processor. For details, see Figure 7 , Figure 7 The main processor abnormal recovery process diagram mainly includes the following steps:

[0080] The main processor's unfed dog count is abnormal;

[0081] The dog clearing control module of the main processor did not receive the dog clearing signal;

[0082] Control the first watchdog chip to reset the main processor;

[0083] Control the second watchdog chip to reset all coprocessors;

[0084] Wait for the entire system to restart and go through the initialization power-on process again.

[0085] If the unfed watchdog count of the second configuration management module is abnormal, the state of the second state management module is updated to abnormal, the coprocessor is reset through the second watchdog chip, and then the state of the coprocessor is detected through the system state monitoring module. This is the step of coprocessor abnormal recovery. For details, see Figure 8 , Figure 8 This is a schematic diagram of the coprocessor exception recovery process, which mainly includes the following steps:

[0086] The unfed dog count of the coprocessor is abnormal;

[0087] The dog clearing control module of the coprocessor did not receive the dog clearing signal;

[0088] Control the second watchdog chip to reset the corresponding coprocessor;

[0089] Wait for the coprocessor to be reset and restored;

[0090] Wait for the main processor to detect that the coprocessor has returned to normal and start related services.

[0091] In one embodiment, the main processor also includes a state process of monitoring the coprocessor. For details, see Fig. 9 , Fig. 9 A schematic diagram of the process flow for monitoring the coprocessor status for the main processor, wherein the steps include:

[0092] Starting a monitoring cycle of the system status monitoring module;

[0093] Reading a processor state value in the first state management module and a processor state value in the second state management module;

[0094] Determine whether the processor status value is abnormal, and if so, suspend the services related to the coprocessor and wait for the coprocessor to return to normal;

[0095] Wait until the coprocessor-related services are restored and wait to enter the next monitoring cycle.

[0096] The technical solution provided by the present application may include the following beneficial effects: Based on a logic-based solution for monitoring task overload of a multi-core system of an AMP architecture, a logic module control unit is designed, which together with a watchdog chip realizes rapid recovery when the processor task is overloaded or other abnormalities occur. At the same time, a logic-based state recording module and an information exchange module are designed to simplify the state communication between multiple processors and improve efficiency. The present application uses a programmable logic module to uniformly process the feeding of each processor, and provides the state information of all processors, so as to facilitate the state interaction between processors. When an abnormality occurs in part, the entire system can respond to the abnormality quickly as a whole according to the situation, and recover from the abnormal operating state, thereby improving the abnormal recovery capability of the entire system, shortening the system abnormality time, and improving the user experience. It solves the existing technology that when a task overload or abnormality occurs in a processor of a multi-core multi-operating system under the AMP architecture, the entire system of the present application can respond quickly and recover from the abnormal state.

[0097] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A satellite communication mission overload monitoring system, characterized in that: include: A main processor, the main processor comprising a system status monitoring module, a first configuration module and a first interrupt processing module; A coprocessor, the coprocessor comprising a second configuration module and a second interrupt processing module; An FPGA programmable logic device, the FPGA programmable logic device comprising a first configuration management module, a second configuration management module, a first state management module, a second state management module, a first watchdog management module, a second watchdog management module and a high-precision timing module; The main processor is responsible for controlling the operation of the multiple coprocessors and the satellite communication system, and the system status monitoring module is used to monitor the status of the main processor and the multiple coprocessors; The first configuration module is used to configure a timer value of the first configuration management module, and the second configuration module is used to configure a timer value of the second configuration management module; The first interrupt processing module is used to send a dog feeding signal according to the timing cycle of the first configuration module to update the state of the first state management module; The second interrupt processing module sends a dog feeding signal according to the timing cycle of the second configuration module to update the state of the second state management module.

2. The satellite communication mission overload monitoring system according to claim 1, characterized in that: The high-precision timing module is used to initiate an interrupt at a fixed time to notify the main processor and the coprocessor to feed the dog.

3. The satellite communication mission overload monitoring system according to claim 2, characterized in that: It further includes a first watchdog chip and a second watchdog chip, wherein the first watchdog chip is used to reset the main processor according to the state of the first state management module, and the second watchdog chip is used to reset the coprocessor according to the state of the second state management module.

4. The satellite communication mission overload monitoring system according to claim 3, characterized in that: The high-precision timing module is used to uniformly control the first watchdog management module and the second watchdog management module. The first watchdog management module is used to trigger the main processor interrupt according to the timing cycle, and control the first watchdog chip to feed the dog according to the processing situation of the main processor. The second watchdog management module is used to trigger the coprocessor interrupt according to the timing cycle, and control the second watchdog chip to feed the dog according to the processing situation of the coprocessor.

5. The satellite communication mission overload monitoring system according to claim 1, characterized in that: The FPGA programmable logic device also includes an information exchange management module, which serves as an expansion module and is used to exchange information between various processors.

6. A satellite communication mission overload monitoring method, characterized in that: Initialize the processor; According to the initialization result of the processor, a dog feeding cycle of a configuration management module of an FPGA programmable logic device is configured; Start the high-precision timing module, control the watchdog management module of the FPGA programmable logic device to enter the periodic watchdog feeding state, and update the operating state of the processor; Calculate the dog feeding cycle of the configuration management module, and when the timer reaches a preset value in the timing cycle, accumulate the unfed dog feeding count value of the configuration management module; Determine whether the unfed dog count value of the configuration management module is abnormal; If the unfed dog count value of the configuration management module is normal, a signal is sent to the processor through the interrupt processing module of the processor. If the unfed dog count value of the configuration management module is abnormal, the state of the state management module of the FPGA programmable logic device is updated to be abnormal.

7. The satellite communication mission overload monitoring system according to claim 6, characterized in that: If the unfed dog count value of the configuration management module is not abnormal, sending a signal to the processor through the interrupt processing module of the processor further includes: Update the status of the state management module of the FPGA programmable logic device to normal; Activate the dog feeding thread of the processor; The unfed dog count value of the configuration management module is cleared by the dog feeding thread.

8. The satellite communication mission overload monitoring system according to claim 7, characterized in that: If the unfed dog count value of the configuration management module is abnormal, updating the state of the state management module of the FPGA programmable logic device to be abnormal further includes: The processor includes a main processor and a coprocessor, and the main processor includes a system status monitoring module, a first configuration module and a first interrupt processing module; The coprocessor includes a second configuration module and a second interrupt processing module; The configuration management module includes a first configuration management module and a second configuration management module, and the state management module includes a first state management module and a second state management module; If the unfed watchdog count of the first configuration management module is abnormal, the state of the first state management module is updated to be abnormal, the main processor is reset through the first watchdog chip, and the coprocessor is reset through the second watchdog chip; If the unfed watchdog count of the second configuration management module is abnormal, the state of the second state management module is updated to be abnormal, the coprocessor is reset through the second watchdog chip, and then the state of the coprocessor is detected through the system state monitoring module.

9. The satellite communication mission overload monitoring system according to claim 6, characterized in that: The main processor also monitors the status of the coprocessor, and the steps include: Starting a monitoring cycle of the system status monitoring module; Reading a processor state value in the first state management module and a processor state value in the second state management module; Determine whether the processor status value is abnormal. If abnormal, suspend the services related to the coprocessor and wait for the coprocessor to return to normal.

10. The satellite communication mission overload monitoring system according to claim 6, characterized in that: Initializing the processor further includes: The system starts up and powers on the processor; Load the logic program of the FPGA programmable logic device; Create shared memory and write the loading status of the FPGA programmable logic device; Configure the dog feeding cycle of the processor, initialize the dog feeding counter state, start the dog feeding program of the processor, feed the dog periodically, and update the state of the processor.

Images