Chip test system, method and device, terminal equipment and readable storage medium

Abstract

The invention is suitable for the technical field of chip testing, and provides a chip testing system, method and device, terminal equipment and a readable storage medium, and the system is characterized in that the system comprises a probe station and a tester; the tester obtains level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, the level information comprises a high level and a low level, and N is greater than or equal to 1; the tester carries out quantity statistics on level information corresponding to each bit of the to-be-tested signal in N signal periods so as to determine the maximum continuous high level quantity and the maximum continuous low level quantity; the tester carries out calculation according to the maximum continuous high level number and the maximum continuous low level number to obtain the duty ratio of the chip to be tested; and the tester sends the duty ratio of the chip to be tested to the probe station. The chip duty ratio testing device is extremely high in practicability, easy to use and capable of rapidly and accurately testing the chip duty ratio.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and in particular, relates to a chip testing system, method, apparatus, terminal equipment and readable storage medium. Background Art

[0002] In the field of chip testing technology, since the duty cycle has a significant impact on the function and performance of the chip, it is particularly important to test whether the chip duty cycle complies with the design rules.

[0003] The duty cycle of a chip refers to the proportion of the time in a high level (or low level) state in a time period to the entire time period. The chip duty cycle has an important impact on the function and performance of the chip. The chip duty cycle directly affects its power consumption and the heat generated. Generally speaking, the higher the duty cycle, the greater the power consumption of the chip and the more heat it generates. Therefore, for applications that require low power consumption and low heat, the chip duty cycle needs to be minimized. The chip duty cycle affects the stability and reliability of its operation. Especially when running at high frequencies, an inappropriate duty cycle may cause signal distortion and circuit instability. Therefore, for applications that require high stability and reliability, the chip duty cycle needs to be precisely controlled. In communication systems, the chip duty cycle directly affects the communication rate. The higher the duty cycle, the higher the frequency of the signal and the faster the communication rate. Therefore, when designing a communication chip, it is necessary to reasonably select the duty cycle according to the communication requirements to achieve the required communication rate. In some applications, the timing requirements of the chip have strict restrictions on the duty cycle. For example, for some timing-sensitive applications, such as high-speed bus communication or synchronous data transmission, the duty cycle must be within a certain range to meet the timing requirements, otherwise it may cause communication errors or data loss. The duty cycle of the chip will also affect its circuit design. When designing, it is necessary to consider the impact of the duty cycle on the circuit, such as clock division, power management and signal processing, to ensure the normal operation of the circuit and the achievement of performance indicators.

[0004] However, when the existing hardware environment does not support the use of the time management unit (TMU) hardware resources, the chip duty cycle cannot be measured. Summary of the invention

[0005] The embodiments of the present application provide a chip testing system, method, apparatus, terminal device and readable storage medium, which can solve the problem that the chip duty cycle cannot be measured when the existing hardware environment does not support the use of the time management unit (TMU) hardware resources.

[0006] In a first aspect, an embodiment of the present application provides a chip testing system, comprising: a probe station and a tester, wherein the probe station is electrically connected to the tester;

[0007] The tester obtains level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1;

[0008] The tester counts the level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0009] The tester calculates according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain a duty cycle of the chip to be tested;

[0010] The tester sends the duty cycle of the chip to be tested to the probe station.

[0011] In a possible implementation of the first aspect, obtaining level information corresponding to each bit of the test signal of the test chip in N signal cycles includes:

[0012] Based on the capture and storage function, the level information of the chip pin signal is captured to obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles.

[0013] In a possible implementation of the first aspect, the chip testing system further includes a probe card disposed on the probe station, and the tester obtains a signal to be tested of the chip to be tested through the probe card.

[0014] In a possible implementation manner of the first aspect, N≤2.

[0015] In a possible implementation of the first aspect, the step of performing quantitative statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine a maximum number of consecutive high levels and a maximum number of consecutive low levels includes:

[0016] Determine whether level information corresponding to the first bit to the last bit of the signal to be tested in N signal cycles is a high level or a low level;

[0017] When the current bit is at a high level, continue to determine whether each subsequent bit is at a high level. When a subsequent bit is at a high level, the number of consecutive high levels increases by 1 until the subsequent bit is at a low level. If there is no subsequent bit, the process ends.

[0018] When the subsequent bit is at a low level, determine whether the current number of consecutive high levels after one or more increases by 1 is greater than a first number threshold, if so, update the first number threshold to the current number of consecutive high levels, set the current number of consecutive low levels to 1, and go to the step of the current bit being at a low level, wherein the first number threshold is initially 1;

[0019] When the current bit is at a low level, continue to determine whether each subsequent bit is at a low level. When a subsequent bit is at a low level, the number of consecutive low levels increases by 1 until the subsequent bit is at a high level. If there is no subsequent bit, the process ends.

[0020] When the subsequent bit is at a high level, determine whether the current number of consecutive low levels after one or more increases by 1 is greater than a second number threshold, if greater, update the second number threshold to the current number of consecutive low levels, set the current number of consecutive high levels to 1, and go to the step of the current bit being at a high level, wherein the second number threshold is initially 1;

[0021] When the level information corresponding to the last bit is determined, the current first quantity threshold is determined as the maximum number of consecutive high levels, and the current second quantity threshold is determined as the maximum number of consecutive low levels.

[0022] In a possible implementation of the first aspect, the step of calculating according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested includes:

[0023] Determine the total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0024] The duty cycle of the chip to be tested is determined according to the total number of levels and any one of the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0025] In a second aspect, an embodiment of the present application provides a chip testing method, comprising:

[0026] Obtaining level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1;

[0027] Performing quantitative statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0028] The duty cycle of the chip to be tested is obtained by performing calculation according to the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0029] In a third aspect, an embodiment of the present application provides a chip testing device, including:

[0030] An information acquisition module, used to obtain level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1;

[0031] A quantity statistics module, used for performing quantity statistics on level information corresponding to each bit of the signal to be tested in N signal cycles, so as to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0032] The result calculation module is used to calculate according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested.

[0033] In a fourth aspect, an embodiment of the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip testing method described in the second aspect when executing the computer program.

[0034] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the chip testing method described in the second aspect is implemented.

[0035] The beneficial effect of the embodiment of the present application compared with the prior art is that the embodiment of the present application realizes the technical effect of realizing chip duty cycle test without using the hardware resources of the timing module and without changing the hardware design, and the embodiment of the present application does not need manual manual zone welding circuit and does not need to change the existing test resources. The embodiment of the present application cooperates with each other through the probe station and the tester electrically connected to each other, and the tester obtains the level information corresponding to each bit of the signal to be tested of the chip to be tested in N signal cycles, and the tester counts the level information corresponding to each bit of the signal to be tested in N signal cycles, to determine the maximum number of continuous high levels and the maximum number of continuous low levels, and the tester calculates according to the maximum number of continuous high levels and the maximum number of continuous low levels, and obtains the duty cycle of the chip to be tested, and the tester sends the duty cycle of the chip to be tested to the probe station. After actual verification, the present invention is extremely practical, simple to use, and can quickly and accurately test the chip duty cycle.

[0036] After practice and application in actual production, this application can simply and quickly meet customers' requirements for chip duty cycle testing. The debugging is simple and easy to understand, the debugging cycle is short, and a lot of time is saved, making the debugging work more efficient, fast, and high-quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 is a schematic diagram of a chip testing system provided by an embodiment of the present application;

[0039] Figure 2 It is a schematic diagram of resource allocation of a square card public board of a Chroma tester provided in an embodiment of the present application;

[0040] Figure 3 This application is in Figure 1 A schematic diagram of a flow chart provided based on an embodiment of a chip testing system;

[0041] Figure 4 This application is in Figure 1 Another flow chart provided based on the chip testing system embodiment;

[0042] Figure 5 It is a flowchart of a program operation provided by an application embodiment of the present application;

[0043] Figure 6 is a flowchart of a chip testing method provided by another embodiment of the present application;

[0044] Figure 7 is a schematic structural diagram of a chip testing device provided by another embodiment of the present application;

[0045] Figure 8 This is a diagram showing an example of the structure of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0047] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0048] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0049] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0050] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0051] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0052] Since the chip duty cycle has an important impact on the function and performance of the chip, it is particularly important to test whether the chip duty cycle meets the design rules. So how to implement the chip duty cycle test without using the timing module hardware resources? The present invention is a chip testing solution proposed to solve this technical problem, to test whether the chip duty cycle can meet the expectations of the chip design.

[0053] Figure 1 Schematic diagram of a chip testing system provided by an embodiment of the present application. Figure 1As shown, the system includes a probe station 10 and a tester 11 , and the probe station 10 is electrically connected to the tester 11 .

[0054] The probe station 10 may be, for example, a UF300 probe station. The UF300 probe station is a fully automatic universal probe station (Prober) suitable for various applications with a modular concept, a six-level Z axis, an SR-3300 visual system, and a laser pattern recognition function. The UF300 probe station is capable of high-precision wafer and die testing with maximum throughput and accuracy while requiring minimal manual intervention.

[0055] The tester 11 may be, for example, a Chroma tester, which is a widely used chip tester.

[0056] Here, the probe station 10 can control the movement of the wafer so that each chip at different positions of the wafer is tested. After the tester 11 tests the duty cycle of different chips on the wafer, it sends the duty cycle of different chips to the probe station 10. The probe station 10 can determine whether the chip meets the design expectations based on the duty cycle of each chip, for example, whether the duty cycle is within the range of 49%-51%. The probe station 10 and the tester 11 jointly complete the test of the chip.

[0057] In one embodiment, the chip test system may further include a signal source. The signal source transmits an input signal (the input signal frequency is, for example, 10 kHz) to the tester 11 through a signal line. The tester 11 transmits the input signal to the chip for the chip to be tested to work normally. Here, the chip to be tested needs to be continuously supplied with input signals and VDD voltage for normal operation.

[0058] In one embodiment, the chip testing system further includes a probe card disposed on the probe station 10 , and the tester 11 obtains a test signal of the chip to be tested through the probe card.

[0059] Here, the probe card can be, for example, a square card public board of a Chroma tester, with a total of 16 sites. For the corresponding resource allocation, see Figure 2 , the embodiments of the present application use the SDA and SCL pins.

[0060] Here, the probe station 10 can control the movement of the wafer so that each chip at a different position of the wafer contacts the probe card to perform chip testing.

[0061] The embodiment of the present application utilizes a probe card to transmit the test signal of the chip to be tested to the tester. Testing can be performed by slightly modifying the test vector (pattern) of the tested pin without changing the hardware environment. This can improve the convenience and ease of data transmission and the convenience of debugging.

[0062] Figure 3 is Figure 1 A schematic diagram of a flow chart provided based on an embodiment of a chip testing system.

[0063] like Figure 3 As shown, in S11, the tester 11 obtains level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1.

[0064] Here, the signal period of the signal to be tested can be determined based on the frequency of the signal to be tested. The distribution of the high level and low level information of the signal to be tested in each signal period is the same. For example, a signal period of the signal to be tested is 6ms, which includes level information of 6 bits, the first 3 bits are high level and the last 3 bits are low level. It can be understood that the signal to be tested will be repeated continuously in this way. Since it is impossible to determine the specific time point at which each signal period of the signal to be tested starts, the tester 11 can obtain the level information corresponding to each bit of the signal to be tested of the chip to be tested in more than 1 signal period, so as to obtain at least one complete signal period of the signal to be tested.

[0065] In one embodiment, 1≤N≤2. For example, N may be 1.5, 1.6, 1.7, 1.8, etc.

[0066] The embodiment of the present application is configured to obtain a test signal within 1 to 2 signal cycles, which can quickly perform chip testing on the one hand, and ensure the reliability of the chip testing results on the other hand, thereby improving the effectiveness of the overall chip testing solution.

[0067] In one embodiment, the tester 11 obtains level information corresponding to each bit of the test signal of the test chip in N signal cycles, including:

[0068] The tester 11 captures the level information of the chip pin signal based on the capture memory function to obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles. Here, the tester 11 is, for example, a Chroma tester, and the Capture Memory function of the Chroma tester can digitize the waveform. The Chroma tester captures K through the Capture Memory function, and the program statement is "SET_CAPTURE_MEM_MODE(Pin_name,PEL_K,ON,16K)".

[0069] Here, the Capture Memory function of the Chroma tester can record and capture the three states of the chip under test output: high level (H), low level (L), and high impedance (Z):

[0070] -Read the readings in some registers of the chip under test, such as analog-to-digital conversion data (ADC convert data), trimming data, etc.

[0071] -When customers need to reflect some data information in the chip register (such as Unique ID, etc.) more intuitively in the test data (datalog), they need to use Capture Memory to read back and process the data, and then print it into the data (log) through JUDGE_VARIABLE.

[0072] -Generally, the IMATCH function cannot process the signals. You need to use Capture Memory to read back all the signals within a period of time and then process them through the algorithm.

[0073] The overall function overview of the Chroma tester's Capture Memory function includes:

[0074] -MXLPC / SNPEC default function, supported by 3360 / 3380 series.

[0075] -Each group has 8 pins, and a group supports a maximum of 64K data per single pin, and a minimum of 8K data per pin.

[0076] -Supports 3 capture modes (PEL, PEH, PFAIL).

[0077] -Supports 2 trigger modes (H / L / Z fail trigger within pattern, K symbol trigger within pattern).

[0078] -Any pin can be assigned to any site (supported in APAS mode).

[0079] -The maximum supported test pattern frequency is 100Mhz.

[0080] Here, the embodiment of the present application utilizes the capture memory function of the Chroma tester to capture the level information of the chip pin signal, so that the chip duty cycle can be tested without using the hardware resources of the timing module, which greatly saves hardware costs and improves usage efficiency.

[0081] In S12 , the tester 11 counts the level information corresponding to each bit of the test signal in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0082] Here, the maximum number of consecutive high levels refers to the number corresponding to the maximum number of high levels that appear when multiple bits appear continuously at high levels in N signal cycles. The maximum number of consecutive low levels refers to the number corresponding to the maximum number of low levels that appear when multiple bits appear continuously at low levels in N signal cycles. For example, 2 consecutive high levels and then 2 consecutive low levels appear in 1 signal cycle (4 bits). The tester 11 obtains 1.5 signal cycles (6 bits), and the levels of the corresponding bits are: 1 high level, 2 low levels, 2 high levels, and 1 low level. The tester 11 counts the level information corresponding to each bit in these 1.5 signal cycles, and determines that the maximum number of consecutive high levels is 2 and the maximum number of consecutive low levels is 2.

[0083] Those skilled in the art should understand that there is no strict order between steps S11 and S12. In one embodiment, the tester 11 may obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles, and then perform a step of counting the level information corresponding to each bit of the test signal in N signal cycles. In another embodiment, the tester 11 may also obtain the level information corresponding to the first bit of the test signal of the test chip in N signal cycles, and then perform a step of counting the level information corresponding to the first bit. Subsequently, the tester 11 obtains the level information corresponding to the second bit of the test signal of the test chip in N signal cycles, and then performs a step of counting the level information corresponding to the second bit. This is analogous to the case until the tester 11 obtains the level information corresponding to the last bit of the test signal of the test chip in N signal cycles, and then performs a step of counting the level information corresponding to the last bit. Those skilled in the art should understand that the tester 11 can also set other time sequences for performing S11 and S12 according to actual needs, and the technical solution of the tester 11 performing S11 and S12 in other time sequences should also fall within the scope of protection of this application.

[0084] In one embodiment, Figure 4 As shown, the level information corresponding to each bit of the signal to be tested in N signal cycles is counted to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels, including:

[0085] S51: Determine whether the level information corresponding to the first bit to the last bit of the signal to be tested in N signal cycles is a high level or a low level; if the first bit is a high level, go to S521; if the first bit is a low level, go to S531;

[0086] S521: When the current bit is at a high level, continue to determine whether each subsequent bit is at a high level. When a subsequent bit is at a high level, the number of consecutive high levels increases by 1, until the subsequent bit is at a low level, and then go to S522. If there is no subsequent bit, end;

[0087] S522: when the subsequent bit is at a low level, determine whether the current number of consecutive high levels after one or more increases by 1 is greater than the first number threshold, if so, update the first number threshold to the current number of consecutive high levels, set the current number of consecutive low levels to 1, and go to step S531 where the current bit is at a low level, wherein the first number threshold is initially 1;

[0088] S531: When the current bit is at a low level, continue to determine whether each subsequent bit is at a low level. When a subsequent bit is at a low level, the number of consecutive low levels increases by 1, until the subsequent bit is at a high level, and then go to S532. If there is no subsequent bit, end;

[0089] S532: when the subsequent bit is at a high level, determine whether the current number of consecutive low levels after one or more increases by 1 is greater than a second number threshold, if so, update the second number threshold to the current number of consecutive low levels, set the current number of consecutive high levels to 1, and go to step S521 where the current bit is at a high level, wherein the second number threshold is initially 1;

[0090] S54: When the level information corresponding to the last bit is determined, the current first quantity threshold is determined as the maximum number of consecutive high levels, and the current second quantity threshold is determined as the maximum number of consecutive low levels.

[0091] Following the previous example, 2 consecutive high levels followed by 2 consecutive low levels appear in 1 signal cycle (4 bits). The tester 11 obtains 1.5 signal cycles (6 bits), and the levels of the corresponding bits are: 1 high level, 2 low levels, 2 high levels, and 1 low level. In S51, the tester 11 continues to determine the level information corresponding to the first bit to the sixth bit in the 1.5 signal cycles of the signal to be tested. Since the first bit is a high level, go to S521. In S521, the tester 11 determines whether the subsequent second bit is a high level. Since the second bit is a low level, not a high level, and the number of consecutive high levels does not increase by 1, go to S522. In S522, the current number of consecutive high levels is 1, which is not greater than the first number threshold (1), so go to S531. In S531, the tester 11 determines that the second bit is a low level and the third bit is a low level, then the number of continuous low levels increases by 1, until the tester 11 determines that the fourth bit is a high level, and then the process goes to S532. In S532, the current number of continuous low levels (2) after an increase of 1 is greater than the second number threshold (1), then the second number threshold is updated to 2. Since the fourth bit is a high level, the current number of continuous high levels is 1, and the process goes to S521 for the second time. When the process goes to S521 for the second time, the tester 11 determines that the fourth bit is a high level and the fifth bit is a high level, then the number of continuous high levels increases by 1, until the tester 11 determines that the sixth bit is a low level, and then the process goes to S522 for the second time. When the process goes to S522 for the second time, the current number of continuous high levels (2) after an increase of 1 is greater than the first number threshold (1), then the first number threshold is updated to 2. Since the sixth bit is a low level, the current number of continuous low levels is 1, and the process goes to S531 for the second time. When the process goes to S531 for the second time, since there is no subsequent bit, the tester 11 ends this step. In S54, when the level information corresponding to the last (sixth) bit is determined, the current first number threshold (2) is determined as the maximum number of continuous high levels, and the current second number threshold (2) is determined as the maximum number of continuous low levels.

[0092] The embodiment of the present application obtains the maximum number of consecutive high levels and the maximum number of consecutive low levels through cyclic calculation, which can simply and quickly meet customers' requirements for chip duty cycle testing. The debugging cycle is short, making the debugging work more efficient, fast and high-quality.

[0093] In S13 , the tester 11 calculates the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested.

[0094] Continuing with the previous example, the tester 11 calculates the maximum number of consecutive high levels (2) and the maximum number of consecutive low levels (2) to obtain the duty cycle of the chip to be tested = 2 / (2+2) = 50%.

[0095] In one embodiment, calculating according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested includes:

[0096] Determine the total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0097] The duty cycle of the chip to be tested is determined according to the total number of levels and any one of the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0098] Here, the total number of levels is the sum of the maximum number of consecutive high levels and the maximum number of consecutive low levels. The tester 11 can determine the ratio of the maximum number of consecutive high levels to the total number of levels as the duty cycle. The tester 11 can also determine the ratio of the maximum number of consecutive low levels to the total number of levels as the duty cycle.

[0099] The embodiment of the present application simplifies the duty cycle test algorithm and scheme by using the maximum number of consecutive high levels and the maximum number of consecutive low levels to calculate the duty cycle of the chip to be tested, and can simply and quickly meet customer needs for chip duty cycle testing.

[0100] In S14 , the tester 11 sends the duty cycle of the chip to be tested to the probe station 10 .

[0101] Here, the tester 11 sends the calculated duty cycle of the chip to be tested to the probe station 10. The probe station 10 can determine whether the chip to be tested is qualified based on whether the determined duty cycle (eg, 50%) meets a predetermined interval (eg, 49%-51%).

[0102] In one embodiment, the tester 11 and the probe station 10 may also print the duty cycle results into the test record.

[0103] In order to solve the technical problem of duty cycle test on chip in the case of no module hardware resources, the embodiment of the present application realizes the technical effect of realizing chip duty cycle test without changing hardware design, the embodiment of the present application only needs to simply modify the test vector (pattern) of the tested pin and the program code of the tester, and does not need to manually weld circuits in the area, and does not need to change existing test resources. The embodiment of the present application cooperates with each other by probe station and tester, and the level information corresponding to each bit position of the signal to be tested of the chip to be tested in N signal cycles is obtained by the tester, and the level information corresponding to each bit position of the signal to be tested in N signal cycles is counted by the tester, to determine the maximum number of continuous high levels and the maximum number of continuous low levels, and the tester is calculated according to the maximum number of continuous high levels and the maximum number of continuous low levels, and the duty cycle of the chip to be tested is obtained, and the duty cycle of the chip to be tested is sent to the probe station by the tester. Through actual verification, the present invention is extremely practical, simple to use, and can quickly and accurately test chip duty cycle.

[0104] After practice and application in actual production, the embodiments of the present application can simply and quickly meet customers' requirements for chip duty cycle testing. The debugging is simple and easy to understand, the debugging cycle is short, and a lot of time is saved, making the debugging work more efficient, fast, and high-quality.

[0105] In an application embodiment, the present application scheme can be implemented through a program. When the program starts running, K will be captured through the Capture Memory function of the Chroma tester first. The program statement is "SET_CAPTURE_MEM_MODE(Pin_name, PEL_K, ON, 16K)". Before testing, it is necessary to know the size of the test frequency, and 1.5 signal cycles are optimal. Then, the maximum number of consecutive high levels (H) and the maximum number of consecutive low levels (L) are filtered out through the for loop and if statement. Finally, the chip duty cycle result is obtained by calculating (H / H+L)*100%. The program statements are as follows:

[0106]

[0107]

[0108] Figure 5 The following is a flowchart of the above program. Figure 5As shown, in S501, the Capture Memory function of the Chroma tester captures K. In S502, the Chroma tester calculates the maximum number of consecutive high levels, that is, the maximum number of high levels (H) that appear. In S503, the Chroma tester calculates the maximum number of consecutive low levels, that is, the maximum number of low levels (L) that appear. In S504, the Chroma tester calculates the chip duty cycle, that is, Cuty=H / (H+L)*100%. In S505, the Chroma tester ends the calculation. In S506, the Chroma tester prints the results to the test log.

[0109] Figure 6 It is a flowchart of a chip testing method provided in another embodiment of the present application.

[0110] like Figure 6 As shown, the chip testing method includes:

[0111] S61, obtaining level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1.

[0112] S62, performing quantity statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0113] S63, performing calculation according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain a duty cycle of the chip to be tested.

[0114] Another embodiment of the present invention discloses another chip testing method. Figure 6 Based on the corresponding embodiment, step S61 specifically includes:

[0115] Based on the Capture Memory function of the tester, the level information of the chip pin signal is captured to obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles.

[0116] Another embodiment of the present invention discloses another chip testing method. Figure 6 On the basis of the corresponding embodiment, the test signal of the chip to be tested is obtained through a probe card, and the probe card is arranged on a probe station.

[0117] Another embodiment of the present invention discloses another chip testing method. Figure 6 On the basis of the corresponding embodiment, 1≤N≤2.

[0118] Another embodiment of the present invention discloses another chip testing method. Figure 6 Based on the corresponding embodiment, step S62 specifically includes:

[0119] S621: Continue to determine whether the level information corresponding to the first bit to the last bit of the signal to be tested in N signal cycles is a high level or a low level; if the first bit is a high level, go to S6221; if the first bit is a low level, go to S6231;

[0120] S6221: When the current bit is at a high level, continue to determine whether each subsequent bit is at a high level. When a subsequent bit is at a high level, the number of consecutive high levels increases by 1, until the subsequent bit is at a low level, and then go to S6222. If there is no subsequent bit, end;

[0121] S6222: Determine whether the current number of consecutive high levels after one or more increases by 1 is greater than the first number threshold, if so, update the first number threshold to the current number of consecutive high levels, set the current number of consecutive low levels to 1, and go to S6231, where the first number threshold is initially 1;

[0122] S6231: When the current bit is at a low level, continue to determine whether each subsequent bit is at a low level. When a subsequent bit is at a low level, the number of consecutive low levels increases by 1, until the subsequent bit is at a high level, and then go to S6232. If there is no subsequent bit, end;

[0123] S6232: Determine whether the current number of consecutive low levels after one or more increases by 1 is greater than a second number threshold, if so, update the second number threshold to the current number of consecutive low levels, set the current number of consecutive high levels to 1, and go to S6221, where the second number threshold is initially 1;

[0124] S624: When the level information corresponding to the last bit is determined, the current first quantity threshold is determined as the maximum number of consecutive high levels, and the current second quantity threshold is determined as the maximum number of consecutive low levels.

[0125] Another embodiment of the present invention discloses another chip testing method. Figure 6 Based on the corresponding embodiment, step S63 includes:

[0126] Determine the total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0127] The duty cycle of the chip to be tested is determined according to the total number of levels and any one of the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0128] Figure 7 It is a structural block diagram of a chip testing device provided in another embodiment of the present application.

[0129] like Figure 7 As shown, the chip testing device includes:

[0130] The information acquisition module 71 is used to obtain level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes high level and low level, and N≥1.

[0131] The quantity statistics module 72 is used to perform quantity statistics on the level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0132] The result calculation module 73 is used to calculate according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested.

[0133] Another embodiment of the present invention discloses another chip testing device. Figure 7 Based on the corresponding embodiment, the information obtaining module 71 includes:

[0134] The first obtaining unit captures the level information of the chip pin signal based on the capture memory function of the tester to obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles.

[0135] Another embodiment of the present invention discloses another chip testing device. Figure 7 On the basis of the corresponding embodiment, the information obtaining module 71 is used to obtain the test signal of the chip to be tested through a probe card, and the probe card is arranged on the probe station.

[0136] Another embodiment of the present invention discloses another chip testing device. Figure 7 Based on the corresponding embodiment, N≤2.

[0137] Another embodiment of the present invention discloses another chip testing device. Figure 7 Based on the corresponding embodiment, the quantity statistics module 72 specifically includes:

[0138] The first statistical unit: continuously determines whether the level information corresponding to the first bit to the last bit of the test signal in N signal cycles is a high level or a low level; if the first bit is a high level, transfer to the second statistical unit for operation; if the first bit is a low level, transfer to the fourth statistical unit for operation.

[0139] Second statistical unit: When the current bit is at a high level, continue to determine whether each subsequent bit is at a high level. When a subsequent bit is at a high level, the number of consecutive high levels increases by 1. When the subsequent bit is at a low level, switch to the third statistical unit for operation. If there is no subsequent bit, end.

[0140] The third statistical unit: determines whether the current number of consecutive high levels after being increased by 1 one or more times is greater than the first number threshold, if so, updates the first number threshold to the current number of consecutive high levels, sets the current number of consecutive low levels to 1, and transfers to the fourth statistical unit for operation, wherein the first number threshold is initially 1.

[0141] Fourth statistical unit: When the current bit is at a low level, continue to determine whether each subsequent bit is at a low level. When a subsequent bit is at a low level, the number of consecutive low levels increases by 1 until the subsequent bit is at a high level, and then switch to the fifth statistical unit for operation. If there is no subsequent bit, end.

[0142] The fifth statistical unit: determines whether the current number of consecutive low levels after increasing by 1 one or more times is greater than the second number threshold; if so, updates the second number threshold to the current number of consecutive low levels, sets the current number of consecutive high levels to 1, and transfers to the second statistical unit for operation, wherein the second number threshold is initially 1.

[0143] The sixth statistical unit: when the level information corresponding to the last bit is determined, the current first quantity threshold is determined as the maximum number of consecutive high levels, and the current second quantity threshold is determined as the maximum number of consecutive low levels.

[0144] Another embodiment of the present invention discloses another chip testing device. Figure 7 Based on the corresponding embodiment, the result calculation module 73 includes:

[0145] A first calculation unit determines a total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0146] The second calculation unit determines the duty cycle of the chip to be tested according to the total number of levels and any one of the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0147] It should be noted that the information interaction, execution process, etc. between the above-mentioned methods, devices, and units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the system embodiment section and will not be repeated here.

[0148] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0149] The present application also provides a terminal device, such as Figure 8 As shown, the terminal device 80 includes: at least one processor 801, a memory 802, and a computer program 803 stored in the memory and executable on the at least one processor, and the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0150] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0151] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0152] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0153] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0154] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0155] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0156] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0157] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A chip testing system, characterized in that: include: A probe station and a tester, wherein the probe station is electrically connected to the tester; The tester obtains level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1; The tester counts the level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels; The tester calculates according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain a duty cycle of the chip to be tested; The tester sends the duty cycle of the chip to be tested to the probe station.

2. The chip testing system according to claim 1, characterized in that: The step of obtaining level information corresponding to each bit of the test signal of the test chip in N signal cycles includes: Based on the capture and storage function, the level information of the chip pin signal is captured to obtain the level information corresponding to each bit of the test signal of the test chip in N signal cycles.

3. The chip testing system according to claim 1, characterized in that: The chip testing system further comprises a probe card arranged on the probe station, and the tester obtains a signal to be tested of the chip to be tested through the probe card.

4. The chip testing system according to claim 1, characterized in that: Said N≤2.

5. The chip testing system according to claim 1, characterized in that: The step of performing quantitative statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels includes: Determine whether level information corresponding to the first bit to the last bit of the signal to be tested in N signal cycles is a high level or a low level; When the current bit is at a high level, continue to determine whether each subsequent bit is at a high level. When a subsequent bit is at a high level, the number of consecutive high levels increases by 1 until the subsequent bit is at a low level. If there is no subsequent bit, the process ends. When the subsequent bit is at a low level, determine whether the current number of consecutive high levels after one or more increases by 1 is greater than a first number threshold, if so, update the first number threshold to the current number of consecutive high levels, set the current number of consecutive low levels to 1, and go to the step of the current bit being at a low level, wherein the first number threshold is initially 1; When the current bit is at a low level, continue to determine whether each subsequent bit is at a low level. When a subsequent bit is at a low level, the number of consecutive low levels increases by 1 until the subsequent bit is at a high level. If there is no subsequent bit, the process ends. When the subsequent bit is at a high level, determine whether the current number of consecutive low levels after one or more increases by 1 is greater than a second number threshold, if greater, update the second number threshold to the current number of consecutive low levels, set the current number of consecutive high levels to 1, and go to the step of the current bit being at a high level, wherein the second number threshold is initially 1; When the level information corresponding to the last bit is determined, the current first quantity threshold is determined as the maximum number of consecutive high levels, and the current second quantity threshold is determined as the maximum number of consecutive low levels.

6. The chip testing system according to claim 1, characterized in that: The step of calculating according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested includes: Determine the total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels; The duty cycle of the chip to be tested is determined according to the total number of levels and any one of the maximum number of consecutive high levels and the maximum number of consecutive low levels.

7. A chip testing method, characterized in that: include: Obtaining level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1; Performing quantitative statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels; The duty cycle of the chip to be tested is obtained by performing calculation according to the maximum number of consecutive high levels and the maximum number of consecutive low levels.

8. A chip testing device, characterized in that: include: An information acquisition module, used to obtain level information corresponding to each bit of the test signal of the test chip in N signal cycles, wherein the level information includes a high level and a low level, and N≥1; A quantity statistics module is used to perform quantity statistics on level information corresponding to each bit of the signal to be tested in N signal cycles to determine the maximum number of consecutive high levels and the maximum number of consecutive low levels; The result calculation module is used to calculate according to the maximum number of consecutive high levels and the maximum number of consecutive low levels to obtain the duty cycle of the chip to be tested.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to claim 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to claim 7 is implemented.

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