Verification system and method for PCIe to SATA chip

Abstract

The invention provides a PCIe-to-SATA chip verification system and method. A verification platform sends PCIe transmission excitation to a PCIe host model according to a data transmission driving command; the PCIe host model converts the PCIe downlink data into PCIe downlink data and transmits the PCIe downlink data to the chip to be tested, and the chip to be tested transmits the corresponding SATA downlink data to the SATA equipment model; and the verification platform monitors a first type of data packet received by the SATA equipment model, and determines whether the first type of data packet accords with the protocol specification according to the first type of data packet and a first expected data packet corresponding to the data transmission driving command. According to the PCIe-to-SATA chip verification system provided by the embodiment of the invention, the PCIe host model and the SATA equipment model are efficiently driven to carry out PCIe-to-SATA communication through the to-be-tested chip, the data interaction process is monitored, protocol check is carried out, and verification convergence of the chip is accelerated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a PCIe to SATA chip verification system and method. Background Art

[0002] With the development of computer systems and the increase in data demand, interface technologies such as high-speed serial computer expansion bus standards (Peripheral Component Interconnect express, referred to as PCIe) and serial hard disk (Serial ATA, referred to as SATA) play an important role in data storage and transmission. The PCIe interface provides the advantages of high bandwidth and low latency, while the SATA interface is widely used to connect storage devices such as hard disk drives and optical disk drives.

[0003] The PCIe to SATA chip can realize the conversion between the PCIe protocol and the SATA protocol. It has many application scenarios in the field of computers and data storage, mainly for connecting high-speed storage devices (such as solid-state drives) with SATA interfaces to motherboards or systems that support PCIe interfaces. The stability of the performance of the PCIe to SATA chip is very important for the stable operation of the host device. Therefore, the verification of the PCIe to SATA chip is very important. However, since the PCIe to SATA chip involves the protocols of two high-speed interfaces, PCIe and SATA, and the two need to cooperate with each other, the process is very complicated. This also brings huge challenges to the verification of the PCIe to SATA chip, which has become a difficult problem that technicians in this field are concerned about. Summary of the invention

[0004] The object of the present invention is to provide a PCIe to SATA chip verification system and method to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a PCIe to SATA chip verification system, the verification system comprising a PCIe to SATA chip verification platform, a PCIe host model, and a SATA device model; In the protocol verification stage in the downstream direction, the verification platform is used to send a PCIe transmission stimulus to the PCIe host model according to a data transmission drive command, and configure the SATA device model according to a response rule corresponding to the data transmission drive command; The PCIe host model is used to convert the PCIe transmission stimulus into PCIe downstream data, and transmit the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip; The verification platform is used to monitor the first type of data packets received by the SATA device model, and determine whether the PCIe to SATA behavior of the chip under test complies with the protocol specification based on the first type of data packets and the first expected data packets corresponding to the data transmission drive command.

[0006] Optionally, in the protocol verification phase in the upstream direction, the SATA device model is further used to transmit SATA upstream data to the chip under test, so that the chip under test converts the SATA upstream data into PCIe upstream data, and transmits the PCIe upstream data to the PCIe host model; The verification platform is used to monitor the second type of data packets received by the PCIe host model, and determine whether the SATA to PCIe behavior of the chip under test complies with the protocol specification based on the second type of data packets and the second expected data packets corresponding to the SATA upstream data sent by the SATA device model.

[0007] Optionally, the chip to be tested includes a PCIe device and a SATA host, the PCIe device and the SATA host are connected via an AXI bus, the PCIe device is connected to the PCIe host model, and the SATA host is connected to the SATA device model; The verification platform includes a performance statistics module and an AXI verification component; In the protocol verification phase in the downlink direction, the performance statistics module is used to obtain the downlink transmission time and the amount of valid data bytes in the first type of data packets, and determine the downlink data transmission rate according to the downlink transmission time and the amount of valid data bytes in the first type of data packets; The AXI verification component is used to monitor the AXI bus during the downlink transmission time to determine the downlink bandwidth utilization of the AXI bus; In the protocol verification phase in the uplink direction, the performance statistics module is used to obtain the uplink transmission time and the amount of valid data bytes in the second type of data packets, and determine the uplink data transmission rate according to the uplink transmission time and the amount of valid data bytes in the second type of data packets; The AXI verification component is used to monitor the AXI bus during the uplink transmission time to determine the uplink bandwidth utilization of the AXI bus.

[0008] By acquiring important parameters such as the downlink data transmission rate, downlink bandwidth utilization, uplink data transmission rate, and uplink bandwidth utilization of the chip to be tested, the performance characteristics of the chip can be evaluated before tape-out, avoiding the additional cost of chip iteration caused by functional or performance defects after tape-out, and helping to quickly locate test problems in the chip after tape-out, thereby accelerating the testing progress.

[0009] In a second aspect, an embodiment of the present invention provides a PCIe to SATA chip verification method, which is applied to the above-mentioned verification system. The PCIe to SATA chip verification method includes: In the protocol verification phase in the downstream direction, the verification platform sends a PCIe transmission stimulus to the PCIe host model according to the data transmission drive command, and configures the SATA device model according to the response rule corresponding to the data transmission drive command; The PCIe host model converts the PCIe transmission stimulus into PCIe downstream data, and transmits the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip; The verification platform monitors the first type of data packets received by the SATA device model, and determines whether the PCIe-to-SATA behavior of the chip under test complies with the protocol specification based on the first type of data packets and a first expected data packet corresponding to the data transmission drive command.

[0010] In a third aspect, an embodiment of the present invention provides a PCIe to SATA chip verification method, which is applied to a verification platform in the above-mentioned verification system. The PCIe to SATA chip verification method includes: In the protocol verification stage in the downstream direction, a PCIe transmission stimulus is sent to the PCIe host model according to a data transmission drive command, and the SATA device model is configured according to a response rule corresponding to the data transmission drive command; so that the PCIe host model converts the PCIe transmission stimulus into PCIe downstream data, and transmits the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip; The first type of data packet received by the SATA device model is monitored, and according to the first type of data packet and a first expected data packet corresponding to the data transmission drive command, it is determined whether the PCIe to SATA behavior of the chip under test complies with the protocol specification.

[0011] Compared with the prior art, the PCIe to SATA chip verification system and method provided in the embodiment of the present invention no longer separately verify that the PCIe or SATA function complies with the protocol specification. The PCIe to SATA chip verification system efficiently drives the PCIe host model and the SATA device model to perform PCIe to SATA communication through the chip to be tested, simulates and tests the data interaction of the PCIe and SATA interfaces, verifies whether the data transmission and control logic processing comply with the specifications and design requirements, monitors the data interaction process and performs protocol checks, which helps to quickly locate test problems in the chip after tape-out, speed up the test progress, and accelerate the verification convergence of the chip.

[0012] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 A schematic diagram of modules of a verification system provided by an embodiment of the present invention.

[0015] Figure 2 A schematic diagram of modules of a verification platform 10 provided in an embodiment of the present invention.

[0016] Figure 3 One of the flow charts of the PCIe to SATA chip verification method provided by the embodiment of the present invention.

[0017] Figure 4 A second flow chart of a method for verifying a PCIe to SATA chip provided in an embodiment of the present invention.

[0018] In the figure: 10-verification platform; 11-PCIe verification component; 12-SATA verification component; 13-SATA protocol check module; 14-PCIe protocol check module; 15-AXI verification component; 16-performance statistics module; 17-parameter configuration module; 20-PCIe host model; 30-SATA device model; 40-chip under test; 41-PCIe device; 42-SATA host; 111-PCIe driver module; 112-PCIe configuration module; 113-PCIe stimulus generator; 114-PCIe monitoring module; 121-SATA driver module; 122-SATA configuration module; 123-SATA stimulus generator; 124-SATA monitoring module. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0022] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0023] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0025] When verifying a PCIe-to-SATA chip, on the one hand, it is necessary to ensure that the PCIe and SATA designs in the PCIe-to-SATA chip comply with their respective protocol specifications. On the other hand, it is necessary to complete the monitoring and inspection of the drive incentives, data interaction, and control logic of the two. A separate verification platform for PCIe or SATA can only verify that their respective functions comply with the protocol specifications, and it is difficult to ensure the functional correctness and performance of the overall design of the PCIe-to-SATA chip.

[0026] In order to solve the above-mentioned problems faced in the process of verifying the PCIe to SATA chip, an embodiment of the present invention provides a verification system for a PCIe to SATA chip, specifically, but not limited to, a verification system for a PCIe to SATA chip based on UVM. Universal Verification Methodology (UVM) is a standard methodology for chip verification. UVM is based on the SystemVerilog language and utilizes the classes, objects and other features in SystemVerilog, as well as some other advanced verification functions.

[0027] The verification platform built by UVM can efficiently drive the PCIe to SATA chip, simulate and test the data interaction between the PCIe and SATA interfaces, and verify whether the data transmission and control logic processing meet the specifications and design requirements. In addition to functional verification, the performance characteristics of the chip can be evaluated before tape-out, avoiding the additional cost of chip iteration caused by functional or performance defects after tape-out, and helping to quickly locate test problems in the chip after tape-out, thereby accelerating the testing progress.

[0028] Specifically, please refer to Figure 1 , Figure 1 The module diagram of the verification system provided by the embodiment of the present invention is as follows: The verification system includes a verification platform 10 for PCIe to SATA chip, a PCIe host model 20 and a SATA device model 30.

[0029] In the protocol verification stage in the downstream direction, the verification platform 10 is used to send a PCIe transmission stimulus to the PCIe host model 20 according to the data transmission drive command, and configure the SATA device model 30 according to the response rule corresponding to the data transmission drive command.

[0030] The data transmission drive command may be any one of the pre-configured standard transmission drivers, which is stored in the parameter configuration module described below. Alternatively, the data transmission drive command may also be carried by the test case.

[0031] The PCIe host model 20 is used to convert PCIe transmission excitation into PCIe downstream data, and transmit the PCIe downstream data to the chip under test 40, so that the chip under test 40 converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model 30, wherein the chip under test 40 is a PCIe to SATA chip.

[0032] Among them, the chip to be tested 40 can be a PCIe to SATA chip to be tested, the PCIe host model 20 communicates with the chip to be tested 40 through PCIe, and provides a physical layer interface on the host side (RC side); the SATA device model 30 communicates with the chip to be tested 40 through SATA, and provides a physical layer interface on the device side. The PCIe host model 20 and the SATA device model 30 can be simulation models implemented by Verilog or Systerm Verilog code, which are used to simulate the actual PCIe and SATA protocol behaviors, communicate with the chip to be tested 40 through the physical layer interfaces of PCIe and SATA, and complete data transmission. The chip to be tested 40 and the PCIe host model 20 and the SATA device model 30 transmit data through corresponding differential signals.

[0033] The verification platform 10 is used to monitor the first type of data packets received by the SATA device model 30, and determine whether the PCIe to SATA behavior of the chip under test 40 complies with the protocol specification based on the first type of data packets and the first expected data packets corresponding to the data transmission drive command.

[0034] Optionally, the verification platform 10 can monitor the PCIe downstream data packets sent by the PCIe host model. The verification platform 10 performs protocol conversion (PCIe to SATA) based on the PCIe downstream data packets to obtain a first expected data packet, and compares the first expected data packet with the first type of data packet to determine whether the two match. If they match, it is considered to comply with the protocol specifications.

[0035] The PCIe to SATA chip verification system provided by the embodiment of the present invention can efficiently drive the PCIe host model 20 and the SATA device model 30 to perform PCIe to SATA communication through the chip under test 40, monitor the data interaction process and perform protocol checks, thereby accelerating the verification convergence of the chip.

[0036] Optionally, during the protocol verification phase in the upstream direction, the SATA device model 30 is also used to transmit SATA upstream data to the chip under test 40 , so that the chip under test 40 converts the SATA upstream data into PCIe upstream data and transmits the PCIe upstream data to the PCIe host model 20 .

[0037] In an optional implementation, when the SATA device model 30 receives a complete first-class data packet, the protocol verification in the upstream direction is triggered, or the PCIe host model 20 actively sends a data feedback request to the SATA device model 30, and when the SATA device model 30 receives the request, the protocol verification in the upstream direction is triggered. After triggering the protocol verification in the upstream direction, the SATA device model 30 transmits the SATA upstream data to the chip under test 40.

[0038] The verification platform 10 is used to monitor the second type of data packets received by the PCIe host model 20, and determine whether the SATA to PCIe behavior of the chip under test 40 complies with the protocol specification based on the second type of data packets and the second expected data packets corresponding to the SATA upstream data sent by the SATA device model 30.

[0039] Optionally, the verification platform 10 monitors the SATA upstream data packets sent by the SATA device model 30, and the verification platform 10 performs protocol conversion (SATA to PCIe) based on the SATA upstream data packets to obtain a second expected data packet, and compares the second expected data packet with the second type of data packet to determine whether the two match. If they match, it is considered to comply with the protocol specifications.

[0040] Please refer to Figure 2 , Figure 2 Module diagram of the verification platform 10 provided by an embodiment of the present invention. The verification platform 10 is provided with a verification environment layer, in which components for instantiating various verification components are deployed, mainly including any one or more of a PCIe verification component 11, a SATA verification component 12, a SATA protocol check module 13, a PCIe protocol check module 14, an AXI verification component 15, a performance statistics module 16, and a parameter configuration module 17. The test case calls each component through the verification environment layer to complete the generation and sending of the drive stimulus of the chip 40 to be tested.

[0041] Based on the foregoing, an embodiment of the present invention also provides an optional implementation method regarding how the verification platform implements the process of sending PCIe transmission stimuli to the PCIe host model according to the data transmission driver command, and configuring the SATA device model according to the response rules corresponding to the data transmission driver command. Please refer to the following.

[0042] The verification platform 10 includes a PCIe verification component 11 and a SATA verification component 12 .

[0043] In the protocol verification stage in the downstream direction, the SATA verification component 12 is used to generate a SATA transmission stimulus according to a data transmission drive command, and transmit the SATA transmission stimulus to the PCIe verification component 11 .

[0044] The PCIe verification component 11 is used to convert the SATA transmission stimulus into a PCIe transmission stimulus, and send the PCIe transmission stimulus to the PCIe host model 20 .

[0045] The SATA verification component 12 is used to configure the SATA device model 30 according to the response rule corresponding to the data transmission drive command.

[0046] Based on the foregoing, an embodiment of the present invention also provides an optional implementation method regarding how the verification platform monitors the first type of data packet received by the SATA device model, and determines whether the PCIe to SATA behavior of the chip under test complies with the protocol specification based on the first type of data packet and the first expected data packet corresponding to the data transmission drive command. Please refer to the following.

[0047] The verification platform 10 further includes a SATA protocol checking module 13 .

[0048] The SATA verification component 12 is further used to monitor the first type of data packets received by the SATA device model 30 and send the first type of data packets to the SATA protocol checking module 13 .

[0049] The PCIe verification component 11 is used to monitor the PCIe downstream data packets corresponding to the data transmission drive commands sent by the PCIe host model 20, and send the PCIe downstream data packets to the SATA protocol checking module 13.

[0050] The SATA protocol checking module 13 is used to perform PCIe to SATA processing according to PCIe downstream data to obtain a first expected data packet, and determine whether the PCIe to SATA behavior of the chip under test 40 complies with the protocol specification according to the first type of data packet and the first expected data packet.

[0051] Optionally, the SATA protocol checking module 13 compares the first expected data packet with the first type of data packet to determine whether the two match. If they match, it is considered to comply with the protocol specification.

[0052] Based on the foregoing, an embodiment of the present invention also provides an optional implementation method regarding how the verification platform monitors the second type of data packet received by the PCIe host model, and determines whether the SATA to PCIe behavior of the chip under test complies with the protocol specification based on the second type of data packet and the second expected data packet corresponding to the SATA upstream data sent by the SATA device model. Please refer to the following.

[0053] The verification platform 10 further includes a PCIe protocol checking module 14 .

[0054] In the protocol verification phase in the uplink direction, the PCIe verification component 11 is used to monitor the second type of data packets received by the PCIe host model 20 and send the second type of data packets to the PCIe protocol checking module 14 .

[0055] The SATA verification component 12 is used to monitor the SATA upstream data packets sent by the SATA device model 30 , and send the SATA upstream data packets to the PCIe protocol checking module 14 .

[0056] The PCIe protocol checking module 14 is used to perform SATA to PCIe processing according to the SATA uplink data packet to obtain a second expected data packet, and determine whether the SATA to PCIe behavior of the chip under test 40 complies with the protocol specification according to the second type of data packet and the second expected data packet.

[0057] Optionally, the PCIe protocol checking module 14 compares the second expected data packet with the second type of data packet to determine whether the two match. If they match, it is considered to comply with the protocol specification.

[0058] Please continue to refer to Figure 2The PCIe verification component 11 includes a PCIe driver module 111, a PCIe stimulus generator 113 and a PCIe monitoring module 114, and the SATA verification component 12 includes a SATA driver module 121, a SATA stimulus generator 123 and a SATA monitoring module 124.

[0059] In the protocol verification stage in the downstream direction, the SATA stimulus generator 123 is used to generate a SATA transmission stimulus according to the data transmission drive command.

[0060] The SATA driver module 121 is used to transmit the SATA transmission stimulus to the PCIe stimulus generator 113 .

[0061] The PCIe stimulus generator 113 is used to convert the SATA transmission stimulus into a PCIe transmission stimulus.

[0062] The PCIe driver module 111 is used to send PCIe transmission stimulus to the PCIe host model 20 .

[0063] The SATA monitoring module 124 is used to monitor the data packets received and sent by the SATA device model 30 during the communication process.

[0064] The PCIe monitoring module 114 is used to monitor the data packets received and sent by the PCIe host model 20 during the communication process.

[0065] The SATA monitoring module 124 can transmit the monitored data packets (first type data packets and SATA upstream data packets) to the SATA protocol checking module 13 , and the PCIe monitoring module 114 can transmit the monitored data packets (second type data packets and PCIe downstream data packets) to the PCIe protocol checking module 14 .

[0066] Based on the above, regarding how the SATA authentication component implements the process of configuring the SATA device model according to the response rules corresponding to the data transmission drive command, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0067] The SATA authentication component 12 further includes a SATA configuration module 122 .

[0068] The SATA driver module 121 is further used to send the configuration instruction corresponding to the response rule stored in the SATA configuration module 122 to the SATA device model 30, so as to configure the SATA device model according to the response rule corresponding to the data transmission drive command.

[0069] Please continue to refer to Figure 2In an optional implementation, the PCIe verification component 11 further includes a PCIe configuration module 112, and the PCIe configuration module 112 includes PCIe training configuration information and PCIe enumeration configuration information.

[0070] After the chip to be tested is initialized, it enters the PCIe side training phase. In the PCIe side training phase, the PCIe driver module 111 is used to send PCIe training configuration information and PCIe enumeration configuration information to the PCIe host model 20 .

[0071] The PCIe host model 20 is used to perform link connection training according to PCIe training configuration information and perform enumeration process according to PCIe enumeration configuration information; The PCIe monitoring module 114 is used to monitor the training status of the PCIe host model 20 to determine whether a data path between the PCIe host model 20 and the PCIe device in the chip under test 40 is successfully established.

[0072] After the data path between the PCIe host model 20 and the PCIe device in the chip under test 40 is successfully established, it indicates that the PCIe side training is completed and the PCIe side training phase ends, and the SATA host initialization phase can be entered. Otherwise, adjustments are made and the training is repeated.

[0073] Please continue to refer to Figure 1 In an optional implementation, the chip under test 40 includes a PCIe device 41 and a SATA host 42, and the PCIe device 41 and the SATA host 42 are connected via an AXI bus, wherein the full name of AXI is Advanced Xtensible Interface.

[0074] During the initialization phase of the SATA host 42, the SATA stimulus generator 123 generates a SATA-side initialization stimulus according to the initialization drive command.

[0075] The initialization driving command is any initialization driving command among pre-configured standard driving commands.

[0076] The SATA driver module 121 is used to transmit the SATA side initialization stimulus to the PCIe stimulus generator 113 .

[0077] The PCIe stimulus generator 113 converts the SATA side initialization stimulus into a PCIe side initialization stimulus.

[0078] The PCIe driver module 111 is used to transmit the PCIe side initialization stimulus to the PCIe host model 20 .

[0079] The PCIe host model 20 transmits the PCIe side initialization stimulus to the PCIe device 41 .

[0080] The PCIe device 41 is used to transmit the PCIe side initialization stimulus to the SATA host 42 to complete the software initialization of the SATA host 42 .

[0081] After completing the software initialization of the SATA host, the SATA side training phase begins.

[0082] The SATA authentication component 12 further includes a SATA configuration module 122 , and the SATA configuration module 122 includes SATA training configuration information.

[0083] In the SATA side training phase, the SATA driver module 121 is used to send SATA training configuration information to the SATA device model 30 .

[0084] The SATA device model 30 is used to perform link connection training according to the SATA training configuration information.

[0085] The SATA monitoring module 124 is used to monitor the training status of the SATA device model 30 to determine whether a data path between the SATA device model 30 and the SATA host 42 in the chip under test 40 is successfully established.

[0086] When the data path between the SATA device model 30 and the SATA host 42 in the chip under test 40 is successfully established, it means that the SATA side training is completed and the SATA side training phase ends. Otherwise, it is necessary to repeat the training after adjustment.

[0087] It should be noted that the negotiation of communication rate is completed during the above training process, including the communication rate between the SATA device model 30 and the SATA host 42 in the chip under test 40 and the communication rate between the PCIe host model 20 and the PCIe device 41 in the chip under test 40.

[0088] Optionally, the chip under test 40 includes a PCIe device 41 and a SATA host 42 , the PCIe device 41 and the SATA host 42 are connected via an AXI bus, the PCIe device 41 is connected to the PCIe host model 20 , and the SATA host 42 is connected to the SATA device model 30 .

[0089] The PCIe device 41 is used to receive PCIe downstream data transmitted by the PCIe host model 20, and send the PCIe downstream data to the SATA host 42 through the AXI bus.

[0090] The SATA host 42 is used to convert the PCIe downstream data into SATA downstream data, and transmit the SATA downstream data to the SATA device model 30 .

[0091] The SATA host 42 is further configured to receive SATA upstream data transmitted by the SATA device model 30 , and send the SATA upstream data to the PCIe device 41 via the AXI bus.

[0092] The PCIe device 41 is used to convert the SATA upstream data into PCIe upstream data, and transmit the PCIe upstream data to the PCIe host model 20 .

[0093] Optionally, the verification platform 10 includes a performance statistics module 16 and an AXI verification component 15 .

[0094] In the protocol verification phase in the downlink direction, the performance statistics module 16 is used to obtain the downlink transmission time and the amount of valid data bytes in the first type of data packets, and determine the downlink data transmission rate based on the downlink transmission time and the amount of valid data bytes in the first type of data packets.

[0095] The downlink transmission time is the time from when the PCIe host model starts sending PCIe downlink data to when the SATA device model completes receiving the first type of data packet.

[0096] The AXI verification component 15 is used to monitor the AXI bus during the downstream transmission time (collect statistics on the bus operation behavior) to determine the downstream bandwidth utilization of the AXI bus.

[0097] In the protocol verification phase in the uplink direction, the performance statistics module 16 is used to obtain the uplink transmission time and the amount of valid data bytes in the second type of data packets, and determine the uplink data transmission rate according to the uplink transmission time and the amount of valid data bytes in the second type of data packets; The upstream transmission time is the time from when the SATA device model starts to send SATA upstream data to when the PCIe host model completes receiving the second type of data packet.

[0098] The AXI verification component 15 is used to monitor the AXI bus during the upstream transmission time (collect statistics on the bus operation behavior) to determine the upstream bandwidth utilization of the AXI bus.

[0099] The verification platform 10 may also compare the downlink data transmission rate, the downlink bandwidth utilization, the uplink data transmission rate, and the uplink bandwidth utilization with corresponding thresholds to determine whether corresponding expectations are met.

[0100] Optionally, when any one of the following is true: the downlink data transmission rate exceeds the downlink transmission standard range; the uplink data transmission rate exceeds the uplink transmission standard range; the downlink bandwidth utilization exceeds the downlink bandwidth standard range; and the uplink bandwidth utilization exceeds the uplink bandwidth standard range, it can be determined that expectations are not met.

[0101] After the verification result is determined, the verification result can also be sent to a user terminal or a printing device for printing. The verification result includes whether the PCIe to SATA behavior of the chip under test complies with the protocol specification, whether the SATA to PCIe behavior of the chip under test complies with the protocol specification, and the above expected results.

[0102] Please continue to refer to Figure 2 The verification platform 10 also includes a parameter configuration module 17, which is used to store protocol configuration parameters, PCIe function parameters and SATA function parameters related to the test case.

[0103] The verification platform 10 is used to complete the initialization of the verification platform 10 according to the protocol configuration parameters and enter the operation stage.

[0104] After entering the operation phase, the verification platform 10 is used to control the chip under test 40 to release the clock and reset.

[0105] The AXI verification component 15 is used to configure the internal registers of the PCIe device 41 in the chip under test according to the PCIe functional parameters, and to configure the internal registers of the SATA host 42 in the chip under test according to the SATA functional parameters, so as to complete the initialization of the chip under test.

[0106] The verification platform provided by the embodiment of the present invention can flexibly construct various application scenarios, such as performance under errors, abnormal scenarios and different load scenarios, is applicable to different scenarios and demand changes, and has high scalability and compatibility. Based on UVM implementation, it is applicable to the UVM verification platform, and has high reusability. For verifying the digital chip of PCIe to SATA, it can effectively improve the verification efficiency, improve the verification quality, and accelerate the verification convergence. Provide comprehensive PCIe / SATA functional verification, performance evaluation and compatibility testing to ensure that the design function correctness of the chip and the PCIe and SATA performance meet expectations. For some special scenarios or abnormal scenarios that cannot meet some provisions of the protocol, the present invention can flexibly construct use cases according to demand, which can be applicable to different scenarios and demand changes. The relevant command conversion of SATA software driver is realized in the verification platform, and the software command is converted into the hardware PCIe interface operation to realize the drive incentive conversion of PCIe to SATA, thereby simulating the behavior of real scenes and enhancing reliability.

[0107] The embodiment of the present invention also provides a PCIe to SATA chip verification method, which is applied to the above-mentioned PCIe to SATA chip verification system. Figure 3 , the verification method of the PCIe to SATA chip includes: S101, S201 and S102, which are specifically described as follows.

[0108] S101, in the protocol verification stage in the downstream direction, the verification platform sends a PCIe transmission stimulus to the PCIe host model according to a data transmission drive command, and configures the SATA device model according to a response rule corresponding to the data transmission drive command.

[0109] S201, the PCIe host model converts the PCIe transmission stimulus into PCIe downstream data, and transmits the PCIe downstream data to the chip under test.

[0110] So that the chip under test converts PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model.

[0111] Among them, the chip to be tested is a PCIe to SATA chip; S102, the verification platform monitors the first type of data packet received by the SATA device model, and determines whether the PCIe to SATA behavior of the chip under test complies with the protocol specification based on the first type of data packet and the first expected data packet corresponding to the data transmission drive command.

[0112] In an optional implementation, the verification method of the PCIe to SATA chip includes: S301 and S103, which are specifically described as follows.

[0113] S301, in the protocol verification phase in the upstream direction, the SATA device model is also used to transmit SATA upstream data to the chip under test.

[0114] The chip under test can convert SATA upstream data into PCIe upstream data and transmit the PCIe upstream data to the PCIe host model.

[0115] S103, the verification platform monitors the second type of data packet received by the PCIe host model, and determines whether the SATA to PCIe behavior of the chip under test complies with the protocol specification based on the second type of data packet and the second expected data packet corresponding to the SATA upstream data sent by the SATA device model.

[0116] The embodiment of the present invention also provides a PCIe to SATA chip verification method, which is applied to the verification platform of the above-mentioned PCIe to SATA chip verification system. Figure 4 ,The verification method of PCIe to SATA chip includes: S1001 and S1002, which are described in detail as follows.

[0117] S1001, in the protocol verification phase in the downstream direction, a PCIe transmission stimulus is sent to a PCIe host model according to a data transmission drive command, and a SATA device model is configured according to a response rule corresponding to the data transmission drive command.

[0118] So that the PCIe host model converts the PCIe transmission stimulus into PCIe downstream data, and transmits the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip.

[0119] S1002, monitoring the first type of data packet received by the SATA device model, and determining whether the PCIe to SATA behavior of the chip under test complies with the protocol specification based on the first type of data packet and a first expected data packet corresponding to the data transmission drive command.

[0120] It should be noted that the PCIe to SATA chip verification method provided in this embodiment can perform the functions and uses shown in the above PCIe to SATA chip verification system embodiment to achieve the corresponding technical effects. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding contents in the above embodiments.

[0121] In summary, an embodiment of the present invention provides a verification system and method for a PCIe to SATA chip, wherein the verification system includes a verification platform for the PCIe to SATA chip, a PCIe host model, and a SATA device model; in the protocol verification stage in the downstream direction, the verification platform is used to send a PCIe transmission stimulus to the PCIe host model according to a data transmission drive command, and configure the SATA device model according to a response rule corresponding to the data transmission drive command; the PCIe host model is used to convert the PCIe transmission stimulus into PCIe downstream data, and transmit the PCIe downstream data to the chip to be tested, so that the chip to be tested converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip to be tested is a PCIe to SATA chip; the verification platform is used to monitor a first type of data packet received by the SATA device model, and determine whether the PCIe to SATA behavior of the chip to be tested complies with the protocol specification based on the first type of data packet and a first expected data packet corresponding to the data transmission drive command. The PCIe to SATA chip verification system provided by the embodiment of the present invention efficiently drives the PCIe host model and the SATA device model to perform PCIe to SATA communication through the chip to be tested, monitors the data interaction process and performs protocol checks, thereby accelerating the verification convergence of the chip.

[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0123] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A PCIe to SATA chip verification system, It is characterized in that The verification system includes a verification platform for PCIe to SATA chips, a PCIe host model, and a SATA device model; In the protocol verification stage in the downstream direction, the verification platform is used to send a PCIe transmission stimulus to the PCIe host model according to a data transmission drive command, and configure the SATA device model according to a response rule corresponding to the data transmission drive command; The PCIe host model is used to convert the PCIe transmission stimulus into PCIe downstream data, and transmit the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip; The verification platform is used to monitor the first type of data packets received by the SATA device model, and determine whether the PCIe to SATA behavior of the chip under test complies with the protocol specification based on the first type of data packets and the first expected data packets corresponding to the data transmission drive command.

2. The PCIe to SATA chip verification system as claimed in claim 1, It is characterized in that In the protocol verification phase in the upstream direction, the SATA device model is also used to transmit SATA upstream data to the chip under test, so that the chip under test converts the SATA upstream data into PCIe upstream data and transmits the PCIe upstream data to the PCIe host model; The verification platform is used to monitor the second type of data packets received by the PCIe host model, and determine whether the SATA to PCIe behavior of the chip under test complies with the protocol specification based on the second type of data packets and the second expected data packets corresponding to the SATA upstream data sent by the SATA device model.

3. The PCIe to SATA chip verification system as claimed in claim 2, It is characterized in that The verification platform includes a PCIe verification component and a SATA verification component; In the protocol verification stage in the downstream direction, the SATA verification component is used to generate a SATA transmission stimulus according to the data transmission drive command, and transmit the SATA transmission stimulus to the PCIe verification component; The PCIe verification component is used to convert the SATA transmission stimulus into the PCIe transmission stimulus, and send the PCIe transmission stimulus to the PCIe host model; The SATA verification component is used to configure the SATA device model according to the response rule corresponding to the data transmission drive command.

4. The PCIe to SATA chip verification system as claimed in claim 3, It is characterized in that The verification platform also includes a SATA protocol checking module; The SATA verification component is also used to monitor the first type of data packets received by the SATA device model, and send the first type of data packets to the SATA protocol checking module; The PCIe verification component is used to monitor the PCIe downstream data packet sent by the PCIe host model and corresponding to the data transmission drive command, and send the PCIe downstream data packet to the SATA protocol inspection module; The SATA protocol checking module is used to perform PCIe-to-SATA processing according to the PCIe downstream data to obtain the first expected data packet, and determine whether the PCIe-to-SATA behavior of the chip under test complies with the protocol specification according to the first type of data packet and the first expected data packet.

5. The PCIe to SATA chip verification system as claimed in claim 4, It is characterized in that The verification platform also includes a PCIe protocol checking module; In the protocol verification phase in the uplink direction, the PCIe verification component is used to monitor the second type of data packets received by the PCIe host model and send the second type of data packets to the PCIe protocol checking module; The SATA verification component is used to monitor the SATA upstream data packets sent by the SATA device model, and send the SATA upstream data packets to the PCIe protocol inspection module; The PCIe protocol checking module is used to perform SATA to PCIe processing according to the SATA uplink data packet to obtain the second expected data packet, and determine whether the SATA to PCIe behavior of the chip under test complies with the protocol specification based on the second type of data packet and the second expected data packet.

6. The PCIe to SATA chip verification system according to any one of claims 3 to 5, It is characterized in that The PCIe verification component includes a PCIe stimulus generator, a PCIe driver module and a PCIe monitoring module, and the SATA verification component includes a SATA stimulus generator, a SATA driver module and a SATA monitoring module; In the protocol verification stage in the downstream direction, the SATA excitation generating device is used to generate a SATA transmission excitation according to the data transmission drive command; The SATA driver module is used to transmit the SATA transmission stimulus to the PCIe stimulus generator; The PCIe incentive generator is used to convert the SATA transmission incentive into the PCIe transmission incentive; The PCIe driver module is used to send the PCIe transmission stimulus to the PCIe host model; The SATA monitoring module is used to monitor the data packets received and sent by the SATA device model during the communication process; The PCIe monitoring module is used to monitor the data packets received and sent by the PCIe host model during the communication process.

7. The PCIe to SATA chip verification system as claimed in claim 6, It is characterized in that The SATA authentication component also includes a SATA configuration module; The SATA driver module is further configured to send the configuration instruction corresponding to the response rule stored in the SATA configuration module to the SATA device model.

8. The PCIe to SATA chip verification system as claimed in claim 6, It is characterized in that The PCIe verification component also includes a PCIe configuration module, and the PCIe configuration module includes PCIe training configuration information and PCIe enumeration configuration information; In the PCIe side training phase, the PCIe driver module is used to send the PCIe training configuration information and the PCIe enumeration configuration information to the PCIe host model; The PCIe host model is used to perform link connection training according to the PCIe training configuration information and perform an enumeration process according to the PCIe enumeration configuration information; The PCIe monitoring module is used to monitor the training status of the PCIe host model and determine whether a data path between the PCIe host model and the PCIe device in the chip to be tested is successfully established.

9. The PCIe to SATA chip verification system as claimed in claim 6, It is characterized in that The chip to be tested includes a PCIe device and a SATA host, and the PCIe device and the SATA host are connected via an AXI bus; In the SATA host initialization phase, the SATA stimulus generator generates a SATA side initialization stimulus according to the initialization drive command; The SATA driver module is used to transmit the SATA side initialization stimulus to the PCIe stimulus generator; The PCIe stimulus generator converts the SATA side initialization stimulus into a PCIe side initialization stimulus; The PCIe driver module is used to transmit the PCIe side initialization stimulus to the PCIe host model; The PCIe host model transmits the PCIe side initialization stimulus to the PCIe device; The PCIe device is used to transmit the PCIe side initialization stimulus to the SATA host to complete the software initialization of the SATA host.

10. The PCIe to SATA chip verification system as claimed in claim 6, It is characterized in that The SATA verification component further includes a SATA configuration module, and the SATA configuration module includes SATA training configuration information; In the SATA side training phase, the SATA driver module is used to send the SATA training configuration information to the SATA device model; The SATA device model is used to perform link connection training according to the SATA training configuration information; The SATA monitoring module is used to monitor the training status of the SATA device model and determine whether a data path between the SATA device model and the SATA host in the chip to be tested is successfully established.

11. The PCIe to SATA chip verification system as claimed in claim 2, It is characterized in that The chip to be tested includes a PCIe device and a SATA host, the PCIe device and the SATA host are connected via an AXI bus, the PCIe device is connected to the PCIe host model, and the SATA host is connected to the SATA device model; The verification platform includes a performance statistics module and an AXI verification component; In the protocol verification phase in the downlink direction, the performance statistics module is used to obtain the downlink transmission time and the amount of valid data bytes in the first type of data packets, and determine the downlink data transmission rate according to the downlink transmission time and the amount of valid data bytes in the first type of data packets; The AXI verification component is used to monitor the AXI bus during the downlink transmission time to determine the downlink bandwidth utilization of the AXI bus; In the protocol verification phase in the uplink direction, the performance statistics module is used to obtain the uplink transmission time and the amount of valid data bytes in the second type of data packets, and determine the uplink data transmission rate according to the uplink transmission time and the amount of valid data bytes in the second type of data packets; The AXI verification component is used to monitor the AXI bus during the uplink transmission time to determine the uplink bandwidth utilization of the AXI bus.

12. The PCIe to SATA chip verification system as claimed in claim 11, It is characterized in that The verification platform also includes a parameter configuration module, which is used to store protocol configuration parameters, PCIe function parameters and SATA function parameters related to the test case; The verification platform is used to complete the verification platform initialization according to the protocol configuration parameters and enter the operation stage; After entering the operation phase, the verification platform is used to control the chip under test to release the clock and reset; The AXI verification component is used to configure the internal registers of the PCIe device in the core to be tested according to the PCIe functional parameters, and to configure the internal registers of the SATA host in the core to be tested according to the SATA functional parameters, so as to complete the initialization of the chip to be tested.

13. A verification method for PCIe to SATA chip, It is characterized in that The verification platform used in the verification system according to any one of claims 1 to 12, wherein the verification method of the PCIe to SATA chip comprises: In the protocol verification stage in the downstream direction, a PCIe transmission stimulus is sent to the PCIe host model according to a data transmission drive command, and the SATA device model is configured according to a response rule corresponding to the data transmission drive command; so that the PCIe host model converts the PCIe transmission stimulus into PCIe downstream data, and transmits the PCIe downstream data to the chip under test, so that the chip under test converts the PCIe downstream data into SATA downstream data, and transmits the SATA downstream data to the SATA device model, wherein the chip under test is a PCIe to SATA chip; The first type of data packet received by the SATA device model is monitored, and according to the first type of data packet and a first expected data packet corresponding to the data transmission drive command, it is determined whether the PCIe to SATA behavior of the chip under test complies with the protocol specification.

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