Chip, device and data processing method

Abstract

The invention discloses a chip, equipment and a data processing method, and belongs to the technical field of semiconductors. The chip comprises an expansion unit, a sorting unit and a cut-off unit which are cascaded in sequence, the expansion unit is used for adding a serial number expansion bit with a preset bit length to the last bit of each piece of input data in m pieces of input data to obtain m pieces of lengthened data; the serial number expansion bit of the previous input data in the m input data is not greater than the serial number expansion bit of the later input data, and m is an integer greater than 1; the sorting unit is used for sorting the m pieces of lengthened data in an ascending order or a descending order according to numerical values to obtain m pieces of output data; and the truncation unit is used for deleting the serial number expansion bit with the preset bit length at the last bit of each piece of output data in the m pieces of output data to obtain m pieces of corrected output data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a device and a data processing method. Background Art

[0002] Data sorting is to organize multiple data into a data sequence from large to small, or from small to large.

[0003] In the scenario of maintaining indexes in a database, there is a need to perform stable sorting on multiple data. Stable sorting means that when the values ​​of two data are the same, in a stable sorted data sequence, the relative order of the two data before and after sorting remains unchanged. In the related art, stable sorting is usually achieved by designing software algorithms.

[0004] How to achieve stable sorting by designing chip structure is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a chip, a device and a data processing method, and the technical solution is as follows:

[0006] According to one aspect of the present application, a chip is provided, the chip comprising: an expansion unit, a sorting unit and a truncation unit cascaded in sequence;

[0007] The extension unit is used to add a sequence number extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data; the sequence number extension bit of the previous input data in the m input data is not greater than the sequence number extension bit of the subsequent input data, and m is an integer greater than 1;

[0008] The sorting unit is used to arrange the m lengthened data in ascending or descending order according to the value to obtain m output data;

[0009] The truncation unit is used to delete the sequence number extension bit of the predetermined bit length from the last bit of each output data in the m output data to obtain the modified m output data.

[0010] According to another aspect of the present application, a data processing method is provided, the method being applied to a chip, the chip comprising: an expansion unit, a sorting unit, and a truncation unit cascaded in sequence;

[0011] The extension unit adds a sequence number extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data; the sequence number extension bit of the previous input data in the m input data is not greater than the sequence number extension bit of the subsequent input data, and m is an integer greater than 1;

[0012] The sorting unit arranges the m lengthened data in ascending or descending order according to the numerical value to obtain m output data;

[0013] The truncation unit deletes the sequence number extension bit of the predetermined bit length at the end of each output data in the m output data to obtain the modified m output data.

[0014] In an optional design of the present application, the sorting unit in the chip is a four-input sorting unit; the value of m is 4;

[0015] The sorting unit arranges the m lengthened data in ascending or descending order according to the numerical value to obtain m output data, including:

[0016] The four-input sorting unit arranges the four lengthened data in ascending or descending order according to the numerical value to obtain four output data.

[0017] In an optional design of the present application, the chip further includes two dual-input comparison units;

[0018] The input end of the expansion unit is connected to the output ends of the two dual-input comparison units respectively, and the two dual-input comparison units are arranged in parallel;

[0019] The method further comprises:

[0020] The ath comparison unit of the two double-input comparison units arranges the bth data and the b+1th data of the four input data according to the numerical values ​​to obtain the bth sequence data and the b+1th sequence data; the value of b is 2*(a-1)+1, and the value of a is 1 or 2;

[0021] The expansion unit adds a sequence number expansion bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data, including:

[0022] The extension unit adds a sequence number extension bit of the predetermined bit length to the last bit of the four sequence data to obtain four lengthened data.

[0023] In an optional design of the present application, the four-input sorting unit in the chip includes three dual-input comparators;

[0024] The first comparator and the second comparator of the three dual-input comparators are arranged in parallel, and the two input terminals of the third comparator of the three dual-input comparators are respectively connected to the second output terminal of the first comparator and the first output terminal of the second comparator;

[0025] The four-input sorting unit arranges the four lengthened data in ascending or descending order according to the numerical value to obtain four output data, including:

[0026] The cth comparator among the three dual-input comparators arranges the two data at the cth position and the c+2th position of the four lengthened data according to the numerical values ​​to obtain the first output data and the second output data of the cth comparator; the value of c is 1 or 2;

[0027] The third comparator among the three dual-input comparators arranges the second output data of the first comparator and the first output data of the second comparator according to numerical values ​​to obtain the first output data and the second output data of the third comparator;

[0028] The four output data include: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator.

[0029] In an optional design of the present application, the sorting unit includes five dual-input comparators; the first comparator and the second comparator of the five dual-input comparators are arranged in parallel, and the third comparator and the fourth comparator of the five dual-input comparators are arranged in parallel; the two input ends of the fifth comparator of the five dual-input comparators are respectively connected to the second output end of the third comparator and the first output end of the fourth comparator;

[0030] The four-input sorting unit arranges the four lengthened data in ascending or descending order according to the numerical value to obtain four output data, including:

[0031] The xth comparator among the five dual-input comparators arranges the two data at the yth position and the y+1th position of the four lengthened data according to the numerical value to obtain the yth sequence data and the y+1th sequence data; the value of y is 2*(x-1)+1, and the value of x is 1 or 2;

[0032] The zth comparator among the five dual-input comparators arranges the wth sequence data and the w+2th sequence data according to the numerical values ​​to obtain the first output data and the second output data of the zth comparator; the value of z is 3 or 4, and the value of w is 2*(z-3)+1;

[0033] The fifth comparator arranges the second output data of the third comparator and the first output data of the fourth comparator according to numerical values ​​to obtain the first output data and the second output data of the fifth comparator;

[0034] The four output data include: the first output data of the third comparator, the first output data and the second output data of the fifth comparator, and the second output data of the fourth comparator.

[0035] According to another aspect of the present application, a computer device is provided, wherein the computer device comprises the chip as described above.

[0036] The beneficial effects of the technical solution provided by this application include at least:

[0037] Through the expansion unit, sequence number extension bits are added to the m input data that need to be sorted, and the original order of the input data is taken into account in the process of sorting based on the value size; a sequence number extension bit of a predetermined bit length is added to the last bit of the input data, ensuring that the original order of the input data will not affect the comparison of the actual size of the data during the sorting process; after m output data are obtained through the sorting unit, the truncation unit deletes the sequence number extension bit of a predetermined bit length at the last bit of the output data, ensuring that the corrected m output data sorted according to the value size are consistent with the original data values ​​of the m input data, and stable sorting of data can be achieved through the structural design in the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a structural block diagram of a chip provided by an exemplary embodiment of the present application;

[0040] Figure 2 is a flow chart of a data processing method provided by an exemplary embodiment of the present application;

[0041] Figure 3 is a flow chart of a data processing method provided by an exemplary embodiment of the present application;

[0042] Figure 4 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0043] Figure 5 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0044] Figure 6 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0045] Figure 7 is a schematic diagram of a comparator provided by an exemplary embodiment of the present application;

[0046] Figure 8 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0047] Fig. 9 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0048] Fig.10 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0049] Fig.11 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0050] Fig.12 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0051] Fig.13 is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application;

[0052] Fig.14 It is a flow chart of a data processing method provided by an exemplary embodiment of the present application.

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0055] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0056] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0057] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the input data and other information involved in this application are obtained with full authorization.

[0058] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0059] Figure 1The structural block diagram of a chip provided by an embodiment of the present application is shown. The chip 100 can be implemented as a system architecture of a data processing method. The chip 100 in this embodiment is a device with data processing capabilities. Exemplarily, the chip 100 includes one or more processing cores, such as a 4-core processor, an 8-core processor, etc., and the chip 100 can be used in electronic devices. The processor can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). Exemplarily, the above-mentioned processor is usually a neural network processor (NPU), but it is not excluded that it can be implemented as at least one of a central processing unit (CPU), an image processor (GPU), etc., or other devices with data processing capabilities, which are not limited by the present application. The chip 100 includes an expansion unit 110, a sorting unit 120, and a truncation unit 130 cascaded in sequence. Exemplarily, the output end of the expansion unit 110 is connected to the input end of the sorting unit 120 , and the output end of the sorting unit 120 is connected to the input end of the truncation unit 130 .

[0060] The expansion unit 110 is a hardware component in the chip 100 for adding a predetermined number of bits of sequence extension bits to the m input data. The expansion unit can be implemented as at least one of a selector, an adder, a shift register, a logic gate circuit, and other hardware components, and the present application does not limit the implementation of the hardware component. The expansion unit 110 is used to obtain data with stable sorting requirements, such as the input end of the expansion unit 110 is connected to a data storage unit or other units with data acquisition capabilities.

[0061] The sorting unit 120 is a computing hardware component in the chip 100 for performing ascending or descending size sorting on the data. The sorting unit 120 can be implemented as a combination of circuit components such as a switching circuit and a multiplexer, which will be introduced below through a separate embodiment. Exemplarily, the input end of the sorting unit 120 is connected to the output end of the expansion unit 110. Exemplarily, the sorting unit 120 performs size sorting on multiple data, and the above-mentioned multiple data can be input from multiple input ends of the sorting unit respectively, or can be input from one input end of the sorting unit in sequence according to the front and back time sequence. The present application does not limit the structure of the sorting unit 120.

[0062] The truncation unit 130 is a hardware component in the chip 100 for deleting a predetermined number of bits of the sequence number extension bit for the data after the size sorting is performed. The truncation unit 130 can be implemented as at least one of the hardware components such as a selector, an adder, a shift register, a logic gate circuit, etc., and the present application does not limit the implementation method of the hardware component. Exemplarily, the input end of the truncation unit 130 is connected to the output end of the sorting unit 120. The truncation unit 130 is used to delete the sequence number extension bit added to the data by the extension unit 110. The truncation unit 130 deletes the sequence number extension bit at the end of the data, shortening the number of bits of the data. The deletion mentioned above can also be referred to as truncation, and the sequence number extension bit at the end of the data is truncated. The data output by the truncation unit 130 is m data arranged in ascending or descending order.

[0063] Figure 2 A flow chart of a data processing method provided by an exemplary embodiment of the present application is shown. The method can be applied to a chip. The method includes:

[0064] Step 210: the extension unit adds a sequence extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data;

[0065] In various embodiments of the present application, the expansion unit, sorting unit and truncation unit in the chip are cascaded in sequence. The expansion unit can process the m input data in parallel or in sequence, and there is no restriction on the processing sequence of the above data.

[0066] Exemplarily, taking one of the m input data as an example, the data is data of a first bit length (e.g., 16 bits), the predetermined bit length added by the expansion unit is data of a second bit length (e.g., 2 bits), and the bit length of the lengthened data is the sum of the first bit length and the second bit length (e.g., 16+2=18 bits).

[0067] Exemplarily, the sequence number extension bit of the previous input data among the m input data is not greater than the sequence number extension bit of the subsequent input data, where m is an integer greater than 1; for example, the sequence number extension bit is the sorting number of the current input data among the m input data, or a value obtained based on the sorting number. Exemplarily, the predetermined bit length of the sequence number extension bit is usually preset, or it can be determined based on the number of input data; Exemplarily, the sequence number extension bits corresponding to different input data have different filling values, for example, the sequence number extension bit is the sorting number of the current input data among the m input data, but it does not exclude the case where the filling values ​​of the sequence number extension bits of multiple input data are the same, which will be introduced through a separate embodiment below.

[0068] Step 220: The sorting unit arranges the m lengthened data in ascending or descending order according to the value to obtain m output data;

[0069] Exemplarily, when the sorting unit arranges the m lengthened data in ascending or descending order according to the numerical value, it is based on the size of the input data and the order of the data in the m input data. Since the sequence number extension bit is at the end of the lengthened data, while ensuring that the size of the input data is correctly sorted, it is also ensured that when the data with the same numerical value appears in the m input data, it is arranged in the order of the m input data, which lays the foundation for stable sorting.

[0070] Exemplarily, the sorting unit arranges the m lengthened data in ascending or descending order according to numerical value, which is usually obtained by performing a sequential transformation on at least two data based on the hardware structure of the sorting unit (such as a switching circuit), which will be introduced separately through an embodiment below.

[0071] Step 230: The truncation unit deletes a sequence number extension bit of a predetermined bit length at the end of each output data in the m output data to obtain the modified m output data;

[0072] Similar to the expansion unit described above, the truncation unit may process the m output data in parallel or sequentially, and the present application does not limit the processing sequence of the data by the truncation unit.

[0073] Exemplarily, the predetermined bit length deleted by the truncation unit at the end of the output data is the bit length of the sequence number. Exemplarily, the predetermined bit length deleted by the truncation unit can be preset or indicated to the truncation unit by the extension unit when adding the sequence number extension bit.

[0074] By using the truncation unit, the sequence number extension bit of the predetermined bit length is deleted at the end of the output data, and the m lengthened data are restored to the values ​​of the m input data, so that the m input data can be arranged in ascending or descending order. It is ensured that when the data with the same value appears in the m input data, they are arranged in the order of the m input data, so that the stable sorting of the data is achieved.

[0075] To summarize, the method provided in this embodiment adds a sequence number extension bit to the m input data that need to be sorted through an expansion unit, and takes into account the original order of the input data in the process of sorting based on the numerical value; adds a sequence number extension bit of a predetermined bit length to the last bit of the input data, ensuring that the original order of the input data will not affect the comparison of the actual size of the data during the sorting process; after obtaining m output data through the sorting unit, the truncation unit deletes the sequence number extension bit of a predetermined bit length at the last bit of the output data, ensuring that the corrected m output data sorted according to the numerical value are consistent with the original data values ​​of the m input data, and stable sorting of the data can be achieved through the structural design in the chip.

[0076] Next, the case where the value of m is 2 to the power of n is introduced, that is, a solution for sorting 2 to the power of n input data is introduced, where n is an integer greater than 1.

[0077] Figure 3 The flowchart of a data processing method provided by an exemplary embodiment of the present application is shown. The method can be applied to a chip. The chip also includes two preprocessing units; each of the two preprocessing units is a preprocessing unit with m / 2 inputs; that is, Figure 2 Based on the embodiment shown, step 202 is also included. Figure 2 Step 210 in can be implemented as step 212:

[0078] Step 202: the ath pre-processing unit of the two pre-processing units arranges the bth data to the b+sth data of the m input data according to the magnitude of the values ​​to obtain the bth sequence data to the b+sth sequence data;

[0079] The input end of the expansion unit is connected to the output ends of the two pre-processing units respectively, and the two pre-processing units are arranged in parallel. The value of b is m / 2*(a-1)+1, the value of s is m / 2, and the value of a is 1 or 2;

[0080] Each preprocessing unit is used to arrange m / 2 input data according to numerical values, the data in the m / 2 input data are adjacent to each other, and each input data is only input to one preprocessing unit.

[0081] In one example, the numerical value arrangement performed by the preprocessing unit is the same as the numerical value arrangement performed by the sorting unit in step 220, that is, both are arranged in ascending order or both are arranged in descending order. The following will introduce the case where the preprocessing unit is implemented as a preprocessing unit with four inputs, eight inputs or a double-input comparison unit through a separate embodiment, but it is not excluded that the preprocessing unit has a larger value.

[0082] Among them, the first preprocessing unit realizes that the first data value and the m / 2th input data among the m input data are arranged according to the numerical size, and m / 2 sequence data are obtained. Similarly, the first preprocessing unit realizes that the m / 2+1th data value and the mth input data among the m input data are arranged according to the numerical size, and m / 2 sequence data are obtained.

[0083] Step 212: the extension unit adds a sequence extension bit of a predetermined bit length to the last bit of the m sequence data to obtain m lengthened data;

[0084] The m sequence data are data that have been partially sorted in advance; the expansion unit does not change the order between the m sequence data, but only adds a sequence number extension bit, so the m lengthened data of the m input sorting units are data that have been partially sorted in advance.

[0085] By pre-sorting the data before the sorting unit, the ability of the preprocessing unit to sort m / 2 can be utilized. The sorting unit only needs to add sequence number extension bits to the partially ordered m sequence data and then perform sorting, which can reduce the complexity of the sorting unit.

[0086] In one example, the data processing of four input data is taken as an example for introduction (that is, the value of m is 4). Figure 3 In the illustrated embodiment, the sorting unit is a four-input sorting unit; Figure 3 Step 220 in can be further implemented as follows:

[0087] The four-input sorting unit arranges the four lengthened data in ascending or descending order according to the numerical value to obtain four output data;

[0088] In this embodiment, the value of m is 4. The sorting unit is implemented as a four-input sorting unit;

[0089] In one example, the four-input sorting unit has four input terminals; four lengthened data are respectively input into the four-input sorting unit at the four input terminals. In another example, the four-input sorting unit has the ability to arrange four data, and the four lengthened data are sequentially input into the four-input sorting unit through one input terminal.

[0090] Next, when the value of m is 4, two preprocessing units are introduced; in an optional implementation, the two preprocessing units are implemented as two dual-input comparison units;

[0091] The ath comparison unit of the two double-input comparison units arranges the bth data and the b+1th data of the four input data according to the numerical values ​​to obtain the bth sequence data and the b+1th sequence data;

[0092] The two dual-input comparison units are arranged in parallel, and the input end of the expansion unit is connected to the output ends of the two dual-input comparison units respectively. The value of b is 2*(a-1)+1, and the value of a is 1 or 2;

[0093] Each dual-input comparison unit is used to arrange two input data according to numerical values. The two input data are adjacent, and each input data is input to only one dual-input comparison unit.

[0094] In one example, the numerical value arrangement performed by the dual-input comparison unit is the same as the numerical value arrangement performed by the sorting unit in step 220 , which is either ascending order or descending order.

[0095] Exemplarily, the dual-input comparison unit determines whether to swap the positions of two data according to the numerical values ​​of the two data to achieve the sorting of the two data, and is also called a compare switch unit (CSU); used to achieve the sorting of the two data, it can also be referred to as CSU2.

[0096] Exemplarily, two ranking data obtained by a dual-input comparison unit are arranged according to numerical size; when the value of a is 1, the first comparison unit arranges the first data and the second data among the four input data according to numerical size to obtain the first ranking data and the second ranking data; when the value of a is 2, the second comparison unit arranges the third data and the fourth data among the four input data according to numerical size to obtain the third ranking data and the fourth ranking data.

[0097] It can be seen that the four sequence data are data that have been partially sorted in advance; the first sequence data and the second sequence data are arranged according to the numerical value, and the third sequence data and the fourth sequence data are arranged according to the numerical value. It can be understood that this embodiment does not make any restrictive provisions on the size of any data in the first array (including the first sequence data and the second sequence data) and any data in the second array (including the third sequence data and the fourth sequence data).

[0098] Exemplarily, the execution sequence of the dual-input comparison unit arranging the data according to the numerical value is before the execution sequence of the expansion unit adding the sequence number extension bit.

[0099] Accordingly, step 210 can be implemented as follows:

[0100] The extension unit adds a sequence extension bit of a predetermined bit length to the last bit of the four sequence data to obtain four lengthened data;

[0101] Exemplarily, the input end of the expansion unit is connected to the output end of the two dual-input comparison units respectively, and the data to which the expansion unit adds the sequence number extension bit is the four sequence data output by the dual-input comparison unit. Since the four sequence data are data that have been partially sorted in advance; the expansion unit does not change the order between the four sequence data, but only adds the sequence number extension bit, so the four lengthened data input to the four-input sorting unit are data that have been partially sorted in advance.

[0102] By pre-sorting the data before the four-input sorting unit, the dual-input comparison unit can be fully utilized to achieve partial sorting of the data. The four-input sorting unit only needs to add sequence number extension bits to the four partially ordered sequence data (such as the first sequence data and the second sequence data are arranged according to numerical size, and the third sequence data and the fourth sequence data are arranged according to numerical size) and then perform sorting, which can reduce the complexity of the four-input sorting unit.

[0103] Further optionally, the four-input sorting unit includes three dual-input comparators; accordingly, the four-input sorting unit arranges the four lengthened data in ascending or descending order according to the numerical value to obtain four output data; which can be implemented as follows:

[0104] The cth comparator among the three dual-input comparators arranges the two data at the cth position and the c+2th position of the four lengthened data according to the numerical value, and obtains the first output data and the second output data of the cth comparator;

[0105] The value of c is 1 or 2; this step introduces the first and second comparators of the three dual-input comparators;

[0106] The first comparator and the second comparator of the three dual-input comparators are arranged in parallel, and the two input terminals of the third comparator of the three dual-input comparators are respectively connected to the second output terminal of the first comparator and the first output terminal of the second comparator;

[0107] The third comparator of the three dual-input comparators arranges the second output data of the first comparator and the first output data of the second comparator according to the numerical values ​​to obtain the first output data and the second output data of the third comparator;

[0108] The four output data include: first output data of the first comparator, first output data and second output data of the third comparator, and second output data of the second comparator.

[0109] It should be noted that the above four output data are arranged in ascending or descending order by sorting the four-input sorting unit (implemented as three dual-input comparators in this embodiment), that is, the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator; a total of four output data are in ascending or descending order from front to back. It is also called that the four output data include from front to back: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator.

[0110] It can be understood that in various embodiments of the present application, the introduction of multiple output data that appear can refer to the explanations in the above text, that is, the multiple output data listed are arranged in ascending or descending order by the sorting unit.

[0111] refer to Figure 4 , Figure 4 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In the figure, four input data (first input data 301 to fourth input data 304) are used as an example for explanation.

[0112] As described above, the chip includes two dual-input comparison units (a first comparison unit 311 and a second comparison unit 312);

[0113] Among them, the first comparison unit 311 arranges the first input data 301 and the second input data 302 among the four input data according to the numerical size, and obtains the first priority data 301a and the second priority data 302a; the second comparison unit 312 arranges the third input data 303 and the fourth input data 304 among the four input data according to the numerical size, and obtains the third priority data 303a and the fourth priority data 304a.

[0114] The expansion unit adds a sequence number expansion bit of a predetermined bit length to the last bit of the four sequence data (the first sequence data 301a to the fourth sequence data 304a) to obtain four lengthened data. In this embodiment, the expansion unit includes four parallel expansion subunits (the first expansion subunit 321 to the fourth expansion subunit 324); taking the first expansion subunit 321 as an example, the first expansion subunit 321 adds a sequence number expansion bit of a predetermined bit length to the last bit of the first sequence data 301a to obtain the first lengthened data 301b.

[0115] In this embodiment, the four-input sorting unit 330 includes three dual-input comparators (first comparator 331 to third comparator 333 ).

[0116] The first comparator 331 arranges the two data at the first position and the third position of the four lengthened data (the first lengthened data 301b and the third lengthened data 303b) according to numerical values ​​to obtain the first output data and the second output data of the first comparator 331.

[0117] The second comparator 332 arranges the two data at the second position and the fourth position of the four lengthened data (the second lengthened data 302b and the fourth lengthened data 304b) according to numerical values ​​to obtain the first output data and the second output data of the second comparator 332.

[0118] The third comparator 333 arranges the second output data of the first comparator 331 and the first output data of the second comparator 332 according to numerical values ​​to obtain the first output data and the second output data of the third comparator 333 .

[0119] Taking the descending order of numerical value as an example, the two data input to the first comparator 331 are the two data with smaller numerical values ​​compared in advance by the two dual-input comparison units, or the data inputted earlier among the data with the same numerical value. The first output data outputted by the first comparator 331 is the data with smaller numerical value among the above two data, or the data inputted earlier among the data with the same numerical value, the minimum value among the four input data, or the data inputted earlier when there are multiple data with the minimum value. Similarly, the second output data outputted by the third comparator 333 is the maximum value among the four input data, or the data with the latter input end when there are multiple data with the maximum value.

[0120] The numerical values ​​of the second output data of the first comparator 331 and the first output data of the second comparator 332 cannot be determined, and need to be input into the third comparator 333 to obtain corresponding output data, thereby determining four output data arranged from small to large.

[0121] The four output data (first output data 301 c to fourth output data 304 c ) include: the first output data of the first comparator 331 , the first output data and the second output data of the third comparator 333 , and the second output data of the second comparator 332 .

[0122] The truncation unit deletes the sequence number extension bits of the predetermined bit length at the end of the four output data (the first output data 301c to the fourth output data 304c) to obtain the four corrected output data (the corrected first output data 301d to the corrected fourth output data 304d). The truncation unit includes four truncation subunits (the first truncation subunit 341 to the fourth truncation subunit 344) connected in parallel; taking the first truncation subunit 341 as an example, the first truncation subunit 341 deletes the sequence number extension bits of the predetermined bit length at the end of the first output data 301c to obtain the corrected first output data 301d.

[0123] To sum up, the method provided in this embodiment can make full use of the dual-input comparison unit to realize partial sorting of data by pre-sorting the data before the four-input sorting unit; the four-input sorting unit includes three dual-input comparators, which can simplify the complexity of the four-input sorting unit on the basis of satisfying the requirement of adding sequence number extension bits to the partially ordered four-sequence data and then performing sorting, and can realize stable sorting of data through the structural design in the chip.

[0124] Next, we will take an example to introduce the ascending order of four data from small to large. Figure 5 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. Figure 4 As can be seen from the introduction, the comparison unit and the comparator both sort the two input data according to the numerical value. This embodiment takes the sorting method of ascending order from small to large as an example for introduction. Figure 5 For simplicity, as introduced above, the dual-input comparison unit and the comparator are referred to as CSU2.

[0125] In this embodiment, the four input data are: 100, 110', 111, 110. Since the data inputted by the second input terminal and the fourth input terminal are both 110, in order to distinguish them, the data inputted by the second input terminal is recorded as 110'.

[0126] A comparison unit sorts the data at the first position and the second position of the four input data in descending order to obtain 100 and 110'; another comparison unit sorts the data at the third position and the fourth position of the four input data in descending order to obtain 110 and 111; the above four data are called four sequence data: 100, 110', 110, 111;

[0127] The extension unit adds a sequence extension bit of a predetermined bit length to the last bit of the four sequence data, and obtains four lengthened data: 1000, 1100', 1101, 1111; wherein the sequence extension bit is the integer part of the quotient of the position of the four sequence data divided by 2; Figure 3 Similarly, the extension unit includes four extension sub-units arranged in parallel, the bit length of the serial number extension bit added by the extension sub-unit is 1, and the extension sub-unit is referred to as ext1.

[0128] For example, the first data 100 among the four sequence data is 1 in the position of the four sequence data, and the first difference is the difference of the first data in the position of the four sequence data minus 1; the first difference is 1-1=0, and the integer part of the quotient of the first difference divided by 2 is 0, which is filled in the serial number extension bit added at the end of the first data 100, and the corresponding lengthened data is 1000.

[0129] Similarly, the second data 110' among the four sequence data is at position 2 of the four sequence data, the first difference is 2-1=1, and the integer part of the quotient of the first difference divided by 2 is 0; the corresponding lengthened data is 1100'. The third data 110 among the four sequence data is at position 3 of the four sequence data, the first difference is 3-1=2, and the integer part of the quotient of the first difference divided by 2 is 1; the corresponding lengthened data is 1101. The fourth data 111 among the four sequence data is at position 4 of the four sequence data, the first difference is 4-1=3, and the integer part of the quotient of the first difference divided by 2 is 1; the corresponding lengthened data is 1111.

[0130] The four extended data are: 1000, 1100', 1101, 1111.

[0131] The first comparator arranges the two data at the first and third positions of the four lengthened data (ie, 1000 and 1101) according to numerical values, and obtains two output data of the first comparator in ascending order (ie, 1000 and 1101).

[0132] The second comparator arranges the two data at the second and fourth positions of the four lengthened data (ie, 1100' and 1111) according to numerical values, and obtains two output data of the second comparator in ascending order (ie, 1100' and 1111).

[0133] The third comparator arranges the second output data of the first comparator (ie 1101) and the first output data of the second comparator (ie 1100') according to numerical values ​​to obtain two output data (1100', 1101) of the third comparator in ascending order.

[0134] As described above, the four output data include: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator, that is, 1000, 1100', 1101, and 1111.

[0135] The truncation unit deletes the sequence number extension bit of the predetermined bit length at the end of the four output data to obtain the four corrected output data: 100, 110', 110, 111. Figure 3 Similarly, the truncation unit includes four truncation sub-units arranged in parallel, the bit length of the sequence number extension bit deleted by the truncation sub-unit is 1, and the extension sub-unit is referred to as trc1.

[0136] It can be seen that the four corrected output data are arranged in ascending order, and the data inputted at the second input terminal and the fourth input terminal are both 110; the data inputted at the second input terminal is recorded as 110', which is before the data inputted at the fourth input terminal, and stable sorting can be achieved.

[0137] In one example of the related art, Figure 6 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. Figure 6 In the process of performing ascending order of four data from small to large, only the two dual-input comparison units and the four-input sorting unit including three dual-input comparators described above are included; there is no expansion unit and truncation unit. Figure 5 For simplicity, as introduced above, the dual-input comparison unit and the comparator are referred to as CSU2.

[0138] In this embodiment, the four input data are: 100, 110', 111, 110. Since the data inputted by the second input terminal and the fourth input terminal are both 110, in order to distinguish them, the data inputted by the second input terminal is recorded as 110'.

[0139] Similar to the two comparison units in the above text, the data at the first position and the second position of the four input data are sorted in descending order, and the data at the third position and the fourth position of the four input data are sorted in descending order; the above four data are called four sequence data: 100, 110', 110, 111;

[0140] The first comparator arranges the two data at the first and third positions of the four lengthened data (ie, 100 and 110) according to numerical values, and obtains two output data of the first comparator in ascending order (ie, 100 and 110).

[0141] The second comparator arranges the two data at the second and fourth positions (ie, 110' and 111) of the four lengthened data according to numerical values, and obtains two output data (ie, 110' and 111) of the second comparator in ascending order.

[0142] The third comparator arranges the second output data of the first comparator (i.e. 110) and the first output data of the second comparator (i.e. 110') according to the numerical value. Since the two numerical values ​​are the same, the order of the two data is not swapped, and the two output data of the third comparator (110, 110') are obtained in ascending order.

[0143] As described above, the four output data include: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator. That is, 100, 110, 110', 111. It can be seen that since the original order of the input data is not considered in the sorting process of the four input data; for two input data with the same value, the data input at the second input end is recorded as 110', which is located after the data input at the fourth input end, and stable sorting cannot be achieved.

[0144] Figure 7 A schematic diagram of a comparator provided by an embodiment of the present application is shown.

[0145] The comparator 600 includes: a comparison circuit 605, a first multiplexer 601, and a second multiplexer 602; wherein the comparator 600 has two input terminals. The first input terminal of the comparator 600 is respectively connected to the first input terminal of the comparison circuit 605, the first input terminal of the first multiplexer 601, and the second input terminal of the second multiplexer 602. That is to say, the first data 611 obtained from the first input terminal of the comparator 600 is the data obtained from the first input terminal of the comparison circuit 605, the data obtained from the first input terminal of the first multiplexer 601, and the data obtained from the second input terminal of the second multiplexer 602.

[0146] The second input terminal of the comparator 600 is respectively connected to the second input terminal of the comparison circuit 605, the second input terminal of the first multiplexer 601, and the first input terminal of the second multiplexer 602. In other words, the second data 612 obtained from the second input terminal of the comparator 600 is the data obtained from the second input terminal of the comparison circuit 605, the data obtained from the second input terminal of the first multiplexer 601, and the data obtained from the first input terminal of the second multiplexer 602.

[0147] In order to better distinguish the hardware components for inputting the first data 611 and the second data 612, Figure 7 In the figure, the data transmission direction of the first data 611 in the hardware component is shown in a dotted line manner, and the data transmission direction of the second data 612 in the hardware component is shown in a solid line manner.

[0148] The comparison circuit 605 outputs a first value (for example, a value of 0) when the data (first data 611) input to the first input terminal of the comparator 600 is less than or equal to the data (second data 612) input to the second input terminal of the comparator 600; and outputs a second value (for example, a value of 1) when the data input to the first input terminal of the comparator 600 is greater than the data input to the first input terminal of the comparator 600;

[0149] The output end of the comparison circuit 605 is connected to the address code port of the first multiplexer 601 and the address code port of the second multiplexer 602 respectively; the address code port indicates the output mode of the multiplexer to which it belongs.

[0150] When the first value is input to the address code port, the first multiplexer 601 outputs the data obtained at the first input terminal of the first multiplexer 601 (i.e., the first data 611); and when the second value is input to the address code port, the first multiplexer 601 outputs the data obtained at the second input terminal of the first multiplexer 601 (i.e., the second data 612).

[0151] When the first value is input to the address code port, the second multiplexer 602 outputs the data obtained at the first input end of the second multiplexer 602 (i.e., the second data 612); and when the second value is input to the address code port, the second multiplexer 602 outputs the data obtained at the second input end of the second multiplexer 602 (i.e., the first data 611).

[0152] The output end of the comparator 600 is connected to the output end of the first multiplexer 601 and the output end of the second multiplexer 602 respectively; the information output by the first multiplexer 601 is the first output data 631; the information output by the second multiplexer 602 is the second output data 632.

[0153] It can be seen that the data output by the comparator 600 is the first data 611 and the second data 612 arranged in ascending order. When the values ​​of the first data 611 and the second data 612 are the same, the order of the first data 611 and the second data 612 remains unchanged.

[0154] It should be noted that Figure 7 The comparator introduced in can be a sorting unit (such as Figure 4 The dual-input comparator in the four-input sorting unit in the expansion unit can also be the other unit before the expansion unit (such as Figure 4 The dual-input comparison unit in any one of the two dual-input comparison units in the present application is not limited to this. The specific structure of the hardware component with two input terminals and the ability to arrange data in ascending order described below can also be implemented as Figure 7 The comparator in . Figure 2The sorting unit in the illustrated embodiment may also be implemented as Figure 7 The comparator introduced in , to achieve stable sorting of two input data.

[0155] In one example, the data processing of eight input data is used as an example for introduction; accordingly, the sorting unit is an eight-input sorting unit; that is, the value of n is 3; the value of m is 8. Accordingly, the eight-input sorting unit sorts the eight lengthened data in ascending or descending order according to the numerical value to obtain eight output data. For the introduction of the sorting unit, please refer to step 220 above, which will not be repeated here one by one.

[0156] Further, correspondingly, in the case where the sorting unit is an eight-input sorting unit, Figure 8 The two preprocessing units shown in the figure are two four-input preprocessing units; the input end of the expansion unit is connected to the output end of the two four-input preprocessing units respectively, and the two four-input preprocessing units are arranged in parallel;

[0157] Step 202 is further implemented as follows: the ath preprocessing unit in the two four-input preprocessing units is used to arrange the bth data to the b+3th data in the eight input data according to numerical size to obtain the bth sequence data to the b+3th sequence data; the value of b is 4*(a-1)+1, and the value of a is 1 or 2.

[0158] Figure 8 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In the figure, eight input data (first input data 301 to eighth input data 308) are used as an example for explanation.

[0159] The first preprocessing unit 401 of the two four-input preprocessing units is used to arrange the first input data 301 to the fourth input data 304 of the eight input data according to the numerical size to obtain the first sequence data to the fourth sequence data; the second preprocessing unit 402 is used to arrange the fifth input data 305 to the eighth input data 308 of the eight input data according to the numerical size to obtain the fifth sequence data to the eighth sequence data.

[0160] It should be noted that Figure 8 A possible structure of a four-input preprocessing unit is shown in FIG. 4 ; taking the first preprocessing unit 401 as an example, the first preprocessing unit 401 includes two dual-input comparison units (CSU2) arranged in parallel. For a specific implementation of CSU2, please refer to Figure 4 For a specific implementation of the four-input comparison unit (CSU4) connected after the two CSU2s in the first preprocessing unit 401, please refer to Figure 4In other words, one of the two four-input preprocessing units is used as Figure 4 The data processing method shown in the figure performs sorting on four input data. Figure 8 In the figure, the output ends of the two four-input preprocessing units are connected to the unit group 412, which is an expansion unit, an eight-input sorting unit, and a truncation unit cascaded in sequence; since the number of data input and output of the unit group is eight, the sorting of the above eight data is realized, and the unit group can be referred to as CSU8.

[0161] In an optional implementation, the sorting unit is an eight-input sorting unit, which is further described as follows. Fig. 9 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In other words, Figure 8 The unit group 412 in the example can be further implemented as: an expansion unit 414, an eight-input sorting unit 415, and a truncation unit 416. For example, Fig. 9 As shown, for the expansion unit 414, the eight-input sorting unit 415, and the truncation unit 416 which are cascaded in sequence; the output end of the expansion unit 414 is connected to the input end of the eight-input sorting unit 415, and the output end of the eight-input sorting unit 415 is connected to the input end of the truncation unit 416.

[0162] The eight-input sorting unit 415 includes two four-input comparators and three two-input comparators;

[0163] The dth four-input comparator of the two four-input comparators arranges the four data at the dth position, d+2th position, d+4th position, and d+6th position of the eight lengthened data according to the numerical value, and obtains the first output data to the fourth output data of the dth four-input comparator; the value of d is 1 or 2;

[0164] refer to Fig. 9 The first four-input comparator 4151 arranges the four data at the 1st, 3rd, 5th and 7th positions of the eight lengthened data output by the sub-unit of the expansion unit 414 according to the numerical value.

[0165] The second four-input comparator 4152 arranges the four data at the 2nd, 4th, 6th and 8th positions of the eight lengthened data output by the sub-unit of the expansion unit 414 according to the numerical values.

[0166] exist Fig. 9 In the example, the extension unit 414 includes eight extension sub-units arranged in parallel, the bit length of the serial number extension bit added by the extension sub-unit is 2, and the extension sub-unit is referred to as ext2.

[0167] It should be noted that the specific implementation of the first four-input comparator 4151 and the second four-input comparator 4152 can refer to Figure 4 A four-input sorting unit in .

[0168] The e-th dual-input comparator among the three dual-input comparators arranges the e+1-th output data of the first four-input comparator and the e-th output data of the second four-input comparator according to the numerical values ​​to obtain the first output data and the second output data of the e-th dual-input comparator; the value of e is 1, 2 or 3;

[0169] refer to Fig. 9 The first two-input comparator 4153 arranges the second output data of the first four-input comparator 4151 and the first output data of the second four-input comparator 4152 according to the numerical value; and so on.

[0170] It should be noted that the specific implementation of the three dual-input comparators can be referred to Figure 7 .

[0171] The eight output data obtained by the eight-input sorting unit 415 include: the first output data of the first four-input comparator 4151, the first output data and the second output data of the first dual-input comparator 4153, the first output data and the second output data of the third dual-input comparator 4155, and the fourth output data of the second four-input comparator 4152; the first four-input comparator 4151 and the second four-input comparator 4152 are arranged in parallel.

[0172] Similar to the expansion unit 414, the truncation unit 416 includes eight truncation subunits arranged in parallel, the bit length of the sequence number extension bit deleted by the truncation subunit is 2, and the truncation subunit is referred to as trc2. The eight truncation subunits delete the sequence number extension bit of the predetermined bit length at the end of each output data in the eight output data to obtain eight corrected output data (corrected first output data 301d to corrected eighth output data 308d).

[0173] To sum up, the method provided in this embodiment adds a sequence extension bit of a predetermined bit length to the last bit of the input data through an expansion unit, thereby ensuring that the original order of the input data will not affect the comparison of the actual size of the data during the sorting process; the sorting unit is an eight-input sorting unit, and the eight-input sorting unit refers to the sorting unit structure when there are four input data, and further realizes the sorting of eight input data on the basis of four input data, avoiding the separate design of the eight-input sorting unit, and realizing stable sorting of data through the structural design in the chip.

[0174] Fig.10A schematic diagram of a data processing method provided by an embodiment of the present application is shown. Fig.10 and Figure 8 Similarly, the data processing of eight input data (the first input data 301 to the eighth input data 308 ) is introduced.

[0175] Fig.10 For the functional description of the first preprocessing unit 401, the second preprocessing unit 402, and the unit group 412, please refer to the above Figure 8 , Fig. 9 , which will not be repeated here one by one; this embodiment introduces the specific circuit implementation method of the above-mentioned units.

[0176] As shown in the figure, the first pre-processing unit 401 can be implemented as five comparators 600. The circuit structure of the comparator 600 is as follows: Figure 7 As shown, it includes a comparison circuit, a first multiplexer, and a second multiplexer; for specific connection methods and function introductions, please refer to the above Figure 7 , I will not repeat them one by one here.

[0177] · For the comparator 600 receiving the first input data 301 and the second input data 302; Figure 7 The circuit configuration is shown in the case:

[0178] If the first input data 301 is less than or equal to the second input data 302 , the first output data 31 a of the comparator 600 is equal to the first input data 301 , and the second output data 32 a of the comparator 600 is equal to the second input data 302 .

[0179] If the first input data 301 is greater than the second input data 302 , the first output data 31 a of the comparator 600 is equal to the second input data 302 , and the second output data 32 a of the comparator 600 is equal to the first input data 301 .

[0180] That is, the first input data 301 and the second input data 302 are sorted in ascending order.

[0181] The comparator 600 receiving the third input data 303 and the fourth input data 304 is similar to the above description and will not be repeated.

[0182] For the extender receiving the first output data 31a, the extender has the ability to add a sequence extension bit with a bit length of 1 to the end of the first output data 31b to obtain the first lengthened data 31b. The extender (extend, also called data extension) can be referred to as ext1. The functions of other extenders in the figure are similar and will not be repeated one by one.

[0183] The specific implementation of the four-input comparison unit (CSU4) in the first pre-processing unit 401 is as follows: Fig.10 The first lengthened data 31b to the fourth lengthened data 34b and the three comparators 600 between the first intermediate data 31c to the fourth intermediate data 34c are similar. The circuit structure of the comparator 600 is as follows: Figure 7 shown.

[0184] For the truncation receiving the first intermediate data 31c, the truncation has the ability to truncate the sequence number extension bit with a bit length of 1 at the end of the first intermediate data 31c to obtain the first sequence data 301a. The truncation (also called data truncation) can be referred to as trc1. The functions of other truncations in the figure are similar and will not be repeated one by one.

[0185] Regarding the second preprocessing unit 402 , the structures of CSU2 and CSU4 in the second preprocessing unit 402 are similar to those of the first preprocessing unit 401 , and are not repeated here.

[0186] As shown in the figure, the unit group 412 can be implemented as an expansion unit 414, an eight-input sorting unit 415, and a truncation unit 416 that are cascaded in sequence; for specific connection methods and function introductions, please refer to the above Fig. 9 , I will not repeat them one by one here.

[0187] For the three dual-input comparators (the first dual-input comparator 4153 to the third dual-input comparator 4155) in the eight-input sorting unit 415, each dual-input comparator can be implemented as follows: Figure 7 The circuit structure shown will not be introduced one by one here.

[0188] For the first four-input comparator 4151 and the second four-input comparator 4152 in the eight-input sorting unit 415, any four-input comparator can be implemented as Figure 4 The four-input sorting unit in the example is implemented as three circuit structures as follows: Figure 7 The comparator shown.

[0189] In another example, the sorting unit is a sixteen-input sorting unit; that is, the value of n is 4; the value of m is 16. Accordingly, the sixteen-input sorting unit sorts the sixteen lengthened data in ascending or descending order according to the numerical value to obtain sixteen output data. For the introduction of the sorting unit, please refer to step 220 above, which will not be repeated here.

[0190] Further, correspondingly, in the case where the sorting unit is a sixteen-input sorting unit, Figure 8The two preprocessing units shown in the figure are two eight-input preprocessing units; the input end of the expansion unit is connected to the output end of the two eight-input preprocessing units respectively, and the two eight-input preprocessing units are arranged in parallel;

[0191] Step 202 is further implemented as follows: the ath preprocessing unit in the two eight-input preprocessing units is used to arrange the bth data to the b+7th data in the sixteen input data according to numerical size to obtain the bth sequence data to the b+7th sequence data; the value of b is 8*(a-1)+1, and the value of a is 1 or 2.

[0192] Fig.11 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In the figure, sixteen input data (the first input data 301 to the sixteenth input data 3016) are used as an example for explanation.

[0193] The first preprocessing unit 451 of the two eight-input preprocessing units is used to arrange the first input data 301 to the eighth input data 308 of the sixteen input data according to numerical size to obtain the first sequence data to the eighth sequence data; the second preprocessing unit 452 is used to arrange the ninth input data 309 to the sixteenth input data 3016 of the sixteen input data according to numerical size to obtain the ninth sequence data to the sixteenth sequence data.

[0194] It should be noted that Fig.11 A possible structure of an eight-input preprocessing unit is shown in FIG. 4 ; taking the first preprocessing unit 451 as an example, the first preprocessing unit 451 includes two dual-input comparison units (CSU2) arranged in parallel. For a specific implementation of CSU2, please refer to Figure 4 For a specific implementation of the four-input comparison unit (CSU4) connected after the two CSU2s in the first preprocessing unit 451, please refer to Figure 4 For the specific implementation of the eight-input comparison unit (CSU8) connected after the two CSU4s in the first preprocessing unit 451, please refer to Figure 8 The unit group in Fig. 9 The expansion unit 414, the eight-input sorting unit 415, and the truncation unit 416 are shown in the figure.

[0195] exist Fig.11 In the figure, the output ends of the two eight-input preprocessing units are connected to the unit group 462, which is an expansion unit, a sixteen-input sorting unit, and a truncation unit cascaded in sequence; since the number of data input and output of the unit group is eight, the sorting of the above sixteen data is realized, and the unit group can be referred to as CSU16.

[0196] In an optional implementation, the sorting unit is a sixteen-input sorting unit, which is further described as follows. Fig.12 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In other words, Fig.11 The unit group 462 in the example can be further implemented as: an expansion unit 464, a sixteen-input sorting unit 465, and a truncation unit 466. For example, Fig.12 As shown, for the expansion unit 464, the sixteen-input sorting unit 465, and the truncation unit 466 which are cascaded in sequence; the output end of the expansion unit 464 is connected to the input end of the sixteen-input sorting unit 465, and the output end of the sixteen-input sorting unit 465 is connected to the input end of the truncation unit 466.

[0197] Among them, the sixteen-input sorting unit includes two eight-input comparators and seven two-input comparators;

[0198] The fth eight-input comparator of the two eight-input comparators is used to arrange eight data from the fth position to the f+14th position of the sixteen lengthened data at intervals of two positions according to numerical values, to obtain the first output data to the eighth output data of the fth eight-input comparator; the value of f is 1 or 2;

[0199] refer to Fig.12 The first eight-input comparator 4651 arranges the eight data at odd positions (the 1st, 3rd, 5th, 7th, ..., 15th positions) of the sixteen lengthened data output by the sub-unit of the expansion unit 464 according to the numerical value.

[0200] The second eight-input comparator 4652 arranges the eight data at the even positions (the 2nd, 4th, 6th, 8th, ..., 16th positions) of the sixteen lengthened data output by the sub-unit of the expansion unit 464 according to the numerical value.

[0201] exist Fig. 9 In the example, the extension unit 464 includes sixteen extension sub-units arranged in parallel, the bit length of the serial number extension bit added by the extension sub-unit is 3, and the extension sub-unit is referred to as ext3.

[0202] It should be noted that the specific implementation of the first eight-input comparator 4651 and the second eight-input comparator 4652 can refer to Fig. 9 The eight-input sorting unit 415 in.

[0203] The g-th dual-input comparator among the seven dual-input comparators is used to arrange the g+1-th output data of the first eight-input comparator and the g-th output data of the second eight-input comparator according to numerical values ​​to obtain the first output data and the second output data of the g-th dual-input comparator; the value of g is a positive integer less than 8;

[0204] refer to Fig.12 The first two-input comparator 4601 arranges the second output data of the first eight-input comparator 4651 and the first output data of the second eight-input comparator 4652 according to numerical values, and so on.

[0205] It should be noted that the specific implementation of the three dual-input comparators can be referred to Figure 7 .

[0206] Among them, the sixteen output data of the sixteen-input sorting unit 465 include: the first output data of the first eight-input comparator 4651, the first output data and the second output data of the first dual-input comparator 4601, to the first output data and the second output data of the seventh dual-input comparator 4607, and the eighth output data of the second eight-input comparator 4652; the first eight-input comparator 4651 and the second eight-input comparator 4652 are arranged in parallel.

[0207] Similar to the expansion unit 464, the truncation unit 466 includes sixteen truncation subunits arranged in parallel, the bit length of the sequence number extension bit deleted by the truncation subunit is 3, and the truncation subunit is referred to as trc3. The sixteen truncation subunits delete the sequence number extension bit of the predetermined bit length at the end of each of the sixteen output data to obtain the sixteen corrected output data (corrected first output data 301d to corrected sixteen output data 3016d).

[0208] To sum up, the method provided in this embodiment adds a sequence number extension bit of a predetermined bit length to the last bit of the input data through an expansion unit, thereby ensuring that the original order of the input data will not affect the comparison of the actual size of the data during the sorting process; the sorting unit is a sixteen-input sorting unit, and the sixteen-input sorting unit refers to the sorting unit structure when there are four input data, and further realizes the sorting of sixteen input data on the basis of four input data, avoiding the separate design of the sixteen-input sorting unit, and realizing stable sorting of data through the structural design in the chip.

[0209] Next, the method of implementing the sorting unit as five dual-input comparators is introduced.

[0210] In this embodiment, the sorting unit is used to arrange the four lengthened data in ascending or descending order according to the value size to obtain four output data;

[0211] The four-input sequencing unit consists of five dual-input comparators; the reference Fig.13 The first comparator 341 and the second comparator 342 of the five dual-input comparators are arranged in parallel, the third comparator 343 and the fourth comparator 344 of the five dual-input comparators are arranged in parallel; the two input ends of the fifth comparator 345 of the five dual-input comparators are respectively connected to the second output end of the third comparator and the first output end of the fourth comparator.

[0212] Accordingly, Figure 2 Step 520 in can be implemented as follows:

[0213] The xth comparator among the five dual-input comparators arranges the two data at the yth position and the y+1th position of the four lengthened data according to the numerical value to obtain the yth sequence data and the y+1th sequence data; the value of y is 2*(x-1)+1, and the value of x is 1 or 2;

[0214] The zth comparator among the five dual-input comparators arranges the wth order data and the w+2th order data according to the numerical value to obtain the first output data and the second output data of the zth comparator; the value of z is 3 or 4, and the value of w is 2*(z-3)+1;

[0215] The fifth comparator arranges the second output data of the third comparator and the first output data of the fourth comparator according to the numerical values ​​to obtain the first output data and the second output data of the fifth comparator;

[0216] The four output data include: the first output data of the third comparator, the first output data and the second output data of the fifth comparator, and the second output data of the fourth comparator.

[0217] refer to Fig.13 , Fig.13 A schematic diagram of a data processing method provided by an embodiment of the present application is shown. In the figure, four input data (first input data 351 to fourth input data 354) are used as an example for explanation.

[0218] The expansion unit adds a sequence number expansion bit of a predetermined bit length to the last bit of the four input data to obtain four lengthened data (the first lengthened data 351a to the fourth lengthened data 354a). In this embodiment, the expansion unit includes four parallel expansion subunits (the first expansion subunit 321 to the fourth expansion subunit 324); taking the first expansion subunit 321 as an example, the first expansion subunit 321 adds a sequence number expansion bit of a predetermined bit length to the last bit of the first input data 351 to obtain the first lengthened data 351a.

[0219] In this embodiment, the four-input sorting unit 340 includes five dual-input comparators. The connection relationship between the five dual-input comparators has been introduced above and will not be repeated.

[0220] The first comparator 341 arranges the two data at the first position and the second position of the four lengthened data (the first lengthened data 351a and the second lengthened data 352a) according to numerical values ​​to obtain the first sequence data 351b and the second sequence data 352b.

[0221] The second comparator 342 arranges the two data at the third and fourth positions of the four lengthened data (the third lengthened data 353a and the fourth lengthened data 354a) according to numerical values ​​to obtain third sequence data 353b and fourth sequence data 354b.

[0222] The third comparator 343 arranges the first sequence data 351 b and the third sequence data 353 b according to numerical values ​​to obtain first output data and second output data of the third comparator 343 .

[0223] The fourth comparator 344 arranges the second sequence data 352 b and the fourth sequence data 354 b according to numerical values ​​to obtain first output data and second output data of the fourth comparator 344 .

[0224] The fifth comparator 345 arranges the second output data of the third comparator 343 and the first output data of the fourth comparator 344 according to the numerical values ​​to obtain the first output data and the second output data of the fifth comparator 345;

[0225] The four output data (first output data 351 c to fourth output data 354 c ) include: the first output data of the third comparator 343 , the first output data and the second output data of the fifth comparator 345 , and the second output data of the fourth comparator 344 .

[0226] The truncation unit deletes the sequence number extension bits of the predetermined bit length at the end of the four output data (the first output data 351c to the fourth output data 354c) to obtain the four corrected output data (the corrected first output data 351d to the corrected fourth output data 354d). The truncation unit includes four truncation subunits (the first truncation subunit 341 to the fourth truncation subunit 344) connected in parallel; taking the first truncation subunit 341 as an example, the first truncation subunit 341 deletes the sequence number extension bits of the predetermined bit length at the end of the first output data 351c to obtain the corrected first output data 351d.

[0227] It should be noted that, in an optional implementation, Figure 8 The specific implementation of the four-input comparison unit (CSU4) introduced in this paper is based on the reference Fig.13 The hardware structure shown in FIG. 1 is used to sort four input data. This application does not limit this. Similarly, Fig. 9 The specific implementation of the first four-input comparator 4151 and the second four-input comparator 4152 can be referred to Fig.13 In an optional implementation, the four-input sorting unit in Figure 4 The four-input sorting unit 330 in is replaced by Fig.13 The four-input sorting unit 340 in FIG.

[0228] To sum up, the method provided in this embodiment, the four-input sorting unit includes five dual-input comparators, which can meet the sorting requirements of four input data in any order, thereby improving the applicability of the four-input sorting unit. The four-input sorting unit takes into account the original order of the input data in the process of sorting based on the numerical size, and can achieve stable sorting of data through the structural design in the chip.

[0229] The above embodiments introduce data processing methods for four, eight, and sixteen input data to achieve stable sorting of the input data. It is understandable that the number of input data (the value of m) is not limited to the above values.

[0230] When m is an integer power of 2, refer to Figure 8 In the illustrated embodiment, the value of m is 2 to the power of n, which achieves stable sorting of input data.

[0231] When the value of m is not equal to an integer power of 2, stable sorting of data can be achieved by inputting placeholders.

[0232] Take three input data as an example. For three input data, the value of m is 3, which is not equal to the positive power of 2. By adding a placeholder input data, the total number of data is four.

[0233] The value and position of the placeholder input data are obtained according to the sorting method of the sorting unit. For example, when the sorting unit sorts the lengthened data in ascending order according to the numerical arrangement method from small to large, the placeholder input data is arranged at the head of the queue of m input data, and the value of the placeholder input data is the minimum value under the bit length of the input data.

[0234] The placeholder input data and three input data are used as four input data, and the expansion unit, sorting unit, and truncation unit in the chip perform data processing on the above four data (refer to Figure 4Or Figure B), get the four corrected output data. Delete the first data in the above four corrected output data, and the remaining three corrected output data are the ascending queues of the three input data, and the ascending queues conform to the stable sorting method.

[0235] When the sorting unit sorts the lengthened data in descending order from large to small according to the numerical arrangement, the placeholder input data is arranged at the end of the queue of m input data, and the value of the placeholder input data is the maximum value under the bit length of the input data.

[0236] To summarize, the method provided in this embodiment, when the value of m is not equal to an integer power of 2, achieves stable sorting of the m input data by implementing the sorting unit as a sorting unit with an integer power of 2 input ends, and adding placeholder input data at the head or tail of the queue of m input data; the sorting unit with an integer power of 2 input ends is fully utilized, and there is no need to design corresponding sorting units for m different values, thereby improving the applicability of the data processing method and the chip to which the data processing method is applied.

[0237] Fig.14 FIG. 1 is a flow chart showing a data processing method provided by an exemplary embodiment of the present application. The method can be applied to a chip. Figure 2 In the illustrated embodiment, step 210 may be implemented as step 210a, and step 230 may be implemented as step 230a:

[0238] Step 210a: the kth extension subunit among the m extension subunits adds a sequence extension bit of a predetermined bit length to the last bit of the kth input data among the m input data to obtain the lengthened kth data;

[0239] The expansion unit includes m expansion sub-units arranged in parallel; k is a positive integer not exceeding m. Figure 4 , Fig. 9 , Fig.12 , Fig.13 The embodiment shows an implementation in which the expansion unit includes 4, 8, or 16 expansion subunits arranged in parallel; illustratively, the kth expansion subunit is connected to the kth input terminal of the sorting unit.

[0240] Furthermore, the sequence number extension bit is introduced as follows.

[0241] refer to Figure 2In the introduction, the sequence number extension bit of the previous input data among the m input data is not greater than the sequence number extension bit of the subsequent input data. In one example, the sequence number extension bit of the k-th input data is used to indicate the sorting sequence number of the input data among the m input data; for example, the value of the sequence number extension bit is also k. In another example, the value of the sequence number extension bit is the k-th quotient value, also known as the k-th extension subunit filling the k-th quotient value in the sequence number extension bit of the k-th input data;

[0242] The kth quotient is the integer part of the quotient of the first difference divided by the first divisor, the value of the first difference is k-1, and the first divisor is a positive integer. Exemplarily, the value of the first divisor can be preset, such as 2. The first divisor can also be determined according to the number of comparators arranged in parallel in the sorting unit. The number of input terminals of the comparator is m / 2. The sorting unit is specifically implemented as a four-input sorting unit. The comparators arranged in parallel in the four-input sorting unit are the first comparator and the second comparator, and the number is 2. The value of the first divisor is 2. Reference Fig. 9 The sorting unit is specifically implemented as an eight-input sorting unit. The comparators arranged in parallel in the eight-input sorting unit are the first four-input comparator and the second four-input comparator. The number is 2, and the value of the first divisor is 2.

[0243] Exemplarily, taking four input data as an example, referring to the above description, when the sorting sequence number of the current input data in the m input data is determined as the value of the sequence number extension bit, the sequence number extension bit needs four different values ​​to distinguish the four input data, and the corresponding bit number is 2 bits;

[0244] When the kth quotient value is determined as the value of the sequence number extension bit, the number of bits corresponding to the sequence number extension bit is 1

[0245] It can be seen that determining the value of the sequence number extension bit as the kth quotient value can save the number of bits of the sequence number extension bit, add fewer bit values ​​to the input data, and save storage space for storing and / or transmitting the lengthened data between various units of the chip, compared to the sorting number of the current data among the m input data.

[0246] Furthermore, the method for determining the sequence number extension bit is determined according to the number of bits of the input data and the amount of input data.

[0247] For example, the number of bits of the input data is the first digit, and there are m input data. When the sequence number extension bit is the sorting number of the current input data among the m input data, the number of bits of the sequence number extension bit is m1, and the value of m1 is m / 2 rounded up; when the sequence number extension bit is the kth quotient value, the number of bits of the sequence number extension bit is m2, and the value of m2 is m / 4 rounded up;

[0248] In the case where the first sum of the first digit and m2 is a positive integer power of 2 (for example, the input data is 7-bit data and there are 4 input data), the k-th quotient value is determined as the sequence number extension bit of the k-th input data; in the case where the second sum of the first digit and m1 is a positive integer power of 2 (for example, the input data is 6-bit data and there are 4 input data), the sorting number of the k-th input data in the m input data is determined as the sequence number extension bit of the k-th input data;

[0249] As described above, the number of bits of the m lengthened data output by the expansion unit is an integer power of 2 (such as 8 bits, 16 bits, etc.), which is convenient for the chip to process the data according to the entire byte, which is beneficial to improving the efficiency of data processing.

[0250] Furthermore, when the second sum is a positive integer power of 2 and the first sum is not a positive integer power of 2, the sorting number of the kth input data among the m input data is determined as the sequence number extension bit of the kth input data; otherwise, the kth quotient value is determined as the sequence number extension bit of the kth input data.

[0251] When the second sum is a positive integer power of 2 and the first sum is not a positive integer power of 2, the only way to achieve that the number of bits of the m lengthened data output by the expansion unit is an integer power of 2 is by determining the sorting number as the sequence number extension bit, so that the chip can process the data according to the entire byte when executing data processing.

[0252] When the second sum is not a positive integer power of 2, the kth quotient value is determined as the serial number extension bit of the kth input data; the number of bits of the serial number extension bit can be saved, saving storage space for storing and / or transmitting the lengthened data between various units of the chip.

[0253] Step 230a: the kth truncation subunit among the m truncation subunits is used to delete a sequence number extension bit of a predetermined bit length at the end of the kth output data among the m input data to obtain a modified kth output data;

[0254] The truncation unit includes m truncation subunits arranged in parallel; k is a positive integer not exceeding m. Figure 4 , Fig. 9 , Fig.12 , Fig.13 The embodiment shows that the truncation unit includes 4, 8, and 16 expansion subunits arranged in parallel.

[0255] It should be noted that step 210a in this embodiment can be Figure 2Step 220 and step 230 in the embodiment are combined into a new embodiment and implemented separately; similarly, step 230a can be combined with Figure 2 Step 210 and step 220 in the embodiment are combined into a new embodiment and implemented separately; this application does not limit this.

[0256] To summarize, in the method provided in this embodiment, the expansion unit includes m expansion sub-units arranged in parallel, which add sequence number extension bits of a predetermined bit length at the end of the input data in parallel, thereby improving the data processing efficiency when adding sequence number extension bits; the truncation unit includes m truncation sub-units arranged in parallel, which delete sequence number extension bits of a predetermined bit length at the end of the output data in parallel, thereby improving the data processing efficiency when deleting the sequence number extension bits, ensuring that the corrected m output data sorted according to numerical value are consistent with the original data values ​​of the m input data, and can achieve stable sorting of data through the structural design in the chip.

[0257] Those skilled in the art can understand that the above embodiments can be implemented independently, or the above embodiments can be freely combined to form new embodiments to implement the data processing method of the present application.

[0258] In one embodiment of the present application, a chip is provided, the chip comprising: an expansion unit, a sorting unit and a truncation unit cascaded in sequence;

[0259] The extension unit is used to add a sequence number extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data; the sequence number extension bit of the previous input data in the m input data is not greater than the sequence number extension bit of the subsequent input data, and m is an integer greater than 1;

[0260] The sorting unit is used to arrange the m lengthened data in ascending or descending order according to the value to obtain m output data;

[0261] The truncation unit is used to delete the sequence number extension bit of the predetermined bit length from the last bit of each output data in the m output data to obtain the modified m output data.

[0262] In an optional implementation of this embodiment, the sorting unit is an m-input sorting unit; m is 2 to the power of n, and n is a positive integer greater than 1;

[0263] The chip further comprises two preprocessing units; each of the two preprocessing units is a preprocessing unit with m / 2 inputs;

[0264] The input end of the expansion unit is connected to the output ends of the two pre-processing units respectively, and the two pre-processing units are arranged in parallel;

[0265] The ath preprocessing unit of the two preprocessing units is used to arrange the bth data to the b+sth data of the m input data according to the numerical value to obtain the bth sequence data to the b+sth sequence data; the value of b is m / 2*(a-1)+1, the value of s is m / 2, and the value of a is 1 or 2;

[0266] The extension unit is used to add a sequence number extension bit of the predetermined bit length to the last bit of the m sequence data to obtain the m lengthened data.

[0267] In an optional implementation of this embodiment, the sorting unit is a four-input sorting unit;

[0268] The four-input sorting unit is used to arrange the four lengthened data in ascending or descending order according to the numerical value to obtain four output data.

[0269] In an optional implementation of this embodiment, the two pre-processing units are two dual-input comparison units;

[0270] The input end of the expansion unit is connected to the output ends of the two dual-input comparison units respectively, and the two dual-input comparison units are arranged in parallel;

[0271] The ath comparison unit of the two dual-input comparison units is used to arrange the bth data and the b+1th data of the four input data according to the numerical value to obtain the bth sequence data and the b+1th sequence data; the value of b is 2*(a-1)+1, and the value of a is 1 or 2;

[0272] The extension unit is used to add a sequence number extension bit of the predetermined bit length to the last bit of the four sequence data to obtain four lengthened data.

[0273] In an optional implementation of this embodiment, the four-input sorting unit includes three dual-input comparators;

[0274] The first comparator and the second comparator of the three dual-input comparators are arranged in parallel, and the two input terminals of the third comparator of the three dual-input comparators are respectively connected to the second output terminal of the first comparator and the first output terminal of the second comparator;

[0275] The cth comparator among the three dual-input comparators is used to arrange the two data at the cth position and the c+2th position of the four lengthened data according to the numerical value to obtain the first output data and the second output data of the cth comparator; the value of c is 1 or 2;

[0276] The third comparator among the three dual-input comparators is used to arrange the second output data of the first comparator and the first output data of the second comparator according to numerical values ​​to obtain the first output data and the second output data of the third comparator;

[0277] The four output data include: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator.

[0278] In an optional implementation of this embodiment, the sorting unit is an eight-input sorting unit;

[0279] The eight-input sorting unit is used to sort the eight lengthened data in ascending or descending order according to the numerical value to obtain eight output data.

[0280] In an optional implementation of this embodiment, the two preprocessing units are two four-input preprocessing units;

[0281] The input end of the expansion unit is connected to the output ends of the two four-input preprocessing units respectively, and the two four-input preprocessing units are arranged in parallel;

[0282] The ath preprocessing unit of the two four-input preprocessing units is used to arrange the bth data to the b+3th data among the eight input data according to numerical size to obtain the bth sequence data to the b+3th sequence data; the value of b is 4*(a-1)+1, and the value of a is 1 or 2.

[0283] In an optional implementation of this embodiment, the eight-input sorting unit includes two four-input comparators and three dual-input comparators;

[0284] The dth four-input comparator of the two four-input comparators is used to arrange the four data at the dth position, d+2th position, d+4th position, and d+6th position of the eight lengthened data according to numerical values ​​to obtain the first output data to the fourth output data of the dth four-input comparator; the value of d is 1 or 2;

[0285] The e-th dual-input comparator among the three dual-input comparators is used to arrange the e+1-th output data of the first four-input comparator and the e-th output data of the second four-input comparator according to numerical values ​​to obtain the first output data and the second output data of the e-th dual-input comparator; the value of e is 1, 2 or 3;

[0286] Among them, the eight output data include: the first output data of the first four-input comparator, the first output data and the second output data of the first dual-input comparator, the first output data and the second output data of the third dual-input comparator, and the fourth output data of the second four-input comparator; the first four-input comparator and the second four-input comparator are arranged in parallel.

[0287] In an optional implementation of this embodiment, the sorting unit is a sixteen-input sorting unit;

[0288] The sixteen-input sorting unit is used to sort the sixteen lengthened data in ascending or descending order according to the numerical value to obtain sixteen output data.

[0289] In an optional implementation of this embodiment, the two preprocessing units are two eight-input preprocessing units;

[0290] The input end of the expansion unit is connected to the output ends of the two eight-input preprocessing units respectively, and the two eight-input preprocessing units are arranged in parallel;

[0291] The ath preprocessing unit of the two eight-input preprocessing units is used to arrange the bth data to the b+7th data of the sixteen input data according to numerical size to obtain the bth sequence data to the b+7th sequence data; the value of b is 8*(a-1)+1, and the value of a is 1 or 2.

[0292] In an optional implementation of this embodiment, the sixteen-input sorting unit includes two eight-input comparators and seven two-input comparators;

[0293] The fth eight-input comparator of the two eight-input comparators is used to arrange eight data from the fth position to the f+14th position of the sixteen lengthened data at intervals of two positions according to numerical values, to obtain the first output data to the eighth output data of the fth eight-input comparator; the value of f is 1 or 2;

[0294] The g-th dual-input comparator among the seven dual-input comparators is used to arrange the g+1-th output data of the first eight-input comparator and the g-th output data of the second eight-input comparator according to numerical values ​​to obtain the first output data and the second output data of the g-th dual-input comparator; the value of g is a positive integer less than 8;

[0295] Among them, the sixteen output data include: the first output data of the first eight-input comparator, the first output data and the second output data of the first dual-input comparator, to the first output data and the second output data of the seventh dual-input comparator, and the eighth output data of the second eight-input comparator; the first eight-input comparator and the second eight-input comparator are arranged in parallel.

[0296] In an optional implementation of this embodiment, the sorting unit is used to arrange the four lengthened data in ascending or descending order according to the value size to obtain four output data;

[0297] The sorting unit comprises five dual-input comparators; the first comparator and the second comparator of the five dual-input comparators are arranged in parallel, and the third comparator and the fourth comparator of the five dual-input comparators are arranged in parallel; the two input ends of the fifth comparator of the five dual-input comparators are respectively connected to the second output end of the third comparator and the first output end of the fourth comparator;

[0298] The xth comparator among the five dual-input comparators is used to arrange the two data at the yth position and the y+1th position of the four lengthened data according to the numerical value to obtain the yth sequence data and the y+1th sequence data; the value of y is 2*(x-1)+1, and the value of x is 1 or 2;

[0299] The zth comparator among the five dual-input comparators is used to arrange the wth sequence data and the w+2th sequence data according to the numerical values ​​to obtain the first output data and the second output data of the zth comparator; the value of z is 3 or 4, and the value of w is 2*(z-3)+1;

[0300] The fifth comparator is used to arrange the second output data of the third comparator and the first output data of the fourth comparator according to numerical values ​​to obtain the first output data and the second output data of the fifth comparator;

[0301] The four output data include: the first output data of the third comparator, the first output data and the second output data of the fifth comparator, and the second output data of the fourth comparator.

[0302] In an optional implementation of this embodiment, it is characterized in that at least one of the comparators includes: a comparison circuit, a first multiplexer, and a second multiplexer; the comparator is used to arrange in ascending order according to the numerical value;

[0303] The first input end of the comparator is respectively connected to the first input end of the comparison circuit, the first input end of the first multiplexer, and the second input end of the second multiplexer; the second input end of the comparator is respectively connected to the second input end of the comparison circuit, the second input end of the first multiplexer, and the first input end of the second multiplexer; the output end of the comparison circuit is respectively connected to the address code port of the first multiplexer and the address code port of the second multiplexer; the output end of the comparator is respectively connected to the output end of the first multiplexer and the output end of the second multiplexer;

[0304] The comparison circuit is configured to output a first value when the data inputted at the first input terminal of the comparator is less than or equal to the data inputted at the second input terminal of the comparator;

[0305] The comparison circuit is configured to output a second value when the data input to the first input terminal of the comparator is greater than the data input to the first input terminal of the comparator;

[0306] The first multiplexer is used to output data acquired by the first input terminal of the first multiplexer when the address code port inputs a first value; and to output data acquired by the second input terminal of the first multiplexer when the address code port inputs a second value;

[0307] The second multiplexer is used to output data acquired by the first input terminal of the second multiplexer when the first value is input to the address code port; and to output data acquired by the second input terminal of the second multiplexer when the second value is input to the address code port;

[0308] The data outputted from the output end of the comparator is obtained by splicing the data from the output ends of the first multiplexer and the second multiplexer.

[0309] In an optional implementation of this embodiment, the expansion unit includes m expansion sub-units arranged in parallel;

[0310] The kth expansion subunit among the m expansion subunits is used to add a sequence number extension bit of the predetermined bit length to the last bit of the kth input data among the m input data to obtain the lengthened kth data; k is a positive integer not exceeding m.

[0311] In an optional implementation of this embodiment, the k-th extension subunit is used to fill the k-th quotient value in the sequence number extension bit of the k-th input data;

[0312] The kth quotient is the integer part of the quotient of the first difference divided by the first divisor, the value of the first difference is k-1, and the first divisor is a positive integer.

[0313] In an optional implementation of this embodiment, the truncation unit includes m truncation sub-units arranged in parallel;

[0314] The kth truncation subunit among the m truncation subunits is used to delete the sequence number extension bit of the predetermined bit length at the end of the kth output data among the m input data to obtain the corrected kth output data; k is a positive integer not exceeding m.

[0315] In an optional implementation of this embodiment, the chip is a neural network processor.

[0316] One point that needs to be explained is that the chip provided in the above embodiment only uses the division of the above-mentioned devices as an example to implement its functions. In practical applications, the above-mentioned functions can be assigned to different functional devices according to actual needs, that is, the content structure of the device can be divided into different functional devices to complete all or part of the functions described above.

[0317] Regarding the chip in the above-mentioned embodiment, the specific manner in which each device performs operations has been described in detail in the embodiment of the relevant data processing method; the technical effects achieved by each device performing operations are the same as the technical effects in the embodiment of the relevant data processing method, and will not be elaborated here.

[0318] The embodiment of the present application further provides a computer device, wherein the computer device includes the chip described above. Exemplarily, the computer device in this embodiment includes: a processor and a memory, wherein the memory stores a computer program; and the processor is the chip described above.

[0319] In one example, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0320] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store at least one instruction.

[0321] Furthermore, the computer device may be implemented as a terminal or a server, and the computer device may also be referred to as an electronic device.

[0322] Taking the computer device as a server as an example, the server includes a processor and a memory. In some embodiments, the server may also optionally include: an input interface and an output interface. The processor, the memory and the input interface and the output interface may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface and the output interface via a bus, a signal line or a circuit board. The input interface and the output interface may be used to connect at least one peripheral device related to input / output (I / O) to the processor and the memory. In some embodiments, the processor, the memory and the input interface and the output interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory and the input interface and the output interface may be implemented on a separate chip or circuit board, and the embodiments of the present application are not limited to this.

[0323] Taking a computer device as a terminal as an example, the terminal includes a processor and a memory. In some embodiments, the terminal may also optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a touch display screen, a camera assembly, an audio circuit and a power supply.

[0324] Those skilled in the art will appreciate that the structure shown above does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0325] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0326] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0327] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip, characterized in that: The chip comprises: an expansion unit, a sorting unit and a truncation unit which are cascaded in sequence; The extension unit is used to add a sequence number extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data; the sequence number extension bit of the previous input data in the m input data is not greater than the sequence number extension bit of the subsequent input data, and m is an integer greater than 1; The sorting unit is used to arrange the m lengthened data in ascending or descending order according to the value to obtain m output data; The truncation unit is used to delete the sequence number extension bit of the predetermined bit length from the last bit of each output data in the m output data to obtain the modified m output data.

2. The chip according to claim 1, characterized in that: The sorting unit is a sorting unit of m inputs; m is 2 to the power of n, and n is a positive integer greater than 1; The chip further comprises two preprocessing units; each of the two preprocessing units is a preprocessing unit with m / 2 inputs; The input end of the expansion unit is connected to the output ends of the two pre-processing units respectively, and the two pre-processing units are arranged in parallel; The ath preprocessing unit of the two preprocessing units is used to arrange the bth data to the b+sth data of the m input data according to the numerical value to obtain the bth sequence data to the b+sth sequence data; the value of b is m / 2*(a-1)+1, the value of s is m / 2, and the value of a is 1 or 2; The extension unit is used to add a sequence number extension bit of the predetermined bit length to the last bit of the m sequence data to obtain the m lengthened data.

3. The chip according to claim 2, characterized in that: The sorting unit is a four-input sorting unit; The four-input sorting unit is used to arrange the four lengthened data in ascending or descending order according to the numerical value to obtain four output data.

4. The chip according to claim 3, characterized in that: The two pre-processing units are two dual-input comparison units; The input end of the expansion unit is connected to the output ends of the two dual-input comparison units respectively, and the two dual-input comparison units are arranged in parallel; The ath comparison unit of the two dual-input comparison units is used to arrange the bth data and the b+1th data of the four input data according to the numerical value to obtain the bth sequence data and the b+1th sequence data; the value of b is 2*(a-1)+1, and the value of a is 1 or 2; The extension unit is used to add a sequence number extension bit of the predetermined bit length to the last bit of the four sequence data to obtain four lengthened data.

5. The chip according to claim 4, characterized in that: The four-input sorting unit includes three dual-input comparators; The first comparator and the second comparator of the three dual-input comparators are arranged in parallel, and the two input terminals of the third comparator of the three dual-input comparators are respectively connected to the second output terminal of the first comparator and the first output terminal of the second comparator; The cth comparator among the three dual-input comparators is used to arrange the two data at the cth position and the c+2th position of the four lengthened data according to the numerical value to obtain the first output data and the second output data of the cth comparator; the value of c is 1 or 2; The third comparator among the three dual-input comparators is used to arrange the second output data of the first comparator and the first output data of the second comparator according to numerical values ​​to obtain the first output data and the second output data of the third comparator; The four output data include: the first output data of the first comparator, the first output data and the second output data of the third comparator, and the second output data of the second comparator.

6. The chip according to claim 2, characterized in that: The sorting unit is an eight-input sorting unit; The eight-input sorting unit is used to sort the eight lengthened data in ascending or descending order according to the numerical value to obtain eight output data.

7. The chip according to claim 6, characterized in that: The two preprocessing units are two four-input preprocessing units; The input end of the expansion unit is connected to the output ends of the two four-input preprocessing units respectively, and the two four-input preprocessing units are arranged in parallel; The ath preprocessing unit of the two four-input preprocessing units is used to arrange the bth data to the b+3th data among the eight input data according to numerical size to obtain the bth sequence data to the b+3th sequence data; the value of b is 4*(a-1)+1, and the value of a is 1 or 2.

8. The chip according to claim 7, characterized in that: The eight-input sorting unit includes two four-input comparators and three dual-input comparators; The dth four-input comparator of the two four-input comparators is used to arrange the four data at the dth position, d+2th position, d+4th position, and d+6th position of the eight lengthened data according to numerical values ​​to obtain the first output data to the fourth output data of the dth four-input comparator; the value of d is 1 or 2; The e-th dual-input comparator among the three dual-input comparators is used to arrange the e+1-th output data of the first four-input comparator and the e-th output data of the second four-input comparator according to numerical values ​​to obtain the first output data and the second output data of the e-th dual-input comparator; the value of e is 1, 2 or 3; Among them, the eight output data include: the first output data of the first four-input comparator, the first output data and the second output data of the first dual-input comparator, the first output data and the second output data of the third dual-input comparator, and the fourth output data of the second four-input comparator; the first four-input comparator and the second four-input comparator are arranged in parallel.

9. The chip according to claim 2, characterized in that: The sorting unit is a sixteen-input sorting unit; The sixteen-input sorting unit is used to sort the sixteen lengthened data in ascending or descending order according to the numerical value to obtain sixteen output data.

10. The chip according to claim 9, characterized in that: The two pre-processing units are two eight-input pre-processing units; The input end of the expansion unit is connected to the output ends of the two eight-input preprocessing units respectively, and the two eight-input preprocessing units are arranged in parallel; The ath preprocessing unit of the two eight-input preprocessing units is used to arrange the bth data to the b+7th data of the sixteen input data according to numerical size to obtain the bth sequence data to the b+7th sequence data; the value of b is 8*(a-1)+1, and the value of a is 1 or 2.

11. The chip according to claim 10, characterized in that: The sixteen-input sorting unit includes two eight-input comparators and seven two-input comparators; The fth eight-input comparator of the two eight-input comparators is used to arrange eight data from the fth position to the f+14th position of the sixteen lengthened data at intervals of two positions according to numerical values, to obtain the first output data to the eighth output data of the fth eight-input comparator; the value of f is 1 or 2; The g-th dual-input comparator among the seven dual-input comparators is used to arrange the g+1-th output data of the first eight-input comparator and the g-th output data of the second eight-input comparator according to numerical values ​​to obtain the first output data and the second output data of the g-th dual-input comparator; the value of g is a positive integer less than 8; Among them, the sixteen output data include: the first output data of the first eight-input comparator, the first output data and the second output data of the first dual-input comparator, to the first output data and the second output data of the seventh dual-input comparator, and the eighth output data of the second eight-input comparator; the first eight-input comparator and the second eight-input comparator are arranged in parallel.

12. The chip according to claim 1, characterized in that: The sorting unit is used to arrange the four lengthened data in ascending or descending order according to the numerical value to obtain four output data; The sorting unit comprises five dual-input comparators; the first comparator and the second comparator of the five dual-input comparators are arranged in parallel, and the third comparator and the fourth comparator of the five dual-input comparators are arranged in parallel; the two input ends of the fifth comparator of the five dual-input comparators are respectively connected to the second output end of the third comparator and the first output end of the fourth comparator; The xth comparator among the five dual-input comparators is used to arrange the two data at the yth position and the y+1th position of the four lengthened data according to the numerical value to obtain the yth sequence data and the y+1th sequence data; the value of y is 2*(x-1)+1, and the value of x is 1 or 2; The zth comparator among the five dual-input comparators is used to arrange the wth sequence data and the w+2th sequence data according to the numerical values ​​to obtain the first output data and the second output data of the zth comparator; the value of z is 3 or 4, and the value of w is 2*(z-3)+1; The fifth comparator is used to arrange the second output data of the third comparator and the first output data of the fourth comparator according to numerical values ​​to obtain the first output data and the second output data of the fifth comparator; The four output data include: the first output data of the third comparator, the first output data and the second output data of the fifth comparator, and the second output data of the fourth comparator.

13. The chip according to claim 5 or 8 or 11 or 12, characterized in that: At least one of the comparators includes: a comparison circuit, a first multiplexer, and a second multiplexer; the comparator is used to arrange in ascending order according to numerical values; The first input end of the comparator is respectively connected to the first input end of the comparison circuit, the first input end of the first multiplexer, and the second input end of the second multiplexer; the second input end of the comparator is respectively connected to the second input end of the comparison circuit, the second input end of the first multiplexer, and the first input end of the second multiplexer; the output end of the comparison circuit is respectively connected to the address code port of the first multiplexer and the address code port of the second multiplexer; the output end of the comparator is respectively connected to the output end of the first multiplexer and the output end of the second multiplexer; The comparison circuit is configured to output a first value when the data inputted at the first input terminal of the comparator is less than or equal to the data inputted at the second input terminal of the comparator; The comparison circuit is configured to output a second value when the data input to the first input terminal of the comparator is greater than the data input to the first input terminal of the comparator; The first multiplexer is used to output data acquired by the first input terminal of the first multiplexer when the address code port inputs a first value; and to output data acquired by the second input terminal of the first multiplexer when the address code port inputs a second value; The second multiplexer is used to output data acquired by the first input terminal of the second multiplexer when the first value is input to the address code port; and to output data acquired by the second input terminal of the second multiplexer when the second value is input to the address code port; The data outputted from the output end of the comparator is obtained by splicing the data from the output ends of the first multiplexer and the second multiplexer.

14. The chip according to any one of claims 1 to 12, characterized in that: The expansion unit includes m expansion sub-units arranged in parallel; The kth expansion subunit among the m expansion subunits is used to add a sequence number extension bit of the predetermined bit length to the last bit of the kth input data among the m input data to obtain the lengthened kth data; k is a positive integer not exceeding m.

15. The chip according to claim 14, characterized in that: The k-th extension subunit is used to fill the k-th quotient value in the sequence number extension bit of the k-th input data; The kth quotient is the integer part of the quotient of the first difference divided by the first divisor, the value of the first difference is k-1, and the first divisor is a positive integer.

16. The chip according to any one of claims 1 to 12, characterized in that: The truncation unit comprises m truncation sub-units arranged in parallel; The kth truncation subunit among the m truncation subunits is used to delete the sequence number extension bit of the predetermined bit length at the end of the kth output data among the m input data to obtain the corrected kth output data; k is a positive integer not exceeding m.

17. The chip according to any one of claims 1 to 16, characterized in that: The chip is a neural network processor NPU.

18. A computer device, characterized in that: The computer device comprises the chip as claimed in any one of claims 1 to 14.

19. A data processing method, characterized in that: The method is applied to a chip, which comprises: an expansion unit, a sorting unit and a truncation unit which are cascaded in sequence; The extension unit adds a sequence number extension bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data; the sequence number extension bit of the previous input data in the m input data is not greater than the sequence number extension bit of the subsequent input data, and m is an integer greater than 1; The sorting unit arranges the m lengthened data in ascending or descending order according to the numerical value to obtain m output data; The truncation unit deletes the sequence number extension bit of the predetermined bit length at the end of each output data in the m output data to obtain the modified m output data.

20. The method according to claim 19, characterized in that The sorting unit is a sorting unit of m inputs; m is 2 to the power of n, and n is a positive integer greater than 1; The chip further comprises two preprocessing units; each of the two preprocessing units is a preprocessing unit with m / 2 inputs; The input end of the expansion unit is connected to the output ends of the two pre-processing units respectively, and the two pre-processing units are arranged in parallel; The method further comprises: The ath preprocessing unit of the two preprocessing units arranges the bth data to the b+sth data of the m input data according to the numerical value to obtain the bth sequence data to the b+sth sequence data; the value of b is m / 2*(a-1)+1, the value of s is m / 2, and the value of a is 1 or 2; The expansion unit adds a sequence number expansion bit of a predetermined bit length to the last bit of each input data in the m input data to obtain m lengthened data, including: The extension unit is used to add a sequence number extension bit of the predetermined bit length to the last bit of the m sequence data to obtain the m lengthened data.

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