Shifting register unit, display driving circuit and display device

Abstract

The invention provides a shift register unit, a display driving circuit and a display device. In the shift register unit, an input control circuit can control the potential of an input node under the control of a clock signal; and the output control circuit can output a display driving signal to the pixel through the output signal end based on the potential of the input node and a reset control signal so as to drive the pixel to emit light. Therefore, by flexibly setting the clock signal and the reset control signal, the shift register unit outputs the display driving signal matched with the P-type transistor and / or the N-type transistor in the pixel. Moreover, the output control circuit and the input control circuit are sequentially arranged in the first direction and in the direction close to the pixels, the signal lines connected with the output control circuit and the input control circuit are sequentially arranged in the first direction and in the direction close to the pixels, and the signal lines extend in the second direction intersecting with the first direction. Therefore, the narrow frame design of the display device can be facilitated.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a display driving circuit and a display device. Background Art

[0002] Gate driver on array (GOA) technology is a technology that integrates a display driving circuit on a display panel, which can facilitate a narrow frame design of the display panel. Summary of the invention

[0003] Provided are a shift register unit, a display driving circuit and a display device, which can solve the problem that the current display driving circuit has a relatively single driving mode, a poor driving effect, and is not conducive to the narrow frame design of the display device. The technical solution is as follows:

[0004] In one aspect, a shift register unit is provided, the shift register unit comprising:

[0005] An input control circuit is connected to the first clock line, the second clock line, the input signal terminal and the input node respectively, and is used to control the connection and disconnection of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line;

[0006] an output control circuit, connected to the input node, the reset control line and the output signal terminal respectively, and used to control the potential of the output signal terminal based on the potential of the input node and the reset control signal provided by the reset control line, so as to output a display driving signal to the P-type transistor and / or the N-type transistor of each pixel in at least one row of pixels through the output signal terminal, so as to drive the light-emitting element of each pixel to emit light;

[0007] Among them, the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel; the reset control line, the first clock line and the second clock line are arranged in sequence along the first direction and in the direction close to the pixel, and the reset control line, the first clock line and the second clock line all extend along the second direction; the second direction intersects with the first direction.

[0008] Optionally, the shift register unit further includes:

[0009] A drive enhancement circuit connected between the output control circuit and the output signal terminal and used to invert the potential of the signal output by the output control circuit at least once and then output it to the output signal terminal;

[0010] The driving enhancement circuit and at least one of the input control circuit and the output control circuit are arranged in sequence along the second direction.

[0011] Optionally, the shift register unit further includes:

[0012] a latch circuit, connected to the third clock line, the fourth clock line, the input node and the intermediate node respectively, and used to control the on-off of the intermediate node and the input node in response to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line, and output the potential of the intermediate node to the input node after inverting the potential, wherein the intermediate node is a connection node between the drive enhancement circuit and the output control circuit;

[0013] Among them, the latch circuit is located between the drive enhancement circuit and at least one of the input control circuit and the output control circuit; the third clock line and the fourth clock line are located on the side of the reset control line close to the pixel, and the third clock line and the fourth clock line are arranged in sequence along the first direction and along the direction close to the pixel, and the third clock line and the fourth clock line both extend along the second direction.

[0014] Optionally, the input control circuit includes: a first transmission gate; the output control circuit includes: an NOR gate; the latch circuit includes: a first NOT gate and a second transmission gate; the drive enhancement circuit includes: three second NOT gates;

[0015] Wherein, the first transmission gate is connected between the input signal terminal and the input node, and is also connected to the first clock line and the second clock line respectively; the two input terminals of the NOR gate are respectively connected to the input node and the reset control line, and the output terminal of the NOR gate is connected to the intermediate node; the input terminal of the first NOT gate is connected to the intermediate node, the output terminal of the first NOT gate is connected to the input node through the second transmission gate, and the second transmission gate is also connected to the third clock line and the fourth clock line respectively; the three second NOT gates are sequentially connected in series between the intermediate node and the output signal terminal;

[0016] Furthermore, the NOR gate, the first NOR gate and the first second NOR gate are arranged in sequence along the second direction, the first transmission gate, the second transmission gate and the second second NOR gate are arranged in sequence along the second direction, the first second NOR gate to the third second NOR gate are arranged in sequence along the first direction and in a direction close to the pixel, and the sizes of the first second NOR gate to the third second NOR gate increase sequentially.

[0017] Optionally, the NOR gate, the first NOT gate, and each of the second NOT gates are also connected to a first power line and a second power line, respectively, and are used to operate based on a first power signal provided by the first power line and a second power signal provided by the second power line, and the potential of the first power signal is greater than the potential of the second power signal;

[0018] Among them, the first power line and the second power line are at least located on both sides of the reset control line in the first direction, and the first power line and the second power line both extend along the second direction; the width of the first power line and the width of the second power line are both greater than the width of the reset control line; the width of the first power line connected to the third second NOT gate is greater than the width of the first power line connected to other gate circuits, and the width of the second power line connected to the third second NOT gate is greater than the width of the second power line connected to other gate circuits; the other gate circuits include: at least one of the NOR gate, the first NOT gate, the second second NOT gate and the first first NOT gate.

[0019] Optionally, the first transmission gate includes: a first P-type transistor and a first N-type transistor;

[0020] The gate of the first P-type transistor and the gate of the first N-type transistor are connected to the first clock line and the second clock line respectively, the first electrode of the first P-type transistor and the first electrode of the first N-type transistor are both connected to the input signal terminal, and the second electrode of the first P-type transistor and the second electrode of the first N-type transistor are both connected to the input node;

[0021] Furthermore, the first P-type transistor and the first N-type transistor are sequentially arranged along the first direction and in a direction close to the pixel.

[0022] Optionally, the NOR gate includes: a second P-type transistor, a second N-type transistor, a third P-type transistor and a third N-type transistor;

[0023] The gate of the second P-type transistor and the gate of the third N-type transistor are both connected to the reset control line, the first electrode of the second P-type transistor is connected to the first power line, the second electrode of the second P-type transistor is connected to the first electrode of the third P-type transistor, the second electrode of the third P-type transistor, the second electrode of the second N-type transistor and the second electrode of the third N-type transistor are all connected to the intermediate node, the first electrode of the second N-type transistor and the first electrode of the third N-type transistor are both connected to the second power line, and the gate of the third P-type transistor and the gate of the second N-type transistor are both connected to the input node;

[0024] Furthermore, the third P-type transistor and the second P-type transistor are arranged in sequence and connected in series along the second direction and along the direction close to the first NOT gate, the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, the third N-type transistor is located on the side of the third P-type transistor close to the second P-type transistor, and the second N-type transistor and the third N-type transistor are both close to the pixel relative to the third P-type transistor.

[0025] Optionally, the first NOT gate includes: a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a dual-gate transistor; the second transmission gate includes: a fifth P-type transistor and a fifth N-type transistor;

[0026] The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are both connected to the intermediate node, the first electrode of the fourth P-type transistor and the first electrode of the fourth N-type transistor are respectively connected to the first power line and the second power line, the second electrode of the fourth P-type transistor and the second electrode of the fourth N-type transistor are both connected to the first electrode of the fifth P-type transistor and the first electrode of the fifth N-type transistor, the gate of the fifth P-type transistor and the gate of the fifth N-type transistor are respectively connected to the third clock line and the fourth clock line, and the second electrode of the fifth P-type transistor and the second electrode of the fifth N-type transistor are both connected to the input node;

[0027] Furthermore, the fourth P-type transistor and the fourth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the fifth P-type transistor and the fifth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, and the fifth P-type transistor and the fifth N-type transistor are both close to the first transmission gate relative to the fourth P-type transistor and the fourth N-type transistor.

[0028] Optionally, the first second NOT gate includes: a sixth P-type transistor and a sixth N-type transistor; the second second NOT gate includes: a seventh P-type transistor and a seventh N-type transistor; the third second NOT gate includes: an eighth P-type transistor and an eighth N-type transistor;

[0029] The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are both connected to the intermediate node, the gate of the seventh P-type transistor and the gate of the seventh N-type transistor are both connected to the second electrode of the sixth P-type transistor and the second electrode of the sixth N-type transistor, the gate of the eighth P-type transistor and the gate of the eighth N-type transistor are both connected to the second electrode of the seventh P-type transistor and the second electrode of the seventh N-type transistor, the second electrode of the eighth P-type transistor and the second electrode of the eighth N-type transistor are both connected to the output signal terminal, and the first electrode of the sixth P-type transistor, the first electrode of the seventh P-type transistor, and the first electrode of the eighth P-type transistor are all connected to the first power line, and the first electrode of the sixth N-type transistor, the first electrode of the seventh N-type transistor, and the first electrode of the eighth N-type transistor are all connected to the second power line;

[0030] Furthermore, the sixth P-type transistor and the sixth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the seventh P-type transistor and the seventh N-type transistor are arranged in sequence along the second direction and in a direction away from the first transmission gate, and the eighth P-type transistor and the eighth N-type transistor are arranged in sequence along the second direction.

[0031] Optionally, the sizes of transistors in the first second NOT gate to the third second NOT gate increase sequentially;

[0032] Furthermore, sizes of transistors in the first transmission gate, the NOR gate, the first NOT gate, and the second transmission gate are all smaller than sizes of transistors in any of the second NOT gates.

[0033] Optionally, the first clock line, the second clock line, the reset control line, the third clock line and the fourth clock line are all located on the same side of the output control circuit away from the latch circuit, and are arranged at equal intervals in the first direction.

[0034] Optionally, the transistor in the shift register unit comprises: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence;

[0035] The first active layer is used as an active layer of a P-type transistor in the shift register unit, and the second active layer is used as an active layer of an N-type transistor in the shift register unit.

[0036] Optionally, at least part of the first source-drain metal layer is reused with at least one of the first active layer, the first gate metal layer, the second gate metal layer and the second active layer to reduce the overlapping area of ​​the first source-drain metal layer and the second source-drain metal layer.

[0037] In another aspect, a display driving circuit is provided, comprising: at least two cascaded shift register units as described in the above aspect.

[0038] In another aspect, a display device is provided, the display device comprising: a display panel, and the display driving circuit as described in the above another aspect;

[0039] The display panel includes a plurality of pixels. The display driving circuit is connected to the plurality of pixels and is used to transmit light emitting control signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0040] In summary, the beneficial effects brought about by the technical solution provided by the present disclosure may at least include:

[0041] A shift register unit, a display driving circuit and a display device are provided. The shift register unit can output a display driving signal to a pixel through an output signal terminal based on a clock signal and a reset control signal to drive the pixel to emit light. In this way, the clock signal and the reset control signal can be flexibly set so that the shift register unit outputs a signal that matches the P-type transistor and / or the N-type transistor in the pixel. In addition, since the output control circuit and the input control circuit are arranged in sequence along a first direction and in a direction close to the pixel, the signal lines connected to the output control circuit and the input control circuit are arranged in sequence along the first direction and in a direction close to the pixel, and the signal lines all extend in a second direction intersecting the first direction, it can also be beneficial to the narrow frame design of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0044] Figure 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0045] Figure 3is a schematic diagram of the working timing of a pixel circuit provided by an embodiment of the present disclosure;

[0046] Figure 4 is a schematic diagram of the structural layout of a shift register unit provided by an embodiment of the present disclosure;

[0047] Figure 5 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0048] Figure 6 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure;

[0049] Figure 7 is a schematic diagram of a circuit structure layout of a shift register unit provided by an embodiment of the present disclosure;

[0050] Figure 8 is a schematic diagram of the circuit structure of another shift register unit provided by an embodiment of the present disclosure;

[0051] Fig. 9 is a schematic diagram of a circuit layout of a shift register unit provided by an embodiment of the present disclosure;

[0052] Fig.10 It is a schematic diagram of a layout of a portion of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0053] Fig.11 is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0054] Fig.12 is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0055] Fig.13 It is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0056] Fig.14 It is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0057] Fig.15 It is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0058] Fig.16 It is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0059] Fig.17It is a schematic diagram of a layout of another part of a film layer of a shift register unit provided by an embodiment of the present disclosure;

[0060] Fig.18 is a schematic diagram of a circuit layout of another shift register unit provided by an embodiment of the present disclosure;

[0061] Fig.19 It is a schematic diagram of a layout of a portion of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0062] Fig. 20 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0063] Fig.21 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0064] Fig. 22 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0065] Fig.23 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0066] Fig.24 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0067] Fig.25 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0068] Fig.26 is a schematic diagram of a layout of another part of a film layer of another shift register unit provided by an embodiment of the present disclosure;

[0069] Fig. 27 is a schematic flow chart of a driving method of a shift register unit provided by an embodiment of the present disclosure;

[0070] Fig.28 is a driving timing diagram of a shift register unit provided by an embodiment of the present disclosure;

[0071] Fig.29 is a structural schematic diagram of a display driver provided by an embodiment of the present disclosure;

[0072] Fig.30 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0074] It can be understood that the transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is called the first pole and the drain is called the second pole. According to the form in the accompanying drawings, the middle end of the transistor is specified as the control pole, which can also be called the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type transistor and an N-type transistor, wherein the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in various embodiments of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not represent that the first potential or the second potential in the full text has a specific value.

[0075] The embodiment of the present disclosure provides a shift register unit that can better match the timing requirements of N-type transistors and / or P-type transistors in pixels, has better driving flexibility and better driving effect. Figure 1 As shown, the shift register unit includes: an input control circuit 01 and an output control circuit 02.

[0076] Among them, the input control circuit 01 is respectively connected to the first clock line CB, the second clock line CKn, the input signal terminal IN_n and the input node Q_n, and is used to control the on and off of the input signal terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock line CB and the second clock signal provided by the second clock line CKn.

[0077] For example, the input control circuit 01 can control the input signal terminal IN_n and the input node Q_n to be connected when the potential of the first clock signal is the first potential and the potential of the second clock signal is the first potential, so that the input signal provided by the input signal terminal IN_n is output to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input signal terminal IN_n to be disconnected from the input node Q_n when the potential of the first clock signal is the second potential, or the potential of the second clock signal is the second potential.

[0078] It can be understood that "n" indicates that the shift register unit is the nth stage shift register unit, and correspondingly, "nm" indicates the first m stages of the shift register unit cascaded, and "n+m" indicates the last m stages of the shift register unit cascaded, and n can be an integer greater than 1, and m can be an integer less than n and greater than 1. For example, m can be 1, that is, except for the first stage shift register unit, each stage shift register unit can be cascaded with the previous stage shift register unit and the next stage shift register unit respectively. The following embodiments are all explained by taking m as 1 as an example. Moreover, generally, the multi-stage shift register unit can be connected to multiple rows of pixels in a one-to-one correspondence. Of course, it is not limited to a one-to-one connection. For example, each stage shift register unit can be connected to at least two rows of pixels.

[0079] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, and the second potential may be an invalid potential. Furthermore, for a P-type transistor in a pixel, the first potential may be a low potential (low, L) relative to the second potential. For an N-type transistor in a pixel, the first potential may be a high potential (high, H) relative to the second potential. Accordingly, it can be seen that resetting the signal output to the P-type transistor means controlling the potential of the signal output to the P-type transistor to be a high potential H; resetting the signal output to the N-type transistor means controlling the potential of the signal output to the N-type transistor to be a low potential L. In addition, a high potential can be represented by a binary "1" and a low potential can be represented by a binary "0".

[0080] Continue to refer Figure 1 The output control circuit 02 is respectively connected to the input node Q_n, the reset control line Trst and the output signal terminal OUT_n, and is used to control the potential of the output signal terminal OUT_n based on the potential of the input node Q_n and the reset control signal provided by the reset control line Trst, so as to output a display driving signal to the P-type transistor and / or N-type transistor of each pixel in at least one row of pixels through the output signal terminal OUT_n, so as to drive the light-emitting element of each pixel to emit light.

[0081] Optionally, the display drive signal includes a reset signal or a light emitting control signal. That is, the output control circuit 02 can output a reset signal to a reset transistor in a pixel through the output signal terminal OUT_n. Alternatively, the output control circuit 02 can output a light emitting control signal to a light emitting control transistor in a pixel through the output signal terminal OUT_n.

[0082] For example, the output control circuit 02 can control the potential of the output signal terminal OUT_n to be a low potential 0 when the potential of the input node Q_n is a high potential 1 and / or the potential of the reset control signal is a high potential 1; and the output control circuit 02 can control the potential of the output signal terminal OUT_n to be a high potential 1 when the potential of the input node Q_n is a low potential 0 and the potential of the reset control signal is a low potential 0. In this way, a display driving signal (such as a light emitting control signal) including a high potential 1 and a low potential 0 (that is, including a first potential and a second potential) can be output through the output signal terminal OUT_n, and a pulse with a required timing can be output to the P-type transistor and / or the N-type transistor in the pixel, so as to meet the driving requirements of the PMOS switch-type pixel, or meet the driving requirements of the NMOS switch-type pixel, or meet the driving requirements of the CMOS switch-type pixel.

[0083] In addition, the reset control signal provided by the reset control line Trst can be flexibly set so that the output control circuit 02 can control the potential of the output signal terminal OUT_n to be an invalid potential when the display panel is powered on or off, so as to globally reset the display drive signal output to the pixel to ensure good reliability of the switch. Of course, the display drive signal output to the pixel can also be reset during the blanking time of each frame (i.e., the Porch period) to ensure good display uniformity of each frame.

[0084] For example, taking the display driving signal as a light-emitting control signal as an example, when the display panel is powered on or off, for the output signal terminal OUT_n connected to the N-type transistor in the pixel, the potential of the reset control signal provided by the reset control line Trst can be set to a high potential 1, that is, the potential of the reset control signal is set high, so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to be a low potential 0, thereby resetting the light-emitting control signal output to the N-type transistor. In addition, when the reset is completed, the potential of the reset control signal provided by the reset control line Trst can be set to remain at a low potential 0, so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to change with the potential change of the input node Q_n. Similarly, for the output signal terminal OUT_n connected to the P-type transistor in the pixel, the potential of the reset control signal provided by the reset control line Trst can be set to a low potential of 0, that is, the potential of the reset control signal is lowered, and at the same time, the potential of the input node Q_n is controlled to be a low potential of 0, so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to be a high potential of 1, thereby resetting the light emitting control signal output to the P-type transistor. In addition, when the reset is completed, the potential of the reset control signal provided by the reset control line Trst can be set to remain at a high potential of 1, so that the output control circuit 02 controls the potential of the output signal terminal OUT_n to change with the potential of the input node Q_n.

[0085] Optionally, in some embodiments, the reset control line Trst may also be replaced by a clock line or other enable line, so as to output a single-pulse display drive signal, which is suitable for switching control of a single-pulse P-type / N-type transistor.

[0086] It can be understood that a PMOS switch-type pixel refers to a pixel in which the pixel circuit includes multiple P-type transistors; an NMOS switch-type pixel refers to a pixel in which the pixel circuit includes multiple N-type transistors; and a CMOS switch-type pixel refers to a pixel in which the pixel circuit includes at least one P-type transistor and at least one N-type transistor. MOS is the abbreviation of metal-oxide-semiconductor, that is, the transistor in the pixel circuit can be a MOS tube. In addition, the transistor can also be a thin film transistor (TFT). That is, the transistor in the pixel circuit can be a MOSTFT, the P-type transistor can be called a PMOS TFT, and the N-type transistor can be called an NMOS TFT. Of course, this is just a schematic description.

[0087] Optionally, taking a CMOS switch type pixel as an example, Figure 2 FIG. 1 is a schematic diagram showing a circuit structure of a pixel provided by an embodiment of the present disclosure. Figure 2 As shown, the pixel may include a pixel circuit and a light-emitting element L1. The pixel circuit may include eight transistors T1 to T8 and one capacitor Cst, that is, a circuit of an 8T1C structure. The light-emitting element L1 may be an organic light-emitting diode (OLED). The connection method of each part is referred to in Figure 2 As shown, no further details are given. In addition, the signal terminals connected to the pixel include: a gate signal terminal Gate, reset signal terminals Reset1, Reset2 and Reset3, a data signal terminal Vdata, a reset power supply terminal V1, V2 and V3, a light emitting control terminal EM, a pull-up power supply terminal EVDD, and a pull-down power supply terminal ELVSS. Of course, in some other embodiments, the pixel circuit may also be other structures, such as an 8T2C structure. The light emitting element L1 may also be of other types. For example, a micro light emitting diode Micro-LED, also known as MLED. The embodiments disclosed herein are not limited to this.

[0088] For a PMOS switch type pixel, the eight transistors T1 to T8 may all be PMOS TFTs; for an NMOS switch type pixel, the eight transistors T1 to T8 may all be NMOS TFTs; and for a CMOS switch type pixel, Figure 2As shown, T2 and T5 can be NMOS TFTs, and other transistors except T2 and T5 can be PMOS TFTs. Moreover, among the transistors T4 and T5 connected to the light-emitting control terminal EM to receive the light-emitting control signal, transistor T4 can be a PMOS TFT, and transistor T5 can be an NMOS TFT. Accordingly, the light-emitting control terminal EM connected to transistor T4 can be identified as EM_P, and the light-emitting control terminal EM connected to transistor T5 can be identified as EM_N. "N" represents the relevant signal terminal connected to the NMOS TFT, and "P" represents the relevant signal terminal connected to the PMOS TFT. The identification of other signal terminals can be similar. For example, Figure 2 The transistor T1 of the PMOS TFT is connected to the gate signal terminal Gate_P, and the transistor T2 of the NMOS TFT is connected to the gate signal terminal Gate_N.

[0089] Taking the light emission control signal as an example, for a PMOS switch-type pixel, since the transistors T4 and T5 receiving the light emission control signal are both PMOS TFTs, the same or similar P-type light emission control signal can be used to drive the transistors T4 and T5 to work. For an NMOS switch-type pixel, since the transistors T4 and T5 receiving the light emission control signal are both NMOS TFTs, the same or similar N-type light emission control signal can be used to drive the transistors T4 and T5 to work. Figure 2 In the CMOS switch-type pixel shown, since the transistor T4 receiving the light-emitting control signal is a PMOS TFT and T5 is an NMOS TFT, it is necessary to use an inverted P-type light-emitting control signal and an N-type light-emitting control signal to drive the transistors T4 and T5 to work respectively. Here, the P-type light-emitting control signal refers to a light-emitting control signal with a first potential of 0 and a second potential of 1; the N-type control signal refers to a light-emitting control signal with a first potential of 1 and a second potential of 0. The gate drive signal is the same and will not be described here.

[0090] Optionally, Figure 2 Take the pixel circuit shown as an example, Figure 3 FIG. 1 shows a driving timing diagram of a pixel circuit. Figure 3 As shown, the driving sequence may include phases t1 to t5 that are executed sequentially.

[0091] In phase t1, the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P can be a high potential, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM_N can be a low potential. Accordingly, the transistors T4 and T5 can be turned off or shut down. Furthermore, the pull-up power supply terminal EVDD and the pull-down power supply terminal EVSS can be disconnected, so that the light-emitting element L1 is turned off.

[0092] In stage t2, the potential of the gate drive signal provided by the gate signal terminal Gate_N can be a high potential, and the potential of the reset signal provided by the reset signal terminal Reset1 / Reset3 can be a low potential. Accordingly, transistors T2, T3 and T6 can all be turned on. Furthermore, the reset power supply terminal V2 can be made to output reset power supply signals to nodes P3 and P1 respectively through the turned-on transistors T3 and T2 in sequence, so as to reset nodes P1 and P3 to the potential V20 of the reset power supply signal provided by the reset power supply terminal V2, so that the potential of node P2 gradually changes to V20-Vth_Td, where Vth_Td refers to the threshold voltage of transistor T8 (also called driving transistor Td). And, the reset power supply terminal V1 can be made to output a reset power supply signal to node P4 (i.e., the anode of OLED) through the turned-on transistor T6, so as to reset node P4 to the potential of the reset power supply signal provided by the reset power supply terminal V1.

[0093] In phase t3, the potential of the reset signal provided by the reset signal terminal Reset1 / Reset3 can all be high potential, the potential of the gate drive signal provided by the gate signal terminal Gate_N can be maintained at a high potential, and the potential of the gate drive signal provided by the gate signal terminal Gate_P can be low potential. Accordingly, transistors T3 and T6 can be turned off, and transistors T1, T2 and T8 can all be turned on. Furthermore, the data signal terminal Vdata can transmit a data signal to the node P2 through the turned-on transistor T1, thereby charging the potential of the node P2 to the potential Vdata0 of the data signal, and charging the node P3 and the node P1 to a potential of Vdata0+Vth_Td.

[0094] In phase t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes a low potential, and the potential of the reset signal provided by the reset signal terminal Reset2 is a low potential. Accordingly, the transistor T2 can be turned off, and the transistor T7 can be turned on. Furthermore, the reset power supply terminal V3 can output a reset power supply signal to the node P2 through the turned-on transistor T7 to reset the node P2 to the potential V30 of the reset power supply signal provided by the reset power supply terminal V3. If V30>Vdata0, the potential of the node P3 can be changed to V30+Vth_Td, otherwise, the potential of the node P3 remains at Vdata0+Vth_Td.

[0095] In stage t5, the potential of the reset signal provided by the reset signal terminal Reset2 becomes a high potential, the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P becomes a low potential, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM_N can become a high potential. Accordingly, the transistor T7 can be turned off, and the transistors T4 and T5 can be turned on. In addition, under the storage effect of the storage capacitor Cst, the potential of the node P1 remains at the potential of the previous stage, so that the transistor T8 remains turned on. Furthermore, a path can be formed between the pull-up power supply terminal EVDD and the pull-down power supply terminal EVSS, so that the light-emitting element L1 can emit light. The light-emitting current Id, which is positively correlated with the light-emitting brightness, can be determined by the potential of the node P1 and the potential of the node P2. Among them, the potential of the node P1 is Vdata0+Vth_Td, and the potential of the node P2 is the potential EVDD0 of the pull-up power supply signal provided by the pull-up power supply terminal EVDD. Accordingly, based on the current calculation formula, it can be determined that Id=K(Vdata0-EVDD0) 2 K is determined by the inherent characteristics of the transistor T8, such as the width-to-length ratio W / L, the capacitance Cox, and the mobility μ. That is, the light-emitting current transmitted from the pixel circuit to the light-emitting element L1 may be independent of the threshold voltage Vth_Td of the driving transistor, and thus the drift of the threshold voltage Vth_Td of the transistor T8 will not affect the light-emitting brightness of the light-emitting element L1, thereby ensuring a good light-emitting effect of the light-emitting element L1.

[0096] It can be understood that based on the above driving principle introduction, transistors T1 and T2 can be called data writing transistors, transistors T3, T6 and T7 can be called reset transistors, transistors T4 and T5 can be called light emitting control transistors, and transistor T8 can be called a driving transistor.

[0097] On this basis, as described above, the output signal terminal OUT_n of the shift register unit can be connected to the light emitting control terminal EM of the pixel circuit (eg, Figure 2 EM_N and EM_P) shown in the figure are connected and used to provide the required light-emitting control signal to the light-emitting control terminal EM. Figure 3 The inverted P-type light emitting control signal and N-type light emitting control signal are used to drive Figure 2 Alternatively, the output signal terminal OUT_n of the shift register unit can also be connected to the reset signal terminal Reset of the pixel circuit (eg, Figure 2 Reset1, Reset2 and Reset3) are connected and used to provide a reset signal to the reset signal terminal Reset. Figure 3 The reset signal is shown.

[0098] Of course, it is not limited to satisfying Figure 3The timing shown. And it is not limited to providing a reset signal and a light emitting control signal. For example, in some other embodiments, the output signal terminal OUT_n of the shift register unit can also be connected to the gate signal terminal Gate of the pixel circuit (eg, Figure 2 The gate_N or Gate_P shown in the figure is connected and is used to provide a gate driving signal to the gate signal terminal Gate.

[0099] Next, combine Figure 4 It can be seen from the schematic diagram of a circuit arrangement that, in the layout, the output control circuit 02 and the input control circuit 01 are sequentially arranged along the first direction X1 and in the direction close to the pixel. The reset control line Trst, the first clock line CB and the second clock line CKn are sequentially arranged along the first direction X1 and in the direction close to the pixel, and the reset control line Trst, the first clock line CB and the second clock line CKn all extend along the second direction Y1.

[0100] The second direction Y1 may intersect with the first direction X1. For example, the first direction X1 may be a pixel row direction, the second direction Y1 may be a pixel column direction, and the first direction X1 and the second direction Y1 may be perpendicular to each other.

[0101] Understandably, Figure 4 The layout shown not only facilitates the connection between the signal lines and the circuits, but also allows the various circuits to be arranged more concentratedly and closely without wasting space, thereby facilitating the narrow frame design of the display device.

[0102] In summary, the embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the potential of the input node under the control of the clock signal; the output control circuit can output a display drive signal to the pixel through the output signal terminal based on the potential of the input node and the reset control signal to drive the pixel to emit light. In this way, the clock signal and the reset control signal can be flexibly set so that the shift register unit outputs a display drive signal that matches the P-type transistor and / or N-type transistor in the pixel. In addition, since the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel, the signal lines connected to the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel, and the signal lines all extend in the second direction intersecting the first direction, it can also be beneficial to the narrow frame design of the display device.

[0103] Optionally, Figure 5 FIG. 1 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. Figure 5 As shown, the shift register unit may further include: a driving enhancement circuit 03.

[0104] The driving enhancement circuit 03 can be connected between the output control circuit 02 and the output signal terminal OUT_n, and can be used to invert the potential of the signal output by the output control circuit 02 at least once and then output it to the output signal terminal OUT_n. In this way, the driving capability of the shift register unit can be enhanced.

[0105] Optionally, in Figure 5 Based on this, continue to refer to Figure 4 It can be seen from the layout shown that the driving enhancement circuit 03 and at least one of the input control circuit 01 and the output control circuit 02 can be arranged in sequence along the second direction Y1. In this way, the connection between the signal line and the circuit can be facilitated, and the narrow frame design of the display device can be facilitated.

[0106] For example, a part of the driving enhancement circuit 03 can be arranged in sequence with the input control circuit 01 along the second direction Y1, another part of the driving enhancement circuit 03 can be arranged in sequence with the output control circuit 02 along the second direction Y1, and the driving enhancement circuit 03 can also include another part located on the side of the input control circuit 01 away from the output control circuit 02. That is, the driving enhancement circuit 03 can also be arranged in sequence with the input control circuit 01 and the output control circuit 02 along the first direction X1 and in a direction away from the pixel.

[0107] Optionally, continue to refer to Figure 5 It can be seen that the shift register unit may further include: a latch circuit 04 .

[0108] The latch circuit 04 can be connected to the third clock line CK, the fourth clock line CBn, the input node Q_n and the intermediate node Q1_n respectively, and can be used to respond to the third clock signal provided by the third clock line CK and the fourth clock signal provided by the fourth clock line CBn, control the on-off of the intermediate node Q1_n and the input node Q_n, and output the potential of the intermediate node Q1_n to the input node Q_n after inverting. The intermediate node Q1_n can be a connection node between the drive enhancement circuit 03 and the output control circuit 02.

[0109] For example, the latch circuit 04 can control the intermediate node Q1_n and the input node Q_n to be turned on when the potential of the third clock signal is the first potential and the potential of the fourth clock signal is the first potential, and at the same time, the potential of the intermediate node Q1_n is inverted and output to the input node Q_n; and the latch circuit 04 can control the intermediate node Q1_n to be disconnected from the input node Q_n when the potential of the third clock signal is the second potential or the potential of the fourth clock signal is the second potential. In this way, the potential of the input node Q_n can be made the same as the potential of the intermediate node Q1_n, which serves the purpose of latching the potential of the input node Q_n, or it can also be said that the latch circuit 04 can store the potential of the input node Q_n to prevent the potential of the input node Q_n from leaking.

[0110] Optionally, in some embodiments, the first clock line CB and the fourth clock line CBn may be shared, and the second clock line CKn and the third clock line CK may be shared. For example, the first clock line CB and the fourth clock line CBn may both be the fourth clock line CBn, and the second clock line CKn and the third clock line CK may both be the second clock line CKn.

[0111] Optionally, on this basis, continue to refer to Figure 4 It can be seen from the layout shown that the latch circuit 04 can be located between the driving enhancement circuit 03 and at least one of the input control circuit 01 and the output control circuit 02. The third clock line CK and the fourth clock line CBn can be located on the side of the reset control line Trst close to the pixel, and the third clock line CK and the fourth clock line CBn can be arranged in sequence along the first direction X1 and along the direction close to the pixel, and the third clock line CK and the fourth clock line CBn can both extend along the second direction Y1. In this way, the connection between the signal line and the circuit can be facilitated, and the narrow frame design of the display device can be facilitated.

[0112] For example, a portion of the latch circuit 04 may be located between the drive enhancement circuit 03 and the input control circuit 01 , and another portion of the latch circuit 04 may be located between the drive enhancement circuit 03 and the output control circuit 02 .

[0113] Optionally, in the above Figure 4 Based on the structure shown, Figure 6 FIG. 1 shows a schematic diagram of a circuit structure of a shift register unit. Figure 6As shown, the input control circuit 01 may include: a first transmission gate Tg1. The output control circuit 02 may include: an NOR gate NOR. The latch circuit 04 may include: a first NOT gate INV1 and a second transmission gate Tg2. The drive enhancement circuit 03 may include: three second NOT gates INV2-1, INV2-2 and INV2-3. Among them, the NOT gate may also be called an inverter, and the transmission gate may also be called a transmission switch.

[0114] Among them, the first transmission gate Tg1 can be connected between the input signal terminal IN_n and the input node Q_n, and can also be connected to the first clock line CB and the second clock line CKn respectively. The two input ends of the NOR gate NOR can be connected to the input node Q_n and the reset control line Trst respectively, and the output end of the NOR gate NOR can be connected to the intermediate node Q1_n. The input end of the first NOT gate INV1 can be connected to the intermediate node Q1_n, and the output end of the first NOT gate INV1 can be connected to the input node Q_n through the second transmission gate Tg2, and the second transmission gate Tg2 can also be connected to the third clock line CK and the fourth clock line CBn respectively. The three second NOT gates INV2-1, INV2-2 and INV2-3 can be connected in series between the intermediate node Q1_n and the output signal terminal OUT_n.

[0115] That is, in some embodiments, the driving enhancement circuit 03 can invert the potential of the output signal of the output control circuit 02 an odd number of times and then output it to the output signal terminal OUT_n. That is, the driving enhancement circuit 03 can control the potential of the output signal terminal OUT_n to be opposite to the potential of the output signal of the output control circuit 02.

[0116] Of course, in some other embodiments, the driving enhancement circuit 03 can also invert the potential of the output signal of the output control circuit 02 an even number of times and then output it to the output signal terminal OUT_n. That is, the driving enhancement circuit 03 can control the potential of the output signal terminal OUT_n to be the same as the potential of the output signal of the output control circuit 02.

[0117] Alternatively, the output signal terminal OUT_n may include: a first output signal terminal OUTN_n and a second output signal terminal OUTP_n, the first output signal terminal OUTN_n may be used to connect to an N-type transistor in a pixel, and the second output signal terminal OUTP_n may be used to connect to a P-type transistor in a pixel. Figure 2 The first output signal terminal OUTN_n can be connected to the light emitting control terminal EM_N, that is, it can be connected to the N-type transistor T5; the second output signal terminal OUTP_n can be connected to the light emitting control terminal EM_P, that is, it can be connected to the P-type transistor T4. Accordingly, the driving enhancement circuit 03 can include: two driving enhancement sub-circuits.

[0118] Among them, one driving enhancement subcircuit can be connected between the output control circuit 02 and the first output signal terminal OUTN_n, and can be used to invert the potential of the output signal of the output control circuit 02 for an even number of times and then output it to the first output signal terminal OUTN_n. Another driving enhancement subcircuit can be connected between the output control circuit 02 and the second output signal terminal OUTP_n, and can be used to invert the potential of the output signal of the output control circuit 02 for an odd number of times and then output it to the second output signal terminal OUTP_n. Optionally, in some embodiments, the two driving enhancement subcircuits can share at least one second invertor INV2.

[0119] It is understandable that by setting the driving enhancement circuit 03 to include a plurality of second inverters INV2 connected in series, the driving capability of the output signal through the output signal terminal OUT_n can be amplified step by step, thereby enhancing the driving capability. Accordingly, the second inverter INV2 can also be called an amplifier (AMP).

[0120] It can also be understood that the logic operation principle of the NOR gate is: all 0s output 1, and 1 outputs 0; that is, when the potential of each received signal is a low potential 0, the potential of the output signal can be controlled to be a high potential 1; otherwise, as long as the potential of a received signal is a high potential 1, the potential of the output signal is controlled to be a low potential 0. Based on this, it can be known that:

[0121] The output control circuit 02 including the NOR gate NOR can control the potential of the intermediate node Q1_n to be a low potential 0 when the potential of the input node Q_n is a high potential 1 and / or the potential of the reset control signal provided by the reset control line Trst is a high potential 1; and the output control circuit 02 including the NOR gate NOR can control the potential of the intermediate node Q1_n to be a high potential 1 when the potential of the input node Q_n is a low potential 0 and the potential of the reset control signal provided by the reset control line Trst is a low potential 0.

[0122] It can be understood that, for the scenario where the output signal terminal OUT_n is connected to the light-emitting control terminal EM and a light-emitting control signal is provided to the light-emitting control terminal EM, the output signal terminal OUT_n can be identified as GP_n, and the intermediate node Q1_n can be identified as GNc_n. In addition, the connection node between the first invertor INV1 and the second transmission gate Tg2 can be identified as GPc_n. Correspondingly, the intermediate node Q1_n of the previous stage shift register unit can be identified as GNc_n-1, and the connection node between the first invertor INV1 and the second transmission gate Tg2 in the previous stage shift register unit can be identified as GPc_n-1. In addition, the input signal terminal IN_n can be connected to the node GPc_n-1 of the cascaded previous stage shift register unit. Of course, the input signal terminal IN_1 of the first stage shift register unit needs to be connected to the start signal line STV to receive the start signal from the start signal line STV.

[0123] And, in Figure 6 Based on the reference Figure 7 It can be seen that the NOR gate NOR, the first NOT gate INV1 and the first second NOT gate INV2-1 can be arranged in sequence along the second direction Y1, the first transmission gate Tg1, the second transmission gate Tg2 and the second second NOT gate INV2-2 can be arranged in sequence along the second direction Y1, and the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be arranged in sequence along the first direction X1 and in the direction close to the pixel. It can be understood that the shift register unit recorded in the embodiment of the present disclosure can be located on one side of the substrate, that is, each circuit device can be set on the substrate.

[0124] Optionally, the sizes of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 may be increased in sequence. Figure 7 It can also be seen that the length of the positive projection of the third second NOT gate INV2-3 on the substrate may include the total length of the positive projections of other gate circuits on the substrate except the third second NOT gate INV2-3. The length direction may be parallel to the second direction Y1. The other gate circuits here may include, for example: a NOR gate NOR, a first NOT gate INV1 and a first second NOT gate INV2-1 arranged in sequence along the second direction Y1.

[0125] It is understandable that, combined with Figure 6It can be seen that the first second NOT gate INV2-1 can refer to the second NOT gate INV2 directly connected to the intermediate node Q1_n; the second second NOT gate INV2-1 can refer to the second NOT gate INV2 connected in series between the first second NOT gate INV2-1 and the third second NOT gate INV2-3; the third second NOT gate INV2-3 can refer to the second NOT gate INV2 directly connected to the output signal terminal OUT_n. Correspondingly, it can be known that the third second NOT gate INV2-3 can also refer to the last second NOT gate INV2.

[0126] It is also understandable that, combined with Figure 4 and Figure 7 The arrangement provided by the embodiment of the present disclosure can make good use of limited space to centrally arrange components included in multiple circuits, thereby effectively reducing the border width, and further facilitating improving the driving capability and stability of the shift register unit.

[0127] Optionally, in Figure 6 On the basis of Figure 8 FIG. 1 is a schematic diagram showing a circuit structure of a shift register unit provided by an embodiment of the present disclosure. Figure 8 It can be seen that the NOR gate NOR, the first invertor INV1, and each second invertor INV2 can also be connected to the first power line VGH and the second power line VGL respectively, and can be used to work based on the first power signal provided by the first power line VGH and the second power signal provided by the second power line VGL. In addition, the potential of the first power signal can be greater than the potential of the second power signal.

[0128] Optionally, the first power line VGH and the second power line VGL are at least located at both sides of the reset control line Trst in the first direction X1, and the first power line VGH and the second power line VGL may both extend along the second direction Y1.

[0129] For example, combined with Figure 7 In the first direction X1, for the NOR gate NOR, the NAND gate NAND and the first second NOT gate INV2-1, the first power line VGH and the second power line VGL connected thereto can be shared and can be located on the left and right sides of the reset control line Trst. For the third second NOT gate INV2-3, the first power line VGH and the second power line VGL connected thereto can be adjacent.

[0130] Optionally, the width of the first power line VGH and the width of the second power line VGL can both be greater than the width of the reset control line Trst. Of course, it can also be greater than the width of the start signal line STV connected to the first-stage shift register unit. Optionally, the width of the first power line VGH connected to the third second NOT gate INV2-3 can be greater than the width of the first power line VGH connected to other gate circuits, and the width of the second power line VGL connected to the third second NOT gate INV2-3 can be greater than the width of the second power line VGL connected to other gate circuits. The other gate circuits may include: at least one of the NOR gate NOR, the first NOT gate INV1, the second second NOT gate INV2-2 and the first first NOT gate INV2-1.

[0131] That is, in the embodiment of the present disclosure, the widths of the reset control line Trst and the start signal line STV may be both smaller than the width of the first power line VGH, and smaller than the width of the second power line VGL. Optionally, in some embodiments, the widths of the reset control line Trst and the start signal line STV may also be similar or equal.

[0132] For example, taking the reset control line Trst as an example, its width can generally be 3 to 10 micrometers (μm). For example, the width of the reset control line Trst can be 4μm. The width of the first power line VGH and the width of the second power line VGL can generally be 5 to 30μm. For example, the width of the first power line VGH connected to the first second invertor INV2-1 and the second second invertor INV2-2 and the width of the second power line VGL can both be 10μm, and the width of the first power line VGH and the width of the second power line VGL connected to the third second invertor INV2-3 can be 30μm.

[0133] It is understandable that by setting the width of the power line (including the first power line VGH and the second power line VGL) to be wider, the driving ability of the gate circuit can be enhanced. In addition, since the last second invertor INV2 is directly connected to the pixel through the output signal terminal OUT_n, the driving ability of the last second invertor INV2 can be enhanced by setting the width of the power line connected to the last second invertor INV2 to be the widest. And, by separating the power line connected to the last second invertor INV2 from the power lines connected to other second invertors INV2, the problem of abnormal output caused by the negative bias of the threshold voltage Vth of the N-type transistor can be solved. For example, when the threshold voltage Vth of the N-type transistor is negatively biased, the power signal provided by the second power line VGL connected to the last second invertor INV2 can be separately adjusted to ensure the normal output of the N-type transistor.

[0134] To distinguish, in the figure, the first power line VGH and the second power line VGL connected to other gate circuits are respectively marked as VGH1 and VGL1, while the first power line VGH and the second power line VGL connected to the last second invertor INV2 (that is, the third second invertor INV2-3) are respectively marked as VGH2 and VGL2.

[0135] Optionally, in some embodiments, among the plurality of second invertors INV2, the potential of the first power signal provided by the first power line VGH2 connected to the last second invertor INV2 may be greater than or equal to the potential of the first power signal provided by the first power line VGH1 connected to other second invertors INV2. And / or, the potential of the second power signal provided by the second power line VGL2 connected to the last second invertor INV2 may be less than or equal to the potential of the second power signal provided by the second power line VGL2 connected to other second invertors INV2. In this way, the charging and discharging speed of the second invertor INV2 directly connected to the output signal terminal OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit, and reducing leakage and saving power consumption.

[0136] That is, in one embodiment, a single VGH and a single VGL power supply can be used, that is, any NOT gate in the shift register unit is connected to the same first power line VGH and second power line VGL. Alternatively, in another embodiment, a dual VGH and a dual VGL power supply can also be used. Of course, it is not limited to the dual VGH and dual VGL power supply.

[0137] Optionally, the first clock line CB, the second clock line CKn, the reset control line Trst, the third clock line CK and the fourth clock line CBn may all be located on the same side of the output control circuit 02 away from the latch circuit 04, and may all extend along the second direction Y1. Figure 7 , the signal lines connected to the shift register units can all be located above the overall circuit structure.

[0138] Optionally, in some embodiments, the first clock line CB, the second clock line CKn, the reset control line Trst, the third clock line CK, and the fourth clock line CBn may be arranged at equal intervals in the first direction X1. That is, the interval between any two adjacent signal lines may be a fixed interval. For example, the fixed interval may be greater than or equal to 3 μm.

[0139] Optionally, based on the foregoing description, it can be known that the shift register unit provided in the embodiment of the present disclosure can actually be divided into two modules: an input shift module and a drive enhancement module. Among them, the input shift module may include: a first transmission gate Tg1, a non-OR gate NOR, a second transmission gate Tg2 and a first non-gate INV1. The drive enhancement module may include: three second non-gates INV2-1, INV2-2 and INV2-3.

[0140] And, combined with Figure 4 and Figure 7 It can be seen that relative to the pixel area, the input shift module can be located in the upper left part of the layout, the drive enhancement module can be located in the lower right part of the layout, and the first second non-gate INV2-1 and the second second non-gate INV2-2 in the drive enhancement module can be arranged up and down or left and right, and the third second non-gate INV2-3 can be located at the rightmost end of the layout.

[0141] Optionally, in some embodiments, in the input shift module, the NOR gate NOR may be located at the leftmost end, the first transmission gate Tg1 and the second transmission gate Tg2 may be located to the right of the NOR gate NOR and arranged from top to bottom, and the first NOT gate INV1 may be located below the NOR gate NOR. In the drive enhancement circuit, the first second NOT gate INV2-1 may be located below the first NOT gate INV1, and the first second NOT gate INV2-1, the second second NOT gate INV2-2 and the third second NOT gate INV2-3 may be arranged from left to right.

[0142] Optionally, continue to refer to Figure 8 It can be seen that the first transmission gate Tg1 may include: a first P-type transistor Tp_1 and a first N-type transistor Tn_1 .

[0143] Among them, the gate of the first P-type transistor Tp_1 and the gate of the first N-type transistor Tn_1 can be connected to the first clock line CB and the second clock line CKn respectively, the first electrode of the first P-type transistor Tp_1 and the first electrode of the first N-type transistor Tn_1 can both be connected to the input signal terminal IN_n, and the second electrode of the first P-type transistor Tp_1 and the second electrode of the first N-type transistor Tn_1 can both be connected to the input node Q_n.

[0144] Optionally, continue to refer to Figure 8 It can be seen that the NOR gate NOR may include: a second P-type transistor Tp_2, a second N-type transistor Tn_2, a third P-type transistor Tp_3 and a third N-type transistor Tn_3.

[0145] Among them, the gate of the second P-type transistor Tp_2 and the gate of the third N-type transistor Tn_3 can both be connected to the reset control line Trst, the first electrode of the second P-type transistor Tp_2 can be connected to the first power line VGH1, the second electrode of the second P-type transistor Tp_2 can be connected to the first electrode of the third P-type transistor Tp_3, the second electrode of the third P-type transistor Tp_3, the second electrode of the second N-type transistor Tn_2 and the second electrode of the third N-type transistor Tn_3 can all be connected to the intermediate node Q1_n, the first electrode of the second N-type transistor Tn_2 and the first electrode of the third N-type transistor Tn_3 can both be connected to the second power line VGL1, and the gate of the third P-type transistor Tp_3 and the gate of the second N-type transistor Tn_2 can both be connected to the input node Q_n.

[0146] Optionally, continue to refer to Figure 8 It can be seen that the first invertor INV1 may include: a fourth P-type transistor Tp_4 and a fourth N-type transistor Tn_4, and the fourth N-type transistor Tn_4 may be a dual-gate transistor. The second transmission gate Tg2 may include: a fifth P-type transistor Tp_5 and a fifth N-type transistor Tn_5. It can be understood that by setting the fourth N-type transistor Tn_4 as a dual-gate transistor, the leakage in the output holding stage can be reduced, thereby reducing the operating power consumption of the shift register unit. Of course, other transistors can also be set as dual-gate transistors in the same way.

[0147] Among them, the gate of the fourth P-type transistor Tp_4 and the gate of the fourth N-type transistor Tn_4 can be both connected to the intermediate node Q1_n, the first electrode of the fourth P-type transistor Tp_4 and the first electrode of the fourth N-type transistor Tn_4 can be respectively connected to the first power line VGH1 and the second power line VGL1, the second electrode of the fourth P-type transistor Tp_4 and the second electrode of the fourth N-type transistor Tn_4 can be both connected to the first electrode of the fifth P-type transistor Tp_5 and the first electrode of the fifth N-type transistor Tn_5, the gate of the fifth P-type transistor Tp_5 and the gate of the fifth N-type transistor Tn_5 can be respectively connected to the third clock line CK and the fourth clock line CBn, and the second electrode of the fifth P-type transistor Tp_5 and the second electrode of the fifth N-type transistor Tn_5 can be both connected to the input node Q_n.

[0148] Optionally, continue to refer to Figure 8 It can be seen that the first second NOT gate INV2-1 may include: a sixth P-type transistor Tp_6 and a sixth N-type transistor Tn_6. The second second NOT gate INV2-2 may include: a seventh P-type transistor Tp_7 and a seventh N-type transistor Tn_7. The third second NOT gate INV2-3 may include: an eighth P-type transistor Tp_8 and an eighth N-type transistor Tn_8.

[0149] Among them, the gate of the sixth P-type transistor Tp_6 and the gate of the sixth N-type transistor Tn_6 can be connected to the intermediate node Q1_n, the gate of the seventh P-type transistor Tp_7 and the gate of the seventh N-type transistor Tn_7 can be connected to the second electrode of the sixth P-type transistor Tp_6 and the second electrode of the sixth N-type transistor Tn_6, and the gate of the eighth P-type transistor Tp_8 and the gate of the eighth N-type transistor Tn_8 can be connected to the second electrode of the seventh P-type transistor Tp_7 and the second electrode of the seventh N-type transistor Tn_7. The second electrode of the eighth P-type transistor Tp_8 and the second electrode of the eighth N-type transistor Tn_8 can be connected to the output signal terminal OUT_n, and the first electrode of the sixth P-type transistor Tp_6, the first electrode of the seventh P-type transistor Tp_7, and the first electrode of the eighth P-type transistor Tp_8 can be connected to the first power line VGH, and the first electrode of the sixth N-type transistor Tn_6, the first electrode of the seventh N-type transistor Tn_7 and the first electrode of the eighth N-type transistor Tn_8 can be connected to the second power line VGL.

[0150] The first electrode of the sixth P-type transistor Tp_6 and the first electrode of the seventh P-type transistor Tp_7 are connected to the first power line VGH1, and the first electrode of the eighth P-type transistor Tp_8 is connected to the first power line VGH2. The first electrode of the sixth N-type transistor Tn_6 and the first electrode of the seventh N-type transistor Tn_7 are connected to the second power line VGL1, and the first electrode of the eighth N-type transistor Tn_8 is connected to the second power line VGL2.

[0151] That is, the shift register unit provided in some embodiments of the present disclosure may include 8 PMOS TFTs and 8 NMOS TFTs, a total of 16 TFTs. Of course, it is not limited to only including these 16 TFTs, that is, the shift register unit provided in the present disclosure can be formed by combining and deleting basic modules. For example, in some embodiments, the shift register unit may also include other gate circuits (such as a NOT gate / NAND gate) connected between the intermediate node Q1_n and the driving enhancement circuit 04.

[0152] Optionally, Figure 8 Take the structure shown as an example, Fig. 9 A schematic diagram of a shift register unit layout is shown. Figure 8 and Fig. 9 It can be seen that the first P-type transistor Tp_1 and the first N-type transistor Tn_1 may be sequentially arranged along the first direction X1 and along a direction close to the pixel.

[0153] The third P-type transistor Tp_3 and the second P-type transistor Tp_2 can be arranged in sequence and connected in series along the second direction Y1 and along the direction close to the first invertor INV1, the second N-type transistor Tn_2 can be located on the side of the third P-type transistor Tp_3 away from the second P-type transistor Tp_2, the third N-type transistor Tn_3 can be located on the side of the third P-type transistor Tp_3 close to the second P-type transistor Tp_2, and the second N-type transistor Tn_2 and the third N-type transistor Tn_3 are both close to the pixel relative to the third P-type transistor Tp_2.

[0154] The fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be arranged in sequence along the first direction X1 and in a direction close to the pixel, the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can be arranged in sequence along the first direction X1 and in a direction close to the pixel, and the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 are both close to the first transmission gate Tg1 relative to the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4.

[0155] Furthermore, the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can be arranged in sequence along the first direction X1 and in a direction close to the pixel, the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 can be arranged in sequence along the second direction Y1 and in a direction away from the first transmission gate Tg1, and the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can be arranged in sequence along the second direction Y1.

[0156] That is, combined Fig. 9 In the disclosed embodiment, the four TFTs included in the NOR gate can be arranged vertically, and two P-type TFTs of the four TFTs can be connected in series, and two N-type TFTs can be located on the upper and lower sides of the two P-type TFTs. On the basis of the upper and lower arrangement of the first transmission gate Tg1 and the second transmission gate Tg2, the same type (i.e., P-type or N-type) TFTs can be located on the same side to facilitate the connection between the TFTs, and the clock line can be located near the top of the P-type TFT and the N-type TFT to facilitate the connection. The first inversion gate INV1 is located in the middle of the Layout, which is convenient for connection with the front module and transmission to the next level, wherein the N-type TFT and the P-type TFT can be arranged horizontally, and as described above, the N-type TFT can be a double-gate design to reduce leakage, thereby reducing the power consumption of the shift register unit. In the first second NOT gate INV2-1, the N-type TFT and the P-type TFT can be placed in parallel on the left and right, and their gate holes can be arranged in a straight line; the N-type TFT and the P-type TFT in each second NOT gate INV2 in the second second NOT gate INV2-2 and the third second NOT gate INV2-3 can be arranged in parallel on the left and right. Fig. 9As shown, they can be placed up and down, or they can be placed horizontally, or the N-type TFT and P-type TFT in one second invertor INV2 can be placed horizontally, and the N-type TFT and P-type TFT in another second invertor INV2 can be placed up and down, which can be determined according to the space of the Layout.

[0157] And, if Fig. 9 As shown, the sizes of transistors in the first second NOT gate INV2-1 to the third second NOT gate INV2-3 can be increased successively. That is, the sizes of the first second NOT gate INV2-1 to the third second NOT gate INV2-3 corresponding to the above-mentioned can be increased successively. The transistors here can refer to P-type transistors and / or N-type transistors.

[0158] It can be understood that the channel width of the transistor can characterize the size of the transistor. Taking an N-type transistor as an example, the channel width of the transistor in the first second NOT gate INV2-1 can be 2 to 15 μm, such as the channel width of the transistor in the first second NOT gate INV2-1 can be 8 μm. The channel width of the transistor in the second second NOT gate INV2-2 can be approximately 1.5 to 10 times the channel width of the transistor in the first second NOT gate INV2-1, such as the channel width of the transistor in the second second NOT gate INV2-2 can be 30 μm. The channel width of the transistor in the third second NOT gate INV2-3 can be the largest and can be determined by the pixel load connected to it. For example, the channel width of the transistor in the third second NOT gate INV2-3 can be 60 μm.

[0159] Of course, the sizes of the N-type transistor and the P-type transistor in each second NOT gate INV2 may be the same, or may be different, which may be determined by the mobility. For example, taking the third second NOT gate INV2-3 as an example, the mobility of the P-type transistor (i.e., the eighth P-type transistor Tp_8) included therein may be 1 / 3 of the mobility of the N-type transistor (i.e., the eighth N-type transistor Tn_8), and accordingly, the channel width of the P-type transistor included therein may be 1 / 3 of the channel width of the N-type transistor included therein.

[0160] Furthermore, the sizes of transistors in the first transmission gate Tg1, the NOR gate NOR, the first NOT gate INV1, and the second transmission gate Tg2 can all be smaller than the sizes of transistors in any second NOT gate INV2. That is, except for the first second NOT gate INV2-1 to the third second NOT gate INV2-3, the sizes of transistors in other gate circuits can all be smaller. For example, the transistors in other gate circuits can be equivalent to the size of the switch tube, and the channel width can be between 2 and 10 μm.

[0161] Understandably, Figure 7 and Fig. 9The layout shown is only a schematic illustration, and any adjustments made on this basis to facilitate narrow frame design are applicable to the embodiments of the present disclosure.

[0162] Optionally, in Fig. 9 On the basis of Figures 10 to 17 A schematic diagram of the structure of different film layers of a shift register unit is shown. Figures 9 to 17 It can be seen that the transistor in the shift register unit provided in the embodiment of the present disclosure may include: a first active layer Poly, a first gate metal layer GATE1, a second gate metal layer GATE2, a second active layer IGZO, a third gate metal layer GATE3, a first source-drain metal layer SD1, and a second source-drain metal layer SD2 stacked in sequence. These film layers may be located on one side of the substrate.

[0163] The first active layer SD1 can be used as an active layer of a P-type transistor in the shift register unit, and the second active layer IGZO can be used as an active layer of an N-type transistor in the shift register unit.

[0164] It is understandable that Poly may refer to an active layer formed of polysilicon material, and IGZO refers to an active layer formed of indium gallium zinc oxide. Of course, in some other embodiments, other materials may be used to form the first active layer, and other materials may be used to form the second active layer.

[0165] It can also be understood that, taking the third second NOT gate INV2-3 as an example, since the size of the P-type transistor is generally smaller than the size of the N-type transistor, Fig.10 and Fig.13 It can be seen that in the third second NOT gate INV2-3, the size of the active layer (i.e., the first active layer Poly) of the P-type transistor (i.e., the eighth P-type transistor Tp_8) is smaller than the size of the active layer (i.e., the second active layer IGZO) of the N-type transistor (i.e., the eighth N-type transistor Tn_8). The size here may refer to the area of ​​the positive projection of the active layer on the substrate. The sizes of the active layers of the P-type transistors and the N-type transistors in other gate circuits are similar and will not be described one by one.

[0166] Optionally, a first interlayer dielectric layer ILD and a second interlayer dielectric layer EBB may be included between the third gate metal layer GATE3 and the first source and drain metal layer SD1. The first interlayer dielectric layer ILD may have a plurality of vias K1 for overlapping the film layers on both sides of the first interlayer dielectric layer ILD. The second interlayer dielectric layer EBB may have a plurality of vias K2 for overlapping the film layers on both sides of the second interlayer dielectric layer EBB. It can be understood that the vias K1 of the first interlayer dielectric layer ILD can be used for overlapping the film layers between P-type transistors. The vias K2 of the second interlayer dielectric layer EBB can be used for overlapping the film layers between N-type transistors. In addition, a passivation layer PVX and a flat layer PLN stacked in sequence may be included between the first source and drain metal layer SD1 and the second source and drain metal layer SD2, and the passivation layer PVX and the flat layer PLN may have a plurality of third vias K3 for overlapping the film layers on both sides of the passivation layer PVX and the flat layer PLN. Correspondingly, the vias K1 , K2 and K3 may also be referred to as connecting vias.

[0167] On this basis, it can be known that the gate hole in the first second NOT gate INV2-1 described above may refer to: a via hole between the first gate metal layer GATE1 and the source-drain metal layer SD; a via hole between the second gate metal layer GATE2 and the source-drain metal layer SD; and a via hole between the third gate metal layer GATE3 and the source-drain metal layer SD. The source-drain metal layer here may be, for example, the first source-drain metal layer.

[0168] Optionally, in the embodiment of the present disclosure, each connection via can be away from the second source-drain metal layer SD2, so as to reduce the parasitic capacitance formed between the second source-drain metal layer SD2 and other metal layers (such as the first source-drain metal layer). In addition, each connection via can be staggered, that is, the orthographic projections on the substrate do not overlap.

[0169] Optionally, in some embodiments, Fig.18 As shown, at least part of the first source-drain metal layer SD1 can be reused with at least one of the first active layer Poly, the first gate metal layer GATE1, the second gate metal layer GATE2 and the second active layer IGZO to reduce the overlapping area between the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0170] That is, the first source-drain metal layer SD1 can be replaced by any layer on the side of the first source-drain metal layer SD1 away from the second source-drain metal layer SD2, thereby reducing the overlapping area of ​​the first source-drain metal layer SD1 and the second source-drain metal layer SD2, thereby reducing the parasitic capacitance formed between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, which is conducive to further reducing the working power consumption of the shift register unit. Of course, in some other embodiments, the same purpose can be achieved by reducing some redundant vias and redundant first source-drain metal layers SD1.

[0171] Optionally, in Fig.18 On the basis of Figures 19 to 26 Another schematic diagram shows the structure of different film layers of the shift register unit. Fig. 9 and Fig.18 Based on the comparison Fig.13 and Fig.12 It can be seen that at position 1, the second active layer IGZO can be reused as the first source and drain metal layer SD1 at this position. Fig.11 and Fig. 20 It can be seen that at position 2, the first gate metal layer GATE1 can be reused as the first source and drain metal layer SD1 at this position. Fig.14 and Fig.23 It can be seen that at position 3, the third gate metal layer GATE3 can be reused as the first source-drain metal layer SD1 at this position. The above examples can reduce the overlapping area of ​​the first source-drain metal layer SD1 and the second source-drain metal layer SD2, thereby reducing parasitic capacitance and power consumption.

[0172] It is understandable that, combined with Figure 8 It can be seen that position 1 may refer to: the position of the connection node between the first invertor INV1 and the second transmission gate Tg2, that is, the position of the node GPc_n. Position 2 may refer to: the position of the connection node between the third P-type transistor Tp_3 and the second P-type transistor Tp_2 in the NOR gate NOR. Position 3 may refer to: the position of the connection node between the first second invertor INV2-1 and the NOR gate NOR, that is, the position of the intermediate node Q1_n.

[0173] It is also understandable that Fig.18 The structure shown is relative to Fig. 9For the structure shown, for position 1, it can be considered that the area of ​​the second active layer IGZO is increased to reduce the area of ​​the first source-drain metal layer SD1. For position 2, it can be considered that the area of ​​the first gate metal layer GATE1 is increased to reduce the area of ​​the first source-drain metal layer SD1. For position 3, it can be considered that the area of ​​the third gate metal layer GATE3 is increased to reduce the area of ​​the first source-drain metal layer SD1. Of course, the above methods are all schematic illustrations. In some embodiments, other film layers can also be reused as the first source-drain metal layer SD1 to achieve the purpose of reducing the overlapping area between the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0174] Optionally, based on the transistor arrangement of the embodiment of the present disclosure, Fig. 9 and Fig.10 It can also be seen that the first active layer Poly of the second P-type transistor Tp_2 and the third P-type transistor Tp_3 can be a whole (ie, can be shared); the first active layer Poly of the first P-type transistor Tp_1 and the fifth P-type transistor Tp_5 can be shared. Fig. 9 and Fig.13 It can be seen that the second active layer IGZO of the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5 can be shared.

[0175] Optionally, based on the transistor arrangement of the embodiment of the present disclosure, the active layer is reused as the first source and drain metal layer SD1, combined with Fig.18 and Fig. 22 It can be seen that: in addition to the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5 sharing the second active layer IGZO, the fourth N-type transistor Tn_4 and the fifth N-type transistor Tn_5 can also share the second active layer IGZO. That is, the first N-type transistor Tn_1, the fourth N-type transistor Tn_4 and the fifth N-type transistor Tn_5 can be a whole.

[0176] It is understandable that by sharing the active layer, the structure can be simplified and the cost can be saved while facilitating the narrow frame design.

[0177] It should be noted that Figures 9 to 17 The layout shown is the layout of two adjacent shift register units (eg, the nth stage shift register unit GOAn and the n+1th stage shift register unit GOAn+1).

[0178] Figures 10 to 26 The layout shown is the layout of a shift register unit (eg, the n-th stage shift register unit GOAn).

[0179] Based on the above records, it can be known that the shift register unit provided in the embodiment of the present disclosure can be a CMOS EM / Preset GOA circuit, EM refers to the light-emitting control terminal connected to the light-emitting control transistor in the pixel, Preset refers to the reset signal terminal connected to the P-type reset transistor in the pixel, CMOS can refer to the ability to output the required display drive signal to both the P-type transistor and the N-type transistor in the pixel, the N-type transistor included in the shift register unit can be responsible for low-level output, and the P-type transistor can be responsible for high-level output. In addition, the layout of the CMOS EM / Preset GOA is compact and concentrated, which can help reduce the border width and improve the driving capability and circuit stability.

[0180] In summary, the embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the potential of the input node under the control of the clock signal; the output control circuit can output a display drive signal to the pixel through the output signal terminal based on the potential of the input node and the reset control signal to drive the pixel to emit light. In this way, the clock signal and the reset control signal can be flexibly set so that the shift register unit outputs a display drive signal that matches the P-type transistor and / or N-type transistor in the pixel. In addition, since the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel, the signal lines connected to the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel, and the signal lines all extend in the second direction intersecting the first direction, it can also be beneficial to the narrow frame design of the display device.

[0181] The embodiment of the present disclosure also provides a method for driving a shift register unit, which can be used to drive the shift register unit described above. Fig. 27 As shown, the method includes:

[0182] Step 2701, in the first stage, a first clock signal of a first potential is provided to the first clock line, a second clock signal of a first potential is provided to the second clock line, and a reset control signal of a first potential is provided to the reset control line, the input control circuit controls the input signal terminal to be connected to the input node in response to the first clock signal of the first potential and the second clock signal of the first potential, and the output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal of the first potential.

[0183] Step 2702, second stage, providing a first clock signal of a second potential to the first clock line, providing a second clock signal of a second potential to the second clock line, and providing a reset control signal of a second potential to the reset control line, the input control circuit controls the input signal terminal to be disconnected from the input node in response to the first clock signal of the second potential and the second clock signal of the second potential, and the output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal of the second potential.

[0184] Step 2703, the third stage, providing a first clock signal of a first potential to the first clock line, providing a second clock signal of a first potential to the second clock line, and providing a reset control signal of a second potential to the reset control line, the input control circuit controls the input signal terminal to be connected to the input node in response to the first clock signal of the first potential and the second clock signal of the first potential, and the output control circuit controls the potential of the output signal terminal based on the potential of the input node and the reset control signal of the second potential.

[0185] Optionally, Figure 6 and Figure 8 Take the structure shown as an example, Fig.28 A driving timing diagram of a shift register unit is shown.

[0186] First, refer to Fig.28 It can be seen that there are 4 groups of clock signals, namely CK, CBn, CB and CKn, with a period of 2H. Among them, the clock signal provided by CK and the clock signal provided by CB can differ by 1H, the clock signal provided by CKn and the clock signal provided by CB can be inverted signals, and the clock signal provided by CBn and the clock signal provided by CK can be inverted signals. In addition, Fig.28 The timing of dual VGH1 / VGH2 and dual VGL1 / VGL2 is also identified.

[0187] Secondly, continue to combine Fig. 27 , the driving principle of the shift register unit is described as follows:

[0188] (1) In the first stage t01, a low-potential first clock signal can be provided to the first clock line CB, and a high-potential second clock signal can be provided to the second clock line CKn, so that the first transmission gate Tg1 is turned on, and then the input signal terminal IN_n is turned on with the input node Q_n, and the input signal terminal IN_n can output an input signal to the input node Q_n, and the potential of the input signal can be a high potential (for example, it can be the potential of the turn-on signal provided by the turn-on signal line STV). In addition, a high-potential reset control signal can be provided to the reset control line Trst, and then the potential of the node GNc_n (that is, the middle node Q1_n) can be controlled to be a low potential after passing through the NOR gate NOR, and then the potential of the node GPc_n can be controlled to be a high potential after passing through the first NOT gate INV1, and the potential of the output signal terminal GP_n can be controlled to be a high potential after passing through the three second NOT gates INV2. Furthermore, a third clock signal with a high potential may be provided to the third clock line CK, and a fourth clock signal with a low potential may be provided to the fourth clock line CBn, so that the second transmission gate Tg2 is turned off, thereby disconnecting the node GPc_n from the input node Q_n.

[0189] It is understandable that if Fig.28 As shown, the low-potential pulse width of the clock signal provided by the clock line CK and the clock signal provided by the clock line CB are both smaller than the high-potential pulse width, generally 0 to 2 μs less than 1H, and can be flexibly selected according to the load RC. Based on this setting, as described above, the influence of clock delay can be eliminated, and the first transmission gate Tg1 and the second transmission gate Tg2 can be prevented from being turned on at the same time, which causes the risk of competition between the NOR gate NOR in the output control subcircuit 02 and the first NOT gate INV1 in the latch circuit 04 when the input state is switched.

[0190] (2) In the second stage t02, a high-potential first clock signal can be provided to the first clock line CB, and a low-potential second clock signal can be provided to the second clock line CKn, so that the first transmission gate Tg1 is turned off, thereby disconnecting the input signal terminal IN_n from the input node Q_n. A low-potential third clock signal can be provided to the third clock line CK, and a high-potential fourth clock signal can be provided to the fourth clock line CBn, so that the second transmission gate Tg2 is turned on, thereby connecting the node GPc_n to the input node Q_n, thereby latching the potential of the input node Q_n to the high potential of the node GPc_n. In addition, a low-potential reset control signal can be provided to the reset control line Trst, so that the potential of the node GNc_n can be controlled to be low after passing through the NOR gate NOR, and the potential of the node GPc_n can be controlled to be high after passing through the first NOT gate INV1, and the potential of the output signal terminal GP_n can be controlled to be high after passing through the three second NOT gates INV2.

[0191] (3) In the third stage t03, a low-potential first clock signal can be provided to the first clock line CB, and a high-potential second clock signal can be provided to the second clock line CKn, so that the second transmission gate Tg2 is turned on, and the input signal terminal IN_n is connected to the input node Q_n, and the input signal terminal IN_n can output the input signal to the input node Q_n, and the potential of the input signal can be low. In addition, a low-potential reset control signal can be provided to the reset control line Trst, and then the potential of the node GNc_n can be controlled to be high after passing through the NOR gate NOR, and the potential of the node GPc_n can be controlled to be low after passing through the first inversion gate INV1, and the potential of the output signal terminal GP_n can be controlled to be low after passing through the three second inversion gates INV2. In addition, a high-potential third clock signal can be provided to the third clock line CK, and a low-potential fourth clock signal can be provided to the fourth clock line CBn, so that the second transmission gate Tg2 is turned off, and the node GPc_n is disconnected from the input node Q_n.

[0192] Understandably, Fig.28 can be adapted to provide a display drive signal to a PMOS TFT in a pixel, and Fig.28 The effective potential width of the output display driving signal is 2H.

[0193] Optionally, the shift register unit may also be connected to a display driver IC (DDIC) and used to receive the above-mentioned signals provided by the DDIC, such as a clock signal. That is, the DDIC may provide the above-mentioned required signals to each signal terminal connected to the shift register unit, so that the shift register unit outputs the required display drive signal to the pixel.

[0194] It can be understood that since the driving method of the shift register unit can have basically the same technical effects as the shift register unit described in the above embodiments, the technical effects of the driving method of the shift register unit will not be repeatedly described here for the purpose of brevity.

[0195] The present disclosure also provides a display driving circuit. Fig.29 As shown, the display driving circuit comprises: at least two cascaded shift register units GOA as described above.

[0196] For example, Fig.29 The shift register unit GOA shown is a shift register unit EM GOA that provides a light emitting control signal, that is, the output signal terminal OUT_n is connected to the light emitting control terminal EM of the pixel. Correspondingly, the display driving circuit including the EM GOA can also be called a light emitting control circuit.

[0197] also, Fig. 27 In the display driving circuit shown, four groups of clock signals (including four clock signal terminals, namely CK, CB, CKn and CBn) are used, and dual VGH and dual VGL (including first power supply terminals VGH1 and VGH2, and second power supply terminals VGL1 and VGL2) are used for power supply.

[0198] And, the cascade mode is shown as follows: the input signal terminal IN_1 of the first stage shift register unit EM GOA is connected to the start signal line STV, and the input signal terminal IN_n of the other stage shift register unit EM GOA is connected to the node GPc_n of the previous stage shift register unit EM GOA. For the design of other structures, refer to the relevant records of the aforementioned shift register unit, which will not be repeated here one by one.

[0199] Optionally, in some embodiments, a dummy shift register unit, namely, a dummy GOA, may be added to the first row or the last row to meet the required timing requirements or drive load.

[0200] It can be understood that, since the display driving circuit can have substantially the same technical effects as the shift register unit described in the above embodiments, the technical effects of the display driving circuit will not be repeatedly described herein for the purpose of brevity.

[0201] The present disclosure also provides a display device. Fig.30 As shown, the display device includes: a display panel 10, and Fig.29 The display driving circuit 00 is shown.

[0202] The display panel 10 may include a plurality of pixels ( Fig.30 (not shown), the display driving circuit 00 is connected to a plurality of pixels and is used to transmit a light emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light. Figure 2 The display driving circuit 00 can be connected to the light emitting control terminals EM of multiple pixels and is used to transmit the light emitting control terminals EM to the multiple pixels. Figure 3 The light emitting control signal shown is used to drive the multiple pixels to emit light.

[0203] Optionally, the display device may be any product or component having a display function, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, etc. Furthermore, the display device may be any appropriate display device, including but not limited to a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and an e-book.

[0204] It can be understood that, since the display device can have substantially the same technical effects as the shift register unit described in the above embodiments, the technical effects of the display device will not be repeatedly described herein for the purpose of brevity.

[0205] It is understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0206] For example, the use of "first", "second", "third" and similar words do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0207] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0208] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0209] The words "connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0210] “Up”, “down”, “left”, “right”, etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0211] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0212] The above descriptions are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: An input control circuit is connected to the first clock line, the second clock line, the input signal terminal and the input node respectively, and is used to control the connection and disconnection of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line; an output control circuit, connected to the input node, the reset control line and the output signal terminal respectively, and used to control the potential of the output signal terminal based on the potential of the input node and the reset control signal provided by the reset control line, so as to output a display driving signal to the P-type transistor and / or the N-type transistor of each pixel in at least one row of pixels through the output signal terminal, so as to drive the light-emitting element of each pixel to emit light; Among them, the output control circuit and the input control circuit are arranged in sequence along the first direction and in the direction close to the pixel; the reset control line, the first clock line and the second clock line are arranged in sequence along the first direction and in the direction close to the pixel, and the reset control line, the first clock line and the second clock line all extend along the second direction; the second direction intersects with the first direction.

2. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: A drive enhancement circuit connected between the output control circuit and the output signal terminal and used to invert the potential of the signal output by the output control circuit at least once and then output it to the output signal terminal; The driving enhancement circuit and at least one of the input control circuit and the output control circuit are arranged in sequence along the second direction.

3. The shift register unit according to claim 2, characterized in that: The shift register unit also includes: a latch circuit, connected to the third clock line, the fourth clock line, the input node and the intermediate node respectively, and used to control the on-off of the intermediate node and the input node in response to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line, and output the potential of the intermediate node to the input node after inverting the potential, wherein the intermediate node is a connection node between the drive enhancement circuit and the output control circuit; Among them, the latch circuit is located between the drive enhancement circuit and at least one of the input control circuit and the output control circuit; the third clock line and the fourth clock line are located on the side of the reset control line close to the pixel, and the third clock line and the fourth clock line are arranged in sequence along the first direction and along the direction close to the pixel, and the third clock line and the fourth clock line both extend along the second direction.

4. The shift register unit according to claim 3, characterized in that: The input control circuit includes: a first transmission gate; the output control circuit includes: an NOR gate; the latch circuit includes: a first NOT gate and a second transmission gate; the drive enhancement circuit includes: three second NOT gates; Wherein, the first transmission gate is connected between the input signal terminal and the input node, and is also connected to the first clock line and the second clock line respectively; the two input terminals of the NOR gate are respectively connected to the input node and the reset control line, and the output terminal of the NOR gate is connected to the intermediate node; the input terminal of the first NOT gate is connected to the intermediate node, the output terminal of the first NOT gate is connected to the input node through the second transmission gate, and the second transmission gate is also connected to the third clock line and the fourth clock line respectively; the three second NOT gates are sequentially connected in series between the intermediate node and the output signal terminal; Furthermore, the NOR gate, the first NOR gate and the first second NOR gate are arranged in sequence along the second direction, the first transmission gate, the second transmission gate and the second second NOR gate are arranged in sequence along the second direction, the first second NOR gate to the third second NOR gate are arranged in sequence along the first direction and in a direction close to the pixel, and the sizes of the first second NOR gate to the third second NOR gate increase sequentially.

5. The shift register unit according to claim 4, characterized in that: The NOR gate, the first NOT gate, and each of the second NOT gates are also connected to a first power line and a second power line, respectively, and are used to operate based on a first power signal provided by the first power line and a second power signal provided by the second power line, and the potential of the first power signal is greater than the potential of the second power signal; Among them, the first power line and the second power line are at least located on both sides of the reset control line in the first direction, and the first power line and the second power line both extend along the second direction; the width of the first power line and the width of the second power line are both greater than the width of the reset control line; the width of the first power line connected to the third second NOT gate is greater than the width of the first power line connected to other gate circuits, and the width of the second power line connected to the third second NOT gate is greater than the width of the second power line connected to other gate circuits; the other gate circuits include: at least one of the NOR gate, the first NOT gate, the second second NOT gate and the first first NOT gate.

6. The shift register unit according to claim 4, characterized in that: The first transmission gate includes: a first P-type transistor and a first N-type transistor; The gate of the first P-type transistor and the gate of the first N-type transistor are connected to the first clock line and the second clock line respectively, the first electrode of the first P-type transistor and the first electrode of the first N-type transistor are both connected to the input signal terminal, and the second electrode of the first P-type transistor and the second electrode of the first N-type transistor are both connected to the input node; Furthermore, the first P-type transistor and the first N-type transistor are sequentially arranged along the first direction and in a direction close to the pixel.

7. The shift register unit according to claim 4, characterized in that: The NOR gate includes: a second P-type transistor, a second N-type transistor, a third P-type transistor and a third N-type transistor; The gate of the second P-type transistor and the gate of the third N-type transistor are both connected to the reset control line, the first electrode of the second P-type transistor is connected to the first power line, the second electrode of the second P-type transistor is connected to the first electrode of the third P-type transistor, the second electrode of the third P-type transistor, the second electrode of the second N-type transistor and the second electrode of the third N-type transistor are all connected to the intermediate node, the first electrode of the second N-type transistor and the first electrode of the third N-type transistor are both connected to the second power line, and the gate of the third P-type transistor and the gate of the second N-type transistor are both connected to the input node; Furthermore, the third P-type transistor and the second P-type transistor are arranged in sequence and connected in series along the second direction and along the direction close to the first NOT gate, the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, the third N-type transistor is located on the side of the third P-type transistor close to the second P-type transistor, and the second N-type transistor and the third N-type transistor are both close to the pixel relative to the third P-type transistor.

8. The shift register unit according to claim 4, characterized in that: The first NOT gate includes: a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a double-gate transistor; the second transmission gate includes: a fifth P-type transistor and a fifth N-type transistor; The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are both connected to the intermediate node, the first electrode of the fourth P-type transistor and the first electrode of the fourth N-type transistor are respectively connected to the first power line and the second power line, the second electrode of the fourth P-type transistor and the second electrode of the fourth N-type transistor are both connected to the first electrode of the fifth P-type transistor and the first electrode of the fifth N-type transistor, the gate of the fifth P-type transistor and the gate of the fifth N-type transistor are respectively connected to the third clock line and the fourth clock line, and the second electrode of the fifth P-type transistor and the second electrode of the fifth N-type transistor are both connected to the input node; Furthermore, the fourth P-type transistor and the fourth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the fifth P-type transistor and the fifth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, and the fifth P-type transistor and the fifth N-type transistor are both close to the first transmission gate relative to the fourth P-type transistor and the fourth N-type transistor.

9. The shift register unit according to claim 4, characterized in that: The first second NOT gate includes: a sixth P-type transistor and a sixth N-type transistor; the second second NOT gate includes: a seventh P-type transistor and a seventh N-type transistor; the third second NOT gate includes: an eighth P-type transistor and an eighth N-type transistor; The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are both connected to the intermediate node, the gate of the seventh P-type transistor and the gate of the seventh N-type transistor are both connected to the second electrode of the sixth P-type transistor and the second electrode of the sixth N-type transistor, the gate of the eighth P-type transistor and the gate of the eighth N-type transistor are both connected to the second electrode of the seventh P-type transistor and the second electrode of the seventh N-type transistor, the second electrode of the eighth P-type transistor and the second electrode of the eighth N-type transistor are both connected to the output signal terminal, and the first electrode of the sixth P-type transistor, the first electrode of the seventh P-type transistor, and the first electrode of the eighth P-type transistor are all connected to the first power line, and the first electrode of the sixth N-type transistor, the first electrode of the seventh N-type transistor, and the first electrode of the eighth N-type transistor are all connected to the second power line; Furthermore, the sixth P-type transistor and the sixth N-type transistor are arranged in sequence along the first direction and in a direction close to the pixel, the seventh P-type transistor and the seventh N-type transistor are arranged in sequence along the second direction and in a direction away from the first transmission gate, and the eighth P-type transistor and the eighth N-type transistor are arranged in sequence along the second direction.

10. The shift register unit according to any one of claims 4 to 9, characterized in that: The sizes of transistors in the first second NOT gate to the third second NOT gate increase successively; Furthermore, sizes of transistors in the first transmission gate, the NOR gate, the first NOT gate, and the second transmission gate are all smaller than sizes of transistors in any of the second NOT gates.

11. The shift register unit according to any one of claims 3 to 9, characterized in that: The first clock line, the second clock line, the reset control line, the third clock line and the fourth clock line are all located on the same side of the output control circuit away from the latch circuit, and are arranged at equal intervals in the first direction.

12. The shift register unit according to any one of claims 1 to 9, characterized in that: The transistor in the shift register unit comprises: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence; The first active layer is used as an active layer of a P-type transistor in the shift register unit, and the second active layer is used as an active layer of an N-type transistor in the shift register unit.

13. The shift register unit according to claim 12, characterized in that: At least a portion of the first source-drain metal layer is reused with at least one of the first active layer, the first gate metal layer, the second gate metal layer and the second active layer to reduce an overlapping area between the first source-drain metal layer and the second source-drain metal layer.

14. A display driving circuit, characterized in that: The display driving circuit comprises: at least two cascaded shift register units according to any one of claims 1 to 13.

15. A display device, characterized in that: The display device comprises: a display panel, and a display driving circuit as claimed in claim 14; The display panel includes a plurality of pixels. The display driving circuit is connected to the plurality of pixels and is used to transmit light emitting control signals to the plurality of pixels to drive the plurality of pixels to emit light.

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