Semiconductor structure and forming method thereof
By monitoring the photolithography alignment signal intensity to adjust the etching depth of the alignment mark, the problem of high monitoring time and cost during the photolithography alignment process is solved, and the alignment accuracy and cost savings are improved.
Patent Information
- Application Number
- CN202411241376.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2024-12-13
AI Technical Summary
The existing monitoring methods for lithography alignment processes increase the duration and cost, and the alignment accuracy is affected, especially after multiple film layer growth processes, the clarity of lithography alignment marks is reduced, resulting in graphical offset and affecting semiconductors. Device stability.
By monitoring whether the signal strength of the photolithography alignment signal at the alignment position is within the preset signal strength interval, adjust the etching depth of the initial alignment mark to form a zero-layer alignment mark to ensure that the photolithography alignment signal is The preset signal strength is within the range of the strongest signal strength, reducing monitoring time and cost and improving alignment accuracy.
It is realized that the accuracy of alignment is ensured without SEM slice analysis during the semiconductor structure formation process, reduce the monitoring time of the lithographic alignment process and reduce the monitoring cost, ensuring the accuracy of lithographic alignment.
Smart Images
Figure CN119133022A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] As human life becomes more and more intelligent, the semiconductor industry is also developing rapidly. Photolithography is a key process in semiconductor manufacturing, which is used to transfer the pattern on the mask to the wafer surface. However, with the continuous reduction of the feature size of semiconductor devices and the continuous improvement of integration, the precision requirements of photolithography are also increasing. In the semiconductor manufacturing process, in order to accurately transfer the pattern on the mask to the wafer surface, the wafer must be aligned before each exposure of the photoresist.
[0003] At present, the zero-layer alignment mark is mainly used for photolithography alignment. During the alignment process of the wafer, the etching depth of the zero-layer alignment mark is required to monitor the photolithography alignment process.
[0004] However, the existing method of monitoring the lithography alignment process not only increases the monitoring time, but also increases the monitoring cost. Summary of the invention
[0005] The problem to be solved by the present invention is to reduce the monitoring time of the photolithography alignment process and reduce the monitoring cost.
[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising:
[0007] Providing a semiconductor substrate and a first mask, wherein the semiconductor substrate has an initial alignment mark, and the first mask has a first alignment mark;
[0008] Performing photolithography scanning on the initial alignment mark and the first alignment mark to obtain an initial photolithography alignment signal;
[0009] Determining whether the signal strength of the initial photolithography alignment signal at the alignment position is within a preset signal strength strongest range;
[0010] Based on the judgment result, determine whether to adjust the etching depth of the initial alignment mark to obtain a zero-layer alignment mark, and the signal strength of the photolithography alignment signal corresponding to the zero-layer alignment mark at the alignment position is within the preset signal strength strongest range;
[0011] Based on the first mask, a first film layer is formed on the zero-layer alignment mark and the semiconductor substrate.
[0012] In a possible embodiment, determining whether to adjust the etching depth of the initial alignment mark to obtain the zero-layer alignment mark based on the judgment result includes:
[0013] When the signal strength of the initial photolithography alignment signal at the alignment position is within the preset signal strength strongest interval, taking the initial alignment mark as the zero-layer alignment mark;
[0014] When the signal strength of the initial photolithography alignment signal at the alignment position is not within the preset signal strength strongest range, continue to etch the groove of the initial alignment mark until the signal strength of the corresponding photolithography alignment signal at the alignment position is within the preset signal strength strongest range after further etching.
[0015] In a possible embodiment, the step of continuing to etch the groove of the initial alignment mark until the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest range includes:
[0016] The groove of the initial alignment mark is continuously etched, and the signal intensity of the corresponding photolithography alignment signal at the alignment position after the etching is continued is monitored in real time.
[0017] In a possible embodiment, the step of continuing to etch the groove of the initial alignment mark until the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest range includes:
[0018] The signal strength of the corresponding photolithography alignment signal at the alignment position after the continued etching is compared with the preset signal strength strongest interval to determine whether the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest interval.
[0019] In a possible embodiment, the signal strength of the initial photolithography alignment signal at the alignment position includes:
[0020] The initial photolithography alignment signal is subjected to a first operation at an X-direction alignment position and a Y-direction alignment position.
[0021] In a possible embodiment, the first operation includes: taking an average value.
[0022] In a possible embodiment, the preset signal strength strongest interval includes: an interval where the maximum signal strength value of the lithography alignment signal is located.
[0023] In a possible embodiment, the etching depth range of the zero layer alignment mark 41 is [1200A, 1400A].
[0024] In a possible embodiment, forming a first film layer on the zero-layer alignment mark and the surface of the semiconductor substrate based on the first mask includes:
[0025] forming a first material layer on the zero-layer alignment mark and the semiconductor substrate;
[0026] Based on the first mask, the first material layer is etched to form a first film layer.
[0027] An embodiment of the present invention further provides a semiconductor structure, which is formed by any of the above-mentioned methods for forming a semiconductor structure.
[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0029] By applying the solution of the present invention, the initial alignment mark and the first alignment mark are subjected to lithography scanning to obtain an initial lithography alignment signal, and then it can be determined whether to adjust the etching depth of the initial alignment mark by judging whether the signal strength of the initial lithography alignment signal at the alignment position is within the preset signal strength interval, so that the signal strength of the lithography alignment signal corresponding to the zero-layer alignment mark at the alignment position is within the preset signal strength interval, and when other film layers are subsequently formed above the first film layer, a lithography alignment signal with obvious amplitude changes can be obtained, thereby ensuring the alignment accuracy. In this way, in the one-time formation process of the semiconductor structure, by monitoring the signal strength of the lithography alignment signal at the alignment position, the final alignment mark with the optimal etching depth can be obtained without the need for SEM slice analysis, thereby reducing the monitoring time of the lithography alignment process and reducing the monitoring cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention;
[0031] Figure 2 is a top view of a zero-layer alignment mark;
[0032] Figure 3 is a cross-sectional schematic diagram corresponding to a semiconductor structure in one embodiment of the present invention;
[0033] Figure 4 is a schematic diagram of aligning photolithography alignment signals in an embodiment of the present invention;
[0034] Figure 5 It is a schematic diagram of the relationship between the signal intensity at the alignment position of the photolithography alignment signal and the etching depth of the alignment mark groove;
[0035] Figure 6 is a cross-sectional schematic diagram corresponding to another semiconductor structure in an embodiment of the present invention;
[0036] Figure 7is a cross-sectional schematic diagram corresponding to another semiconductor structure in an embodiment of the present invention;
[0037] Figure 8 is a cross-sectional schematic diagram corresponding to another semiconductor structure according to an embodiment of the present invention;
[0038] Fig. 9 is a cross-sectional schematic diagram corresponding to another semiconductor structure in an embodiment of the present invention;
[0039] Figures 10 to 13 Schematic diagram of a curve showing a change in the signal intensity value of a photolithography alignment signal at an alignment position at different etching depths in an embodiment of the present invention. DETAILED DESCRIPTION
[0040] Most existing semiconductor devices require multiple film layer formation processes and photolithography processes on a semiconductor substrate. In order to ensure product quality, each layer of exposure needs to be accurately overlaid.
[0041] However, in actual applications, during the photolithography process alignment after the first film layer formation process, the zero-layer alignment mark received by the alignment detector is relatively clear, and the obtained photolithography alignment signal amplitude varies greatly. When photolithography alignment is performed based on the photolithography alignment signal, the impact on the photolithography alignment accuracy is small. However, during the photolithography alignment after the second film layer growth process, especially the third to seventh film layer growth processes, the zero-layer alignment mark received by the alignment detector becomes increasingly unclear, and even deformed. The obtained photolithography alignment signal amplitude varies increasingly smaller, which greatly affects the alignment accuracy, causing the pattern formed by the photoresist on the film layer after photolithography to shift. After the ion implantation process is performed using the patterned photolithography layer as a mask, the ion implantation area formed in the film layer will shift, affecting the stability of the semiconductor device.
[0042] In order to reduce the influence of the photolithography alignment signal on the alignment accuracy, the photolithography alignment process needs to be monitored.
[0043] The existing scheme for monitoring the photolithography alignment process is to form an alignment mark on the semiconductor substrate, slice it using a scanning electron microscope (SEM), and then measure the etching depth of the zero-layer alignment mark on the SEM slice. The measurement result can be used as a reference for the next etching process of the zero-layer alignment mark. In the photolithography process, only after the last layer of the product is completed can it be determined whether the depth of the zero-layer alignment mark can be aligned. If it cannot be aligned, it is necessary to re-form a new zero-layer alignment mark, and then perform SEM slice measurement, and the re-obtained SEM slice measurement result is used as a reference for the next etching process of the zero-layer alignment mark until the last layer of the product can be aligned.
[0044] Therefore, using SEM for slicing to monitor the lithography alignment process requires the use of a large number of wafers, and the used wafers can only be scrapped, which will increase the monitoring cost to a certain extent. In addition, the slicing measurement process will increase the monitoring time.
[0045] In view of this problem, the present invention provides a method for forming a semiconductor structure. By adopting this method, in the process of forming the semiconductor structure, the etching depth of the zero-layer alignment mark is determined by monitoring whether the signal strength of the lithography alignment signal at the alignment position is within the preset signal strength strongest range, thereby ensuring the accuracy of alignment. Since the accuracy of alignment can be ensured only by monitoring the signal strength of the lithography alignment signal without performing SEM slice analysis, the monitoring time of the lithography alignment process can be reduced and the monitoring cost can be reduced.
[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0047] Reference Figure 1 , an embodiment of the present invention provides a method for forming a semiconductor structure, the method may include the following steps:
[0048] Step 11, providing a semiconductor substrate and a first mask, wherein the semiconductor substrate has an initial alignment mark, and the first mask has a first alignment mark;
[0049] Step 12, performing photolithography scanning on the initial alignment mark and the first alignment mark to obtain an initial photolithography alignment signal;
[0050] Step 13, determining whether the signal strength of the initial photolithography alignment signal at the alignment position is within a preset signal strength strongest range;
[0051] Step 14, based on the judgment result, determining whether to adjust the etching depth of the initial alignment mark to obtain a zero-layer alignment mark, wherein the signal strength of the photolithography alignment signal corresponding to the zero-layer alignment mark at the alignment position is within the preset signal strength strongest range;
[0052] Step 15: forming a first film layer on the zero-layer alignment mark and the semiconductor substrate based on the first mask.
[0053] Figure 2The figure is a top view of a zero-layer alignment mark. The zero-layer alignment mark is formed by four groups of gratings, which are distributed in the XY plane. The two groups of gratings distributed in the X direction are used to form a group of marks X8.0 with a line width of 8um and an interval of 8um, and another group of marks X8.8 with a line width of 8.8μm and an interval of 8.8μm. The two groups of gratings distributed in the Y direction are used to form a group of marks Y8.0 with a line width of 8um and an interval of 8um, and another group of marks Y8.8 with a line width of 8.8μm and an interval of 8.8μm.
[0054] In practical applications, the mark in the X direction is used to measure the deviation between the wafer and the mask in the horizontal direction, and the mark in the Y direction is used to measure the deviation between the wafer and the mask in the vertical direction.
[0055] It should be noted that the zero-layer alignment mark provided in the embodiment of the present invention is only an example and does not constitute a limitation of the present invention. Zero-layer alignment marks of other structures and shapes are also within the protection scope of the present invention.
[0056] In order to more clearly and briefly illustrate the scheme of the present invention, in the following examples, Figure 3 The protrusion 311 and the groove 312 are shown to represent the zero-layer alignment mark.
[0057] Specifically, Figure 3 FIG. 1 is a cross-sectional schematic diagram corresponding to a semiconductor structure in an embodiment of the present invention. Figure 3 The semiconductor structure may include: a semiconductor substrate 30 and an initial alignment mark 31 formed on the semiconductor substrate 30 .
[0058] In a specific implementation, the semiconductor substrate 30 may be a silicon substrate. The silicon substrate may include a device region and a mark region. The device region is used to form a semiconductor device, and the mark region is used to form a zero-layer alignment mark (ZeroMark).
[0059] The process of forming the initial alignment mark 31 on the semiconductor substrate 30 may include: forming a photoresist layer (not shown) covering the surface of the semiconductor substrate 30; patterning the photoresist layer, wherein the opening of the patterned photoresist layer exposes the position of the initial alignment mark groove; etching the semiconductor substrate 30 using the patterned photoresist layer as a mask to form a plurality of protrusions 311 and grooves 312 located on both sides of the protrusions 311. The plurality of protrusions 311 and the grooves 312 on both sides of the protrusions constitute the initial alignment mark 31. The bottom of the groove 312 has a certain step height difference with the surface of the adjacent protrusion 311.
[0060] After the initial alignment mark 31 is formed, before the first film layer is formed on the semiconductor substrate, a first mask is first obtained, on which a first alignment mark is provided. The first alignment mark has a structure and shape similar to the initial alignment mark. For example, both can be Figure 2 The structure and shape of the zero-layer alignment mark are shown in FIG.
[0061] Next, the initial alignment mark and the first alignment mark are photolithographically scanned to obtain an initial photolithographic alignment signal. Specifically, the light generated by the light source is irradiated on the initial alignment mark 31 to form diffracted light, and the diffracted light is reflected into the alignment detector. Since the bottom of the groove 312 and the surface of the adjacent protrusion 311 have a certain step height difference, the intensity of the diffracted light generated by the bottom surface of the groove 312 and the surface of the adjacent protrusion 311 is different. The light of the diffracted light is imaged on the surface of the first mask through the projection lens. The alignment detector identifies the initial alignment mark 31 based on the change in the intensity of the diffracted light, and photolithographically scans the initial alignment mark 31 and the first alignment mark on the first mask to obtain an initial photolithographic alignment signal.
[0062] In some embodiments, the initial photolithography alignment signal may include two groups of sinusoidal wave signals obtained by performing alignment scanning on marks of different distribution directions in the initial alignment mark and the first alignment mark respectively.
[0063] by Figure 2 Taking the zero-layer alignment mark structure shown in FIG as an example, the initial alignment mark and the two groups of lines in the first alignment mark in the X direction (ie, X8.0 and X8.8) are aligned and scanned to obtain the first sine wave signal with a period of 8 μm (eg, Figure 4 The second sine wave signal with a period of 8.8 μm (as shown in the middle curve 41) Figure 4 The initial alignment mark and the two groups of lines in the first alignment mark in the X direction (ie, Y8.0 and Y8.8) are aligned and scanned to obtain a third sine wave signal with a period of 8 μm and a fourth sine wave signal with a period of 8.8 μm. Figure 4 The overlapping position (ie point A) of the first sine wave signal 41 and the second sine wave signal 42 is the alignment position. The third sine wave signal and the fourth sine wave signal also have an alignment position.
[0064] In practical applications, the alignment position may be at the peak of the two sinusoidal wave signals (ie, the signal strength at the alignment position is equal to the peak), or may deviate from the peak (ie, the signal strength at the alignment position is less than the peak).
[0065] The inventors have found that the signal strength at the alignment position of the photolithography alignment signal is related to the etching depth of the alignment mark groove. Figure 5 The curve relationship is shown. Figure 5 It can be seen that as the etching depth of the alignment mark groove continues to increase, the signal strength at the alignment position of the lithography alignment signal continues to rise. When the etching depth of the alignment mark groove reaches a certain depth, the signal strength at the alignment position reaches a peak and then begins to decline. After multiple film layers are formed on the semiconductor substrate and the zero-layer alignment mark, the stronger the signal strength at the alignment position of the lithography alignment signal, the clearer the zero-layer alignment mark received by the alignment detector.
[0066] Therefore, in an embodiment of the present invention, after obtaining the initial photolithography alignment signal, step 13 is performed, that is, determining whether the signal strength of the initial photolithography alignment signal at the alignment position is within a preset signal strength strongest range.
[0067] In an embodiment of the present invention, the initial photolithography alignment signal being at an alignment position may include: the initial photolithography alignment signal being at an X-direction alignment position and a Y-direction alignment position.
[0068] In one embodiment, the signal strength of the initial photolithography alignment signal at the alignment position may be a result of performing a first operation on the initial photolithography alignment signal at the X-direction alignment position and the Y-direction alignment position.
[0069] In a specific implementation, the first operation may be a variety of operations, for example, a sum operation (i.e., summing the X-direction alignment position and the Y-direction alignment position), a product operation (i.e., multiplying the X-direction alignment position and the Y-direction alignment position), etc. It is understandable that no matter what the first operation is, after the first operation, the signal strength of the initial lithography alignment signal at the alignment position can still be reflected.
[0070] In one embodiment of the present invention, the first operation may be to take an average value, that is, to take an average value of the X-direction alignment position and the Y-direction alignment position. Subsequently, the average value of the X-direction alignment position and the Y-direction alignment position is compared with the interval where the maximum signal strength value of the lithography alignment signal is located.
[0071] In a specific implementation, the interval where the maximum signal strength value of the lithography alignment signal is located refers to an interval containing the maximum signal strength value of the lithography alignment signal. The minimum value of the interval is less than the maximum signal strength value of the lithography alignment signal, and the maximum value of the interval is greater than the maximum signal strength value of the lithography alignment signal.
[0072] It should be noted that when the wafer changes, the maximum signal strength value of the lithography alignment signal will also change accordingly.
[0073] In one embodiment, assuming that H represents the maximum signal strength value of the lithography alignment signal, the preset strongest signal strength interval may be [H-α, H+α], 0<α<H. For example, H=1, then α may be 0.1, 0.2 or 0.3, etc.
[0074] Reference Figure 2 When the average value M of the initial photolithography alignment signal at the X-direction alignment position and the Y-direction alignment position is within the preset signal strength strongest interval, the initial alignment mark is used as the zero-layer alignment mark. Taking the preset signal strength strongest interval as [H-α, H+α] as an example, when H-α≤M≤H+α, the initial alignment mark 31 is used as the zero-layer alignment mark.
[0075] When the signal strength of the initial photolithography alignment signal at the alignment position is not within the preset signal strength strongest range, continue to etch the groove of the initial alignment mark until the signal strength of the corresponding photolithography alignment signal at the alignment position is within the preset signal strength strongest range after further etching.
[0076] Specifically, taking the example that the signal strength of the initial photolithography alignment signal at the alignment position is the average value M of the X-direction alignment position and the Y-direction alignment position, and the preset signal strength strongest interval can be [H-α, H+α], when M<H-α, or H+α<M, the etching of the groove of the initial alignment mark can continue.
[0077] In a specific implementation, during the etching of the groove of the initial alignment mark, the signal strength of the corresponding photolithography alignment signal at the alignment position after continued etching can be monitored in real time, that is, the alignment mark after the etching depth is adjusted and the first alignment mark are photolithographically scanned in real time to obtain a new photolithography alignment signal, and the signal strength of the new photolithography alignment signal at the alignment position is monitored, that is, the result of monitoring the new photolithography alignment signal after performing the first operation at the X-direction alignment position and the Y-direction alignment position.
[0078] During this period, a certain etching step length can be set. After each etching step length is continued, the new photolithography alignment signal is obtained by alignment scanning, and the signal strength of the new photolithography alignment signal at the alignment position is compared with the preset signal strength interval. It may take only one etching to obtain a new etching signal whose signal strength at the alignment position is within the preset signal strength interval. It may also take two or more etchings to obtain a new etching signal whose signal strength at the alignment position is within the preset signal strength interval. After obtaining a new etching signal whose signal strength at the alignment position is within the preset signal strength interval, etching is stopped. The alignment mark formed at this time is the zero-layer alignment mark.
[0079] For example, Figure 2After one etching, we get Figure 6 The zero layer alignment mark 41 shown in FIG. The zero layer alignment mark 41 includes a protrusion 412 and grooves 411 located on both sides of the protrusion 412. The depth of the groove 411 is greater than the depth of the groove 311.
[0080] In one embodiment of the present invention, the etching depth range of the zero layer alignment mark 41 is [1200A, 1400A].
[0081] After the zero-layer alignment mark is obtained, a first film layer can be formed on the zero-layer alignment mark and the semiconductor substrate based on the first mask.
[0082] Specifically, refer to Figure 7 , forming a first material layer 42 on the zero-layer alignment mark 41 and the semiconductor substrate 30. Figure 8 , using the aligned pattern on the first mask, the first material layer 42 is etched, and the pattern of the first mask is transferred to the first material layer 42 to form a first film layer 43.
[0083] In a specific implementation, a chemical vapor deposition process may be used to form the material layer 42. The chemical vapor deposition process may be a low-pressure chemical vapor deposition process or an organic metal chemical vapor deposition process.
[0084] In a specific implementation, the first film layer 43 may be an oxide layer, such as a silicon oxide layer. The first film layer 43 has a second alignment mark 44 , which has the same structure and shape as the zero-layer alignment mark 41 and is located above the zero-layer alignment mark 41 .
[0085] In a specific implementation, other film layers may be formed on the first film layer 43, for example, Fig. 9 , a second film layer 45 can be formed on the surface of the first film layer 43, and a third film layer 47 can be formed on the surface of the second film layer 45. Among them, a third alignment mark 46 is provided on the surface of the second film layer 44, and a fourth alignment mark 48 is provided on the third film layer 45. The structure and shape of the third alignment mark 46 are the same as those of the second alignment mark 44 and the zero-layer alignment mark 41, and are located above the second alignment mark 44 and the zero-layer alignment mark 41. The structure and shape of the fourth alignment mark 48 are the same as those of the third alignment mark 46, the second alignment mark 44 and the zero-layer alignment mark 41, and are located above the third alignment mark 46, the second alignment mark 44 and the zero-layer alignment mark 41.
[0086] The method for forming the second film layer 45 includes: performing photolithography scanning on the alignment mark on the second mask and the second alignment mark 44 to obtain a photolithography alignment signal, which has a certain signal strength and can achieve photolithography alignment. After alignment, a second material layer is formed on the surface of the first film layer 43 and the second alignment mark 44, and then the second material layer is etched using the second mask to transfer the pattern of the second mask to the second material layer to form the second film layer 45.
[0087] Similarly, the method for forming the third film layer 47 includes: performing photolithography scanning on the alignment mark on the third mask and the third alignment mark 46 to obtain a photolithography alignment signal, which has a certain signal strength and can achieve photolithography alignment. After alignment, a third material layer is formed on the surface of the second film layer 45 and the fourth alignment mark 48, and then the third material layer is etched using the third mask to transfer the pattern of the third mask to the third material layer to form the third film layer 47.
[0088] In a specific implementation, the second film layer 45 may be a metal layer, such as an aluminum (AL) layer. The third film layer 47 may be a protective layer.
[0089] By adopting the scheme of the present invention, when forming the first film layer, by monitoring the signal strength of the lithography alignment signal at the alignment position, the signal strength of the lithography alignment signal corresponding to the zero-layer alignment mark at the alignment position is made within the preset signal strength strongest range. Therefore, when forming subsequent film layers, a clear lithography alignment signal can also be obtained, thereby realizing lithography alignment, thereby ensuring the accuracy of alignment.
[0090] An embodiment of the present invention further provides a semiconductor structure, which is formed by the method for forming the semiconductor structure described in the above embodiment.
[0091] Specifically, refer to Fig. 9 , the semiconductor structure may include: a semiconductor substrate 30 and a first film layer 43. The semiconductor substrate 30 has a zero-layer alignment mark 41, the first film layer 43 covers the zero-layer alignment mark 41 and the surface of the semiconductor substrate 30, and a second alignment mark 44 is formed on the first film layer 43. The signal strength of the photolithography alignment signal corresponding to the zero-layer alignment mark 41 at the alignment position is within the preset signal strength strongest range.
[0092] In one embodiment of the present invention, the etching depth range of the zero layer alignment mark 41 is [1200A, 1400A].
[0093] In order to verify that the lithography alignment signal with a signal strength at the alignment position within the preset signal strength strongest range can be obtained within the etching depth range, the applicant obtains multiple test wafers with different etching depths, and two initial alignment marks are formed on the semiconductor substrate of each test wafer, namely, initial alignment mark W1 and initial alignment mark W2. The first alignment mark M1 on the first mask is aligned with the initial alignment mark W1 and initial alignment mark W2 on the wafer respectively. The intensity of the lithography alignment signal measured by different alignment detectors is shown in Table 1:
[0094] Table 1
[0095]
[0096] As can be seen from Table 1, two alignment detectors are used to perform lithography scanning on 12 test wafers with different etching depths, and the signal intensity values of the corresponding lithography alignment signals at the alignment positions are obtained.
[0097] Among them, M1W1 refers to the photolithography scanning of the first alignment mark M1 on the first mask and the initial alignment mark W1 on the wafer, and M1W2 refers to the photolithography scanning of the first alignment mark M1 on the first mask and the initial alignment mark W2 on the wafer.
[0098] STPO02 refers to the use of the first detector for lithography alignment, and STPO03 refers to the use of the second detector for lithography alignment. Taking the etching depth of 1000A as an example, in the same lithography alignment process, the two columns of values under M1W1 are the signal strength values of the lithography alignment signals corresponding to the test wafers with wafer numbers 2# and 8# at the alignment position.
[0099] Based on Table 1, the variation curve of the signal intensity value of the lithography alignment signal at the alignment position under different etching depths can be obtained, such as Figures 10 to 13 As shown. Among them, Fig.10 The first detector is used to perform photolithography scanning on the first alignment mark M1 and the initial alignment mark W1, and the signal strength value of the photolithography alignment signal at the alignment position is obtained. Fig.11 The first detector is used to perform photolithography scanning on the first alignment mark M1 and the initial alignment mark W2, and the signal strength value of the photolithography alignment signal at the alignment position is obtained. Fig.12 The second detector is used to perform photolithography scanning on the first alignment mark M1 and the initial alignment mark W1, and the signal strength value of the photolithography alignment signal at the alignment position is obtained. Fig.13 The second detector is used to perform photolithography scanning on the first alignment mark M1 and the initial alignment mark W2, and the signal intensity value of the photolithography alignment signal at the alignment position is obtained.
[0100] from Figures 10 to 13It can be seen that when the etching depth is in the range of 1200A to 1400A, the photolithography alignment signal has the strongest signal strength at the alignment position. This proves that within this etching depth range, the signal strength can be aligned.
[0101] In some embodiments, the semiconductor structure may further include: a second film layer 45 and a third film layer 46. The second film layer 45 covers the surface of the second alignment mark 44 and the surface of the area on the first film layer 43 except the second alignment mark 44. A third alignment mark 46 is formed on the second film layer 45. The third film layer 46 covers the surface of the third alignment mark 46 and the surface of the area on the second film layer 45 except the third alignment mark 46. A fourth alignment mark 48 is formed on the third film layer 46.
[0102] From the above content, it can be seen that according to the solution of the embodiment of the present invention, in the process of forming a semiconductor structure, it is only necessary to monitor the intensity value of the lithography alignment signal at the alignment position to ensure the accuracy of the alignment without the need for SEM analysis, thereby saving the time cost required for monitoring, avoiding a large number of wafers being scrapped due to SEM analysis, and saving laboratory resources to a certain extent.
[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate and a first mask, wherein the semiconductor substrate has an initial alignment mark, and the first mask has a first alignment mark; Performing photolithography scanning on the initial alignment mark and the first alignment mark to obtain an initial photolithography alignment signal; Determining whether the signal strength of the initial photolithography alignment signal at the alignment position is within a preset signal strength strongest range; Based on the judgment result, determine whether to adjust the etching depth of the initial alignment mark to obtain a zero-layer alignment mark, and the signal strength of the photolithography alignment signal corresponding to the zero-layer alignment mark at the alignment position is within the preset signal strength strongest range; Based on the first mask, a first film layer is formed on the zero-layer alignment mark and the semiconductor substrate.
2. The method for forming a semiconductor structure according to claim 1, wherein: The step of determining whether to adjust the etching depth of the initial alignment mark to obtain the zero-layer alignment mark based on the judgment result includes: When the signal strength of the initial photolithography alignment signal at the alignment position is within the preset signal strength strongest interval, taking the initial alignment mark as the zero-layer alignment mark; When the signal strength of the initial photolithography alignment signal at the alignment position is not within the preset signal strength strongest range, continue to etch the groove of the initial alignment mark until the signal strength of the corresponding photolithography alignment signal at the alignment position is within the preset signal strength strongest range after further etching.
3. The method for forming a semiconductor structure according to claim 2, wherein: Continuing to etch the groove of the initial alignment mark until the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest range, comprises: The groove of the initial alignment mark is continuously etched, and the signal intensity of the corresponding photolithography alignment signal at the alignment position after the etching is continued is monitored in real time.
4. The method for forming a semiconductor structure according to claim 2, wherein: Continuing to etch the groove of the initial alignment mark until the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest range, comprises: The signal strength of the corresponding photolithography alignment signal at the alignment position after the continued etching is compared with the preset signal strength strongest interval to determine whether the signal strength of the photolithography alignment signal at the alignment position after the continued etching is within the preset signal strength strongest interval.
5. The method for forming a semiconductor structure according to claim 1, wherein: The signal strength of the initial photolithography alignment signal at the alignment position includes: The initial photolithography alignment signal is subjected to a first operation at an X-direction alignment position and a Y-direction alignment position.
6. The method for forming a semiconductor structure according to claim 5, wherein: The first operation includes: taking an average value.
7. The method for forming a semiconductor structure according to claim 1, wherein: The preset strongest signal strength interval includes: an interval where the maximum signal strength value of the lithography alignment signal is located.
8. The method for forming a semiconductor structure according to claim 1, wherein: The etching depth range of the zero layer alignment mark 41 is [1200A, 1400A].
9. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first film layer on the zero-layer alignment mark and on the surface of the semiconductor substrate based on the first mask includes: forming a first material layer on the zero-layer alignment mark and the semiconductor substrate; Based on the first mask, the first material layer is etched to form a first film layer.
10. A semiconductor structure, characterized in that: Formed by the method for forming a semiconductor structure according to any one of claims 1 to 9.