Memory allocation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a memory allocation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: determining the priority of a first process for the to-be-allocated memory, determining a waterline value corresponding to the priority of the first process according to a predetermined corresponding relation between the priority and the waterline value, and obtaining a first waterline value; and obtaining the current remaining memory, and determining whether to perform fast memory allocation or slow memory allocation on the first process based on the current remaining memory and the first waterline value of the first process. Different allocation waterline values are set for the memory, so that the priority allocation of the memory is realized according to different requirements of the process on the memory allocation speed, the situation of application lagging is reduced, and the situation that the use experience of a user is influenced by slow memory application of the VIP process is reduced to a certain extent.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory allocation method, device, electronic device and readable storage medium. Background Art

[0002] Memory allocation in Linux memory management refers to the process of allocating memory pages from the memory management system to programs. When the buddy system allocates memory, the allocation strategy used is: for all processes, the process that applies for memory resources first can apply for memory faster, reducing the number of times it enters the slow path of memory allocation. However, using the above method, whether it is a process that directly affects application performance or an ordinary process that has little impact on the application, their memory competition method is exactly the same. When there are fewer possible memory resources, the process that directly affects application performance is prone to enter the slow path of memory allocation, resulting in application freezes. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a memory allocation method, device, electronic device and readable storage medium to reduce application freezes. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a memory allocation method, the method comprising:

[0005] For a first process to which memory is to be allocated, determining a priority of the first process to obtain a first priority;

[0006] According to a predetermined correspondence relationship between priorities and waterline values, determining that the first priority corresponds to a waterline value to obtain a first waterline value, wherein in the correspondence relationship, a higher priority corresponds to a higher waterline value;

[0007] Get the current remaining memory;

[0008] When the current remaining memory is not less than the first watermark value, quickly allocating memory to the first process;

[0009] When the current remaining memory is less than the first watermark value, memory is slowly allocated to the first process.

[0010] In one possible embodiment,

[0011] The determining the priority of the first process to obtain a first priority includes:

[0012] Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value;

[0013] According to the attribute information of the first process, a priority of the first process is determined to obtain a first priority.

[0014] In one possible embodiment,

[0015] The attribute information includes a process type;

[0016] The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes:

[0017] When the attribute information of the first process indicates that the first process is a foreground process or a native process, determining that the first process is a VIP process;

[0018] and / or,

[0019] When the attribute information of the first process indicates that the first process is a background process or a visible process, determining that the first process is a common process;

[0020] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0021] In one possible embodiment,

[0022] The attribute information includes an ADJ value;

[0023] The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes:

[0024] When the ADJ value of the first process is greater than a first preset value, the first process is determined to be a common process; when the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process;

[0025] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0026] In one possible embodiment,

[0027] The attribute information includes a Prio value;

[0028] The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes:

[0029] When the Prio value of the first process is less than a second preset value, the first process is determined to be a VIP process; when the Prio value of the first process is not less than the second preset value, the first process is determined to be a common process;

[0030] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0031] In one possible embodiment,

[0032] The fast allocation of memory to the first process includes: selecting a memory of a specified capacity from the remaining memory and allocating the memory to the first process;

[0033] The slow allocation of memory to the first process includes: performing memory recycling; after the memory recycling is completed, selecting a memory of a specified capacity from the remaining memory and allocating it to the first process.

[0034] In a second aspect, an embodiment of the present application provides a memory allocation device, the device comprising:

[0035] A first determining module, configured to determine, for a first process to which memory is to be allocated, a priority of the first process to obtain a first priority;

[0036] A second determination module is used to determine the first priority corresponding to the waterline value to obtain a first waterline value according to a predetermined correspondence relationship between the priority and the waterline value, wherein in the correspondence relationship, a higher priority corresponds to a higher waterline value;

[0037] Acquisition module, used to obtain the current remaining memory;

[0038] A first allocation module, configured to quickly allocate memory to the first process when the current remaining memory is not less than the first watermark value;

[0039] A second allocation module is configured to slowly allocate memory to the first process when the current remaining memory is less than the first watermark value.

[0040] In one possible embodiment,

[0041] The first determining module is specifically used for:

[0042] Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value;

[0043] According to the attribute information of the first process, a priority of the first process is determined to obtain a first priority.

[0044] In one possible embodiment,

[0045] The attribute information includes a process type;

[0046] The first determining module is specifically used for:

[0047] When the attribute information of the first process indicates that the first process is a foreground process or a native process, determining that the first process is a VIP process;

[0048] and / or,

[0049] When the attribute information of the first process indicates that the first process is a background process or a visible process, determining that the first process is a common process;

[0050] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0051] In one possible embodiment,

[0052] The attribute information includes an ADJ value;

[0053] The first determining module is specifically used for:

[0054] When the ADJ value of the first process is greater than a first preset value, the first process is determined to be a common process; when the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process;

[0055] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0056] In one possible embodiment,

[0057] The attribute information includes a Prio value;

[0058] The first determining module is specifically used for:

[0059] When the Prio value of the first process is less than a second preset value, the first process is determined to be a VIP process; when the Prio value of the first process is not less than the second preset value, the first process is determined to be a common process;

[0060] Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

[0061] In one possible embodiment,

[0062] The first allocation module is specifically used to: select a memory of a specified capacity from the remaining memory and allocate it to the first process;

[0063] The second allocation module is specifically used to: perform memory recycling; after the memory recycling is completed, select a memory of a specified capacity from the remaining memory and allocate it to the first process.

[0064] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute any one of the steps described in the first aspect.

[0065] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the methods described in the first aspect.

[0066] Beneficial effects of the embodiments of the present application:

[0067] The memory allocation method, device, electronic device and storage medium provided in the embodiments of the present application determine the priority of the first process for which memory is to be allocated, determine the first waterline value corresponding to the priority of the first process according to the predetermined correspondence between the priority and the waterline value, obtain the current remaining memory, and determine whether to allocate memory to the first process quickly or slowly based on the current remaining memory and the first waterline value of the first process. By setting different allocation waterline values ​​for the memory, the priority allocation of memory is achieved according to the different requirements of the processes for the memory allocation speed, the situation of application jamming is reduced, and the situation where the VIP process affects the user experience due to the slow memory application is reduced to a certain extent.

[0068] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0070] Figure 1-1 A schematic diagram of a memory allocation method in the related art;

[0071] Figure 1-2 A schematic diagram of the first hardware structure of the electronic device provided in this application;

[0072] Figure 1-3 A schematic diagram of a second hardware structure of an electronic device provided in this application;

[0073] Figure 1-4 A third hardware structure diagram of the electronic device provided in this application;

[0074] Figure 2-1 A schematic diagram of a first flow chart of a memory allocation method provided in an embodiment of the present application;

[0075] Figure 2-2 A schematic diagram of process priority provided in an embodiment of the present application;

[0076] Figure 3-1 A schematic diagram of waterline value setting provided in an embodiment of the present application;

[0077] Figure 3-2 A second flow chart of the memory allocation method provided in the embodiment of the present application;

[0078] Figure 3-3 An interactive schematic diagram of a memory allocation method provided in an embodiment of the present application;

[0079] Figure 4 A schematic diagram of the structure of a memory allocation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first instruction and the second instruction are to distinguish different user instructions, and their order is not limited. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order, and the words "first" and "second" do not necessarily limit them to be different.

[0081] It should be noted that, in this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0082] In addition, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0083] Memory allocation in Uinux memory management refers to the process of allocating memory pages from the memory management system to the program. When the buddy system allocates memory, the allocation strategy adopted is: for all processes, the process that applies for memory resources first can apply for memory faster, reducing the number of times it enters the slow path of memory allocation. For details, see Figure 1-1 As shown in the figure, when processes 1 to 5 apply for memory resources, the process that applies for memory resources first can allocate memory quickly.

[0084] The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0085] The present application also provides an electronic device, such as Figure 1-2 As shown, including:

[0086] Memory 01, used for storing computer programs;

[0087] The processor 02 is used to execute the program stored in the memory 01, and implements the following steps:

[0088] For a first process to which memory is to be allocated, determining a priority of the first process to obtain a first priority;

[0089] According to the predetermined correspondence relationship between the priority and the waterline value, determine the waterline value corresponding to the first priority to obtain the first waterline value, wherein in the above correspondence relationship, the higher the priority, the higher the corresponding waterline value;

[0090] Get the current remaining memory;

[0091] When the current remaining memory is not less than the first watermark value, quickly allocating memory to the first process;

[0092] When the current remaining memory is less than the first watermark value, memory is slowly allocated to the first process.

[0093] Furthermore, the electronic device may further include a communication bus and / or a communication interface, and the processor 02, the communication interface, and the memory 01 communicate with each other via the communication bus.

[0094] In a possible embodiment, in order to more clearly describe the electronic device provided by the embodiment of the present application, a possible application scenario of the electronic device provided by the embodiment of the present application is exemplarily described below. It can be understood that the following example is only a possible application scenario of the electronic device provided by the embodiment of the present application. In other possible embodiments, the electronic device provided by the embodiment of the present application can also be applied to other possible application scenarios, and the following example does not impose any limitation on this.

[0095] See also Figure 1-3 , Figure 1-3 The figure shows a hardware structure diagram of an electronic device targeted by the memory allocation method provided in an embodiment of the present application.

[0096] The electronic device includes a processor 110, a transceiver 120, and a display unit 170. The display unit 170 may include a display screen.

[0097] In a possible implementation, the electronic device may further include a memory 130. The processor 110, the transceiver 120, and the memory 130 may communicate with each other through an internal connection path to transmit control and / or data signals. The memory 130 is used to store a computer program, and the processor 110 is used to call and run the computer program from the memory 130.

[0098] In a possible implementation, the electronic device may further include an antenna 140 for transmitting the wireless signal output by the transceiver 120 .

[0099] The processor 110 and the memory 130 may be combined into a processing device, or more commonly, they are independent components, and the processor 110 is used to execute the program code stored in the memory 130 to implement the above functions. In specific implementation, the memory 130 may also be integrated into the processor 110, or may be independent of the processor 110.

[0100] In addition, in order to make the functions of the electronic device more complete, the electronic device may also include one or more of an input unit 160, an audio circuit 180, a camera 190 and a sensor 101, and the audio circuit may also include a speaker 182, a microphone 184, and the like.

[0101] In a possible implementation manner, the electronic device may further include a power supply 150 for providing power to various devices or circuits in the electronic device.

[0102] Understandably, Figure 1-3 The operations and / or functions of each module in the electronic device shown are respectively for implementing the corresponding processes in the following method embodiments. For details, please refer to the description in the following method embodiments, and the detailed description is appropriately omitted here to avoid repetition.

[0103] Understandably, Figure 1-3 The processor 110 in the electronic device shown may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (imagesignalprocessor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and / or a neural-network processing unit (neural-network processing unit, NPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors. A memory can also be set in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory can save instructions or data that the processor 110 has just used or circulated. If the processor 110 needs to use the instruction or data again, it can be directly called from the memory. Repeated access is avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved.

[0104] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0105] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple groups of I2C buses. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 190, etc. through different I2C bus interfaces. For example: the processor 110 may be coupled to the touch sensor 180K through the I2C interface, so that the processor 110 communicates with the touch sensor 180K through the I2C bus interface to realize the touch function of the electronic device.

[0106] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio circuit 180 via the I2S bus to achieve communication between the processor 110 and the audio circuit 180. In some embodiments, the audio circuit 180 can transmit an audio signal to the transceiver 120 via the I2S interface to achieve the function of answering a voice call through a Bluetooth headset.

[0107] The PCM interface can also be used for audio communication, sampling, quantizing and encoding analog signals. In some embodiments, the audio circuit 180 and the transceiver 120 can be coupled via a PCM bus interface. In some embodiments, the audio circuit 180 can also transmit audio signals to the transceiver 120 via the PCM interface to implement the function of answering voice calls through a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0108] The UART interface is a universal serial data bus for asynchronous communication. The bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is generally used to connect the processor 110 and the transceiver 120. For example, the processor 110 communicates with the Bluetooth module in the transceiver 120 through the UART interface to implement the Bluetooth function. In some embodiments, the audio circuit 180 can transmit an audio signal to the transceiver 120 through the UART interface to implement the function of playing music through a Bluetooth headset.

[0109] The MIPI interface can be used to connect the processor 110 with peripheral devices such as the display unit 170 and the camera 190. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 190 communicate via the CSI interface to implement the shooting function of the electronic device. The processor 110 and the display unit 170 communicate via the DSI interface to implement the display function of the electronic device.

[0110] The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 190, the display unit 170, the transceiver 120, the audio circuit 180, the sensor 101, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0111] It is understandable that the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0112] Understandably, Figure 1-3 The power supply 150 shown is used to power the processor 110, the memory 130, the display unit 170, the camera 190, the input unit 160 and the transceiver 120. The antenna 140 is used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antenna. For example, the antenna 140 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0113] The transceiver 120 can provide wireless communication solutions for electronic devices, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The transceiver 120 can be one or more devices integrating at least one communication processing module. The transceiver 120 receives electromagnetic waves via the antenna 140, modulates the frequency of the electromagnetic wave signal and filters it, and sends the processed signal to the processor 110. The transceiver 120 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 140.

[0114] In some embodiments, the antenna 140 and the transceiver 120 of the electronic device are coupled so that the electronic device can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology, etc. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS) and / or satellite based augmentation system (SBAS).

[0115] The electronic device implements the display function through a GPU, a display unit 170, and an application processor. The GPU is a microprocessor for image processing, which connects the display unit 170 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0116] The display unit 170 is used to display images, videos, etc. The display unit 170 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (AMOLED), a flexible light emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light emitting diode (QLED), etc. In some embodiments, the electronic device may include 1 or N display units 170, where N is a positive integer greater than 1.

[0117] The electronic device can realize the shooting function through the ISP, the camera 190, the video codec, the GPU, the display unit 170 and the application processor.

[0118] The ISP is used to process the data fed back by the camera 190. For example, when recording a video, the camera is turned on, and light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image.

[0119] ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, ISP can be set in camera 190. Camera 190 is used to capture static images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to ISP for conversion into a digital image signal. ISP outputs the digital image signal to DSP for processing. DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device may include 1 or N cameras 190, where N is a positive integer greater than 1. The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0120] Video codecs are used to compress or decompress digital videos. Electronic devices can support one or more video codecs. In this way, electronic devices can play or record videos in multiple coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0121] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and continuously self-learn. NPU can realize applications such as intelligent cognition of electronic devices, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0122] The memory 130 can be used to store computer executable program codes, which include instructions. The memory 130 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device (such as audio data, a phone book, etc.), etc. In addition, the memory 130 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device by running instructions stored in the memory 130 and / or instructions stored in a memory provided in the processor.

[0123] The electronic device can implement audio functions such as music playing and recording through the audio circuit 180, the speaker 182, the microphone 184, and the application processor.

[0124] The audio circuit 180 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio circuit 180 can also be used to encode and decode audio signals. In some embodiments, the audio circuit 180 can be arranged in the processor 110, or some functional modules of the audio circuit 180 can be arranged in the processor 110.

[0125] The speaker 182, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device can listen to music or listen to a hands-free call through the speaker 182.

[0126] Microphone 184, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can input the sound signal into microphone 184 by speaking close to microphone 184. The electronic device can be provided with at least one microphone 184. In other embodiments, the electronic device can be provided with two microphones 184, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device can also be provided with three, four or more microphones 184 to realize the collection of sound signals, noise reduction, identification of sound sources, and realization of directional recording function, etc.

[0127] Electronic devices, such as mobile phones, tablet computers, and car computers, usually support three types of audio channels, namely Bluetooth call audio channels, Bluetooth media audio channels, and electronic device audio channels (external audio channels and handset audio channels). Electronic devices can establish connections with Bluetooth devices that have audio playback capabilities, such as Bluetooth headsets and car audio systems, through Bluetooth. After the electronic device is successfully connected to the Bluetooth device, the application running on the electronic device can send audio data to the Bluetooth device through the Bluetooth audio channel for playback.

[0128] Taking the electronic device as a smart phone as an example, the memory allocation method in the embodiment of the present application can be Figure 1-4 The smartphone system architecture shown is implemented in Figure 1-4 , the smartphone system architecture includes a kernel part, a framework layer part and an application layer part; the kernel part includes a driver layer and a real-time operating system, the driver layer includes a GPU (graphics processor), a display driver (specifically an LCD driver in the figure), a TP driver (touch screen driver), buttons, etc.; the real-time operating system includes interrupt management, task scheduling, MEM (memory management); the framework layer includes: UI (user interface), basic system capabilities, underlying software services, hardware service capabilities, etc.; the application layer includes: process applications, display applications, system applications, communication applications, etc. Among them, the process application includes process services, and the process services call the services of the framework layer through the application program interface, thereby realizing the call to the resources of the kernel part, so as to realize the memory allocation method in the embodiment of the present application. In an example, the memory allocation method provided in the embodiment of the present application can be implemented by the buddy system application in the Linux system.

[0129] like Figure 2-1 As shown, it is a first flow chart of the memory allocation method provided in an embodiment of the present application, and the above method includes the following steps S201-S205.

[0130] S201: for a first process to which memory is to be allocated, determining a priority of the first process to obtain a first priority;

[0131] S202: According to a predetermined correspondence relationship between priorities and waterline values, determining the waterline value corresponding to the first priority to obtain a first waterline value, wherein in the above correspondence relationship, a higher priority corresponds to a higher waterline value;

[0132] S203: Get the current remaining memory;

[0133] S204: When the current remaining memory is not less than the first watermark value, quickly allocate memory to the first process;

[0134] S205: When the current remaining memory is less than the first watermark value, slowly allocate memory to the first process.

[0135] The executor of this application can be a mobile phone, tablet, computer, etc., or any other electronic device that can have a memory allocation service.

[0136] In the embodiment of the present application, each process has a corresponding priority. The greater the impact of the process on the application that is currently running or about to run, the higher the priority of the process. For example, the priority of the foreground process is higher than the priority of the background process, and the priority of the system process is higher than the priority of the ordinary process. The number of priority levels can be customized according to actual conditions, and the waterline value corresponding to each priority can be determined according to the actual memory value of the electronic device, which can be an empirical value. The corresponding relationship between the priority and the waterline value when the jamming is the smallest can be obtained through multiple experiments, but it is necessary to ensure that the higher the priority, the higher the corresponding waterline value.

[0137] For the process to be allocated memory (hereinafter referred to as the first process), the priority of the first process can be determined. Exemplarily, the priority of the first process can be determined based on the attribute information of the first process. Among them, the attribute information of the first process may include process type, ADJ value, Prio value, etc. Among them, the process type may include foreground process, background process, visible process, native process, system process, etc., and the ADJ value represents the importance of the process, wherein the higher the ADJ value, the less important the process. Prio value refers to a dynamic priority value, wherein the higher the Prio value, the lower the priority. Exemplarily, the priority of the foreground process is higher than the priority of the background process, the priority of the process with a high ADJ value is lower than the priority of the process with a low ADJ value, and the priority of the process with a high Prio value is lower than the priority of the process with a low Prio value.

[0138] In addition, for each process, the process may also have a fixed priority, that is, a relationship table corresponding to the process priority is maintained, and when a memory application is received from a first process, the priority corresponding to the first process may be determined based on the identification information of the first process. Figure 2-2 As shown, the process priority is divided into 5 levels, namely Level1-Level5. The higher the value, the higher the priority, that is, the priority of Level5 is higher than that of Level4.

[0139] For the sake of clarity of the scheme and layout, a detailed description is given below in conjunction with another embodiment.

[0140] The watermark value is used to determine a threshold for memory allocation speed. For each process, if the current remaining memory is not less than the watermark value of the process, memory is allocated quickly to the process. If the current remaining memory is less than the watermark value of the process, memory is allocated slowly to the process. Figure 3-1 Among them, the priority of the VIP process is higher than that of the ordinary process, and the watermark value of the VIP process is lower than the priority of the ordinary thread.

[0141] The predetermined correspondence between the priority and the watermark value represents the watermark value corresponding to each priority. After the first priority is determined, the watermark value corresponding to the first priority can be determined based on the predetermined correspondence between the priority and the watermark value. Then, the current remaining memory is obtained. If the current remaining memory is not less than the first watermark value, the memory is quickly allocated to the first process. If the current remaining memory is less than the first watermark value, the memory is slowly allocated to the first process.

[0142] For the first process to be allocated memory, determine the priority of the first process, determine the first process's priority corresponding to the waterline value according to the predetermined correspondence between the priority and the waterline value, obtain the first waterline value, obtain the current remaining memory, and determine whether to allocate memory to the first process quickly or slowly based on the current remaining memory and the first waterline value of the first process. By setting different allocation waterline values ​​for memory, the priority allocation of memory is achieved according to the different requirements of the processes for memory allocation speed, which reduces the situation of application freezes and, to a certain extent, reduces the situation where the VIP process affects the user experience due to slow memory application.

[0143] In one possible embodiment,

[0144] The step of determining the priority of the first process to obtain the first priority includes:

[0145] Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value;

[0146] According to the attribute information of the first process, the priority of the first process is determined to obtain a first priority.

[0147] For any process, the process includes attribute information, wherein the attribute information may include at least one of a process type, an ADJ value, and a Prio value. The process type may include a foreground process, a background process, a visible process, a native process, a system process, etc. The ADJ value represents the importance of the process, wherein the higher the ADJ value, the less important the process. The Prio value refers to a dynamic priority value, wherein the higher the Prio value, the lower the priority. Based on the attribute information of the first process, the priority of the first process may be determined to obtain a first priority.

[0148] In one possible embodiment,

[0149] The above attribute information includes process type;

[0150] The step of determining the priority of the first process according to the attribute information of the first process to obtain the first priority includes:

[0151] In a case where the attribute information of the first process indicates that the first process is a foreground process or a native process, determining that the first process is a VIP process;

[0152] and / or,

[0153] In a case where the attribute information of the first process indicates that the first process is a background process or a visible process, determining that the first process is a common process;

[0154] Among them, the watermark value corresponding to the above VIP process is greater than the watermark value corresponding to the above ordinary process.

[0155] The foreground process refers to the process currently displayed on the screen and some system processes. For example, when a program such as a browser is running on a mobile terminal, when the browser interface is displayed in the foreground, the browser belongs to the foreground process, but once you return to the main interface of the mobile phone, the browser becomes a background process.

[0156] The native process refers to the interface process that Java uses to call non-Java code.

[0157] Visible processes are processes that are no longer in the foreground but are still visible to the user, such as the clock process, weather process, news push process, and input method process. Although visible processes are not in the foreground, they are also closely related to actual use.

[0158] Background processes refer to processes that are currently invisible to the user. For example, if I am using a chat software to chat with someone, the chat software is the foreground process at this time, but once I return to the main interface of the phone, the chat software becomes a background process.

[0159] System service processes are processes started by the startService() method, but are not foreground processes or visible processes. For example, playing music or downloading in the background is a system service process.

[0160] When the first process is a foreground process or a native process, the first process is determined to be a VIP process. When the attribute information of the first process indicates that the first process is a background process or a visible process, the first process is determined to be a normal process.

[0161] In one possible embodiment,

[0162] The above attribute information includes ADJ value;

[0163] The step of determining the priority of the first process according to the attribute information of the first process to obtain the first priority includes:

[0164] In the case where the ADJ value of the first process is greater than the first preset value, the first process is determined to be a common process; in the case where the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process;

[0165] Among them, the watermark value corresponding to the above VIP process is greater than the watermark value corresponding to the above ordinary process.

[0166] The ADJ value represents the importance of the process. The ADJ value of the process can be pre-set or adjusted in real time. For details, please refer to the method for determining the ADJ value of the process in the relevant technology. When the ADJ value of the first process is greater than the first preset value, the first process is determined to be an ordinary process; when the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process. The first preset value can be set based on the actual situation. In other words, when the ADJ value is greater than the first preset value, it means that the process is not important, and the process can be treated as an ordinary process. When the ADJ value is not greater than the first preset value, it means that the process is important, and the process can be treated as a VIP process. The priority of the process is determined based on the ADJ value. Important processes can be treated as VIP processes, and unimportant processes can be treated as ordinary processes.

[0167] In one possible embodiment,

[0168] The above attribute information includes Prio value;

[0169] The step of determining the priority of the first process according to the attribute information of the first process to obtain the first priority includes:

[0170] In the case where the Prio value of the first process is less than the second preset value, determine the first process as a VIP process; in the case where the Prio value of the first process is not less than the second preset value, determine the first process as an ordinary process;

[0171] Among them, the waterline value corresponding to the VIP process is greater than the waterline value corresponding to the ordinary process.

[0172] The Prio value refers to the dynamic priority value. Among them, the higher the Prio value, the lower the priority. Among them, the second preset value is determined based on the actual situation. For example, when 0 < Prio < 99, it is a VIP process, and when the Prio value is 100 <= prio <= 139, it is an ordinary process.

[0173] Based on the above embodiments, exemplarily, weighted calculations can be performed on the ADJ value and the Prio value to determine whether the first process is a VIP process or an ordinary process.

[0174] In one possible embodiment,

[0175] The above-mentioned rapid memory allocation for the first process includes: selecting a memory with a specified capacity from the remaining memory and allocating it to the first process;

[0176] The above-mentioned slow memory allocation for the first process includes: performing memory recycling; after the memory recycling is completed, selecting a memory with a specified capacity from the remaining memory and allocating it to the first process.

[0177] When performing rapid memory allocation, it can be directly selecting a memory with a specified capacity from the remaining memory for allocation. Among them, the memory with the specified capacity is not less than the memory applied for by the first process. When performing rapid memory allocation. Then it is necessary to first perform memory recycling. After the memory recycling is completed, select a memory with a specified capacity from the remaining memory and allocate it to the first process. Among them, memory recycling is to recycle the memory space composed of memory pages that have been allocated to threads and are in an occupied state. The specific recycling strategy can be based on the memory page allocation time for recycling, that is, giving priority to recycling the memory space that was allocated first. The longer the memory space has been allocated, the more likely this memory space is idle. In this way, the idle memory space can be recycled again to improve the memory utilization rate.

[0178] Based on the above implementation, see Figure 3-2 , Figure 3-2 This is the second flow diagram of the memory allocation method provided by the embodiments of the present application.

[0179] For each process, the process sends a request for applying for memory to the Buddy system;

[0180] After receiving the memory request from the process, the Buddy system determines the process priority to obtain the first priority of the process.

[0181] According to the predetermined correspondence between the priorities and the waterline values, the waterline value corresponding to the first priority is determined to obtain the first waterline value;

[0182] Based on the current remaining memory and the first watermark value, memory is allocated to the process.

[0183] Specifically, the current remaining memory is obtained; and according to the waterline value and the current remaining memory, it is determined whether to enter the slow path for slow allocation. If yes, the slow path is entered for slow allocation; if not, a different allocation path is executed, that is, the fast path is entered for fast allocation.

[0184] Based on the above implementation, see Figure 3-3 , Figure 3-3 An interactive schematic diagram of the memory allocation method provided in an embodiment of the present application.

[0185] The electronic device includes a priority judgment module, a waterline setting module, a waterline judgment module, and a memory allocation module;

[0186] For the first process to which memory is to be allocated, the priority determination module determines the priority of the first process according to the process type, the ADJ value, and the Prio value to obtain a first priority;

[0187] Then, the priority judgment module sends the obtained first priority to the waterline setting module, and the waterline setting module sets different allocated waterline values ​​according to the priority. Specifically, according to the predetermined correspondence between the priority and the waterline value, the first waterline value corresponding to the first priority is determined to obtain the first waterline value;

[0188] The waterline judgment module obtains the current remaining memory; and judges whether to enter the slow path for slow allocation according to the waterline value and the current remaining memory; and sends the judgment result to the memory allocation module.

[0189] The memory allocation module performs memory allocation based on the judgment result of the waterline judgment module. Specifically, if the slow path is entered for slow allocation, the slow path is entered for slow allocation. If not, a different allocation path is executed, that is, the fast path is entered for fast allocation. After the allocation is completed, the allocated memory page is returned.

[0190] By determining the priority of the first process for which memory is to be allocated, and determining the first process's priority corresponding to the waterline value according to the predetermined correspondence between the priority and the waterline value, the first waterline value is obtained, the current remaining memory is obtained, and based on the current remaining memory and the first waterline value of the first process, it is determined whether to allocate memory to the first process quickly or slowly. By setting different allocation waterline values ​​for memory, the priority allocation of memory is achieved according to the different requirements of the processes for memory allocation speed, the situation of application freeze is reduced, and to a certain extent, the situation in which the VIP process affects the user experience due to slow memory application is reduced.

[0191] Corresponding to the aforementioned memory allocation method, the present application also provides a memory allocation device, such as Figure 4 As shown, the device comprises:

[0192] A first determining module 410 is used to determine the priority of a first process to which memory is to be allocated, and obtain a first priority;

[0193] A second determination module 420 is used to determine the first waterline value corresponding to the first priority according to a predetermined correspondence relationship between the priority and the waterline value, wherein in the above correspondence relationship, the higher the priority, the higher the corresponding waterline value;

[0194] The acquisition module 430 is used to obtain the current remaining memory;

[0195] A first allocation module 440, configured to quickly allocate memory to the first process when the current remaining memory is not less than the first watermark value;

[0196] The second allocation module 450 is used to slowly allocate memory to the first process when the current remaining memory is less than the first waterline value.

[0197] In one possible embodiment,

[0198] The first determining module 410 is specifically used for:

[0199] Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value;

[0200] According to the attribute information of the first process, the priority of the first process is determined to obtain a first priority.

[0201] In one possible embodiment,

[0202] The above attribute information includes process type;

[0203] The first determining module 410 is specifically used for:

[0204] In a case where the attribute information of the first process indicates that the first process is a foreground process or a native process, determining that the first process is a VIP process;

[0205] and / or,

[0206] In a case where the attribute information of the first process indicates that the first process is a background process or a visible process, determining that the first process is a common process;

[0207] Among them, the watermark value corresponding to the above VIP process is greater than the watermark value corresponding to the above ordinary process.

[0208] In one possible embodiment,

[0209] The above attribute information includes ADJ value;

[0210] The first determining module 410 is specifically used for:

[0211] In the case where the ADJ value of the first process is greater than the first preset value, the first process is determined to be a common process; in the case where the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process;

[0212] Among them, the watermark value corresponding to the above VIP process is greater than the watermark value corresponding to the above ordinary process.

[0213] In one possible embodiment,

[0214] The above attribute information includes Prio value;

[0215] The first determining module 410 is specifically used for:

[0216] When the Prio value of the first process is less than the second preset value, the first process is determined to be a VIP process; when the Prio value of the first process is not less than the second preset value, the first process is determined to be a normal process;

[0217] Among them, the watermark value corresponding to the above VIP process is greater than the watermark value corresponding to the above ordinary process.

[0218] In a possible embodiment, the first allocation module 440 is specifically used to: select a memory of a specified capacity from the remaining memory and allocate it to the first process;

[0219] The second allocation module 450 is specifically used to: perform memory recycling; after the memory recycling is completed, select a memory of a specified capacity from the remaining memory and allocate it to the first process.

[0220] In a specific implementation, the present application also provides a computer storage medium, wherein the computer storage medium may store a program, wherein when the program is running, the device where the computer-readable storage medium is located is controlled to perform some or all of the steps in the above embodiment. The storage medium may be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0221] In a specific implementation, an embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above method embodiment.

[0222] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0223] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0224] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0225] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or by other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, compact disc read-only memories (Compact Disc Read Only Memory, CD-ROMs), magneto-optical disks, read-only memories (Read Only Memory, ROM), random access memories (RAM), erasable programmable read-only memories (Erasable Programmable Read Only Memory, EPROM), electrically erasable programmable read-only memories (Electrically Erasable Programmable Read Only Memory, EEPROM), magnetic cards or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0226] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the accompanying drawings of the specification. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0227] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0228] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0229] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A memory allocation method, characterized in that: The method comprises: For a first process to which memory is to be allocated, determining a priority of the first process to obtain a first priority; According to a predetermined correspondence relationship between priorities and waterline values, determining that the first priority corresponds to a waterline value to obtain a first waterline value, wherein in the correspondence relationship, a higher priority corresponds to a higher waterline value; Get the current remaining memory; When the current remaining memory is not less than the first watermark value, quickly allocating memory to the first process; When the current remaining memory is less than the first watermark value, memory is slowly allocated to the first process.

2. The method according to claim 1, characterized in that The determining the priority of the first process to obtain a first priority includes: Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value; According to the attribute information of the first process, a priority of the first process is determined to obtain a first priority.

3. The method according to claim 2, characterized in that The attribute information includes a process type; The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes: When the attribute information of the first process indicates that the first process is a foreground process or a native process, determining that the first process is a VIP process; and / or, When the attribute information of the first process indicates that the first process is a background process or a visible process, determining that the first process is a common process; Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

4. The method according to claim 2, characterized in that: The attribute information includes an ADJ value; The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes: When the ADJ value of the first process is greater than a first preset value, the first process is determined to be a common process; when the ADJ value of the first process is not greater than the first preset value, the first process is determined to be a VIP process; Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

5. The method according to claim 2, characterized in that: The attribute information includes a Prio value; The determining, according to the attribute information of the first process, the priority of the first process to obtain a first priority includes: When the Prio value of the first process is less than a second preset value, the first process is determined to be a VIP process; when the Prio value of the first process is not less than the second preset value, the first process is determined to be a common process; Among them, the watermark value corresponding to the VIP process is greater than the watermark value corresponding to the ordinary process.

6. The method according to claim 1, characterized in that The fast allocation of memory to the first process includes: selecting a memory of a specified capacity from the remaining memory and allocating the memory to the first process; The slow allocation of memory to the first process includes: performing memory recycling; after the memory recycling is completed, selecting a memory of a specified capacity from the remaining memory and allocating it to the first process.

7. A memory allocation device, characterized in that: The device comprises: A first determining module, configured to determine, for a first process to which memory is to be allocated, a priority of the first process to obtain a first priority; A second determination module is used to determine the first priority corresponding to the waterline value to obtain a first waterline value according to a predetermined correspondence relationship between the priority and the waterline value; wherein, in the correspondence relationship, a higher priority corresponds to a higher waterline value; Acquisition module, used to obtain the current remaining memory; A first allocation module, configured to quickly allocate memory to the first process when the current remaining memory is not less than the first watermark value; A second allocation module is configured to slowly allocate memory to the first process when the current remaining memory is less than the first watermark value.

8. The device according to claim 7, characterized in that The first determining module is specifically used for: Acquire attribute information of the first process, wherein the attribute information includes at least one of a process type, an ADJ value, and a Prio value; According to the attribute information of the first process, a priority of the first process is determined to obtain a first priority.

9. An electronic device, characterized in that: The device comprises a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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