Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, a plurality of pixels electrically connected with a pixel circuit are arranged in a display area, and the display area comprises a plurality of first signal ends arranged along a first direction and first signal lines respectively connected with the first signal ends, the first signal end is configured to provide a first power supply voltage signal for the pixel circuit through a first signal line; the first signal line extends along a second direction, and the first direction and the second direction intersect and are parallel to the light emitting surface of the display panel; the first signal ends comprise a first group of signal ends and a second group of signal ends, and the number of the first signal ends included in the second group of signal ends is greater than that of the first signal ends included in the first group of signal ends; in the first direction, the first set of signal terminals is located between the second set of signal terminals and the edge of the display panel. Therefore, the voltage drop of the first power supply voltage signal in the transmission process can be reduced, and the display uniformity can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At this stage, how to improve the uniformity of display brightness of display products and improve the display effect has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to enhance the uniformity of display brightness and improve the display effect.

[0005] In a first aspect, the present disclosure provides a display panel, comprising:

[0006] A display area, wherein a plurality of pixels are arranged in the display area, and the pixels are electrically connected to the pixel circuit;

[0007] a plurality of first signal terminals arranged along a first direction and first signal lines respectively connected to the first signal terminals, wherein the first signal terminals are configured to provide a first power supply voltage signal to the pixel circuit through the first signal lines; the first signal lines extend along a second direction, the first direction intersects with the second direction and are parallel to a light emitting surface of the display panel;

[0008] The first signal end includes a first group of signal ends and a second group of signal ends, the number of the first signal ends included in the second group of signal ends is greater than the number of the first signal ends included in the first group of signal ends; along the first direction, the first group of signal ends is located between the second group of signal ends and the edge of the display panel.

[0009] In a second aspect, based on the same inventive concept, the present disclosure provides a display device, including the display panel provided in the first aspect of the present disclosure.

[0010] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0011] In the present disclosure, a first group of signal terminals and a second group of signal terminals are introduced into a display panel, and both the first group of signal terminals and the second group of signal terminals are used to provide a first power supply voltage signal to a pixel circuit, wherein the number of first signal terminals included in the second group of signal terminals is greater than the number of first signal terminals included in the first group of signal terminals, and each first signal terminal is electrically connected to a different first signal line, and the first power supply voltage signal is provided to pixel circuits in different display areas of the display panel through the first signal line, so that the area near the center line extending along the second direction of the display panel and the area near the edge extending along the second direction of the display panel are both electrically connected to the first signal line. The first signal line connected to the first signal terminal of the first signal terminal and the second signal terminal of the second signal terminal, when providing the first power supply voltage signal to the pixel circuit of the display area, each first signal terminal in the first signal terminal and the second signal terminal group transmits the first power supply voltage signal to the corresponding first signal line. Compared with the method of transmitting the power supply voltage signal only through one first signal terminal, the method of introducing multiple first signal terminals and corresponding multiple first signal lines in the present disclosure is conducive to improving the transmission rate of the first power supply voltage signal and reducing the overall voltage drop of the first power supply voltage signal, thereby helping to weaken or avoid the display unevenness caused by the voltage drop problem of the first power supply voltage signal of the display panel, so as to improve the overall display brightness uniformity of the display panel. Moreover, a smaller number of first signal terminals are set in the first signal terminal group close to the edge, and a larger number of first signal terminals are set in the second signal terminal group away from the edge, so that the first signal terminals can be arranged as evenly as possible along the first direction and transmit the first power supply voltage signal to the corresponding first signal line, thereby helping to reduce the display brightness difference between the display area around the first signal terminal and other display areas, thereby helping to improve the overall display brightness uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 Shown is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 2 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0016] Figure 3Shown Figure 1 A BB cross-sectional view of the provided display panel;

[0017] Figure 4 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0018] Figure 5 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0019] Figure 6 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0020] Figure 7 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0021] Figure 8 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0022] Fig. 9 Said Figure 8 A connection diagram of the first signal line and the first connection line;

[0023] Fig.10 Another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure is shown;

[0024] Fig.11 Said Fig.10 A connection diagram of a first signal line, a first connecting line and a second connecting line;

[0025] Fig.12 The figure shows a relative position relationship diagram of the first signal line and the second signal line in the present disclosure;

[0026] Fig.13 Shown is a relative position relationship diagram of the first signal line, the second signal line and the second connecting line in the present disclosure;

[0027] Fig.14 Another relative position relationship diagram of the first signal line, the second signal line and the second connecting line in the present disclosure is shown;

[0028] Fig.15 Shown is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0029] Fig.16 Shown with Fig.15 A corresponding timing diagram;

[0030] Fig.17 Another schematic diagram of a pixel circuit provided by an embodiment of the present disclosure is shown;

[0031] Fig.18 Shown is a connection diagram of a pulse amplitude modulation circuit and a pulse width modulation circuit in the present disclosure;

[0032] Fig.19 Another connection diagram of the pulse amplitude modulation circuit and the pulse width modulation circuit in the present disclosure is shown;

[0033] Fig. 20 FIG. 1 is another connection diagram of the pulse amplitude modulation circuit and the pulse width modulation circuit in the present disclosure;

[0034] Fig.21 Shown is a connection diagram of a second signal terminal and a first connection portion in a display panel provided by the present disclosure;

[0035] Fig. 22 Shown Figure 2 A CC cross-sectional view of the display panel;

[0036] Fig.23 Shown is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure;

[0037] Fig.24 Shown is another structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0038] Fig.25 Shown is another structural schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] Figure 1 FIG. 1 is a schematic diagram of a structure of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is another schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 3 Shown Figure 1 For a BB cross-sectional view of the provided display panel, please refer to Figures 1 to 3 The present disclosure provides a display panel 100, comprising:

[0042] A display area A, in which a plurality of pixels 21 are arranged, and the pixels 21 are electrically connected to a pixel circuit 20;

[0043] A plurality of first signal terminals 10 arranged along a first direction D1 and first signal lines 11 respectively connected to the first signal terminals 10, wherein the first signal terminals 10 are configured to provide a first power supply voltage signal to the pixel circuit 20 through the first signal lines 11; the first signal lines 11 extend along a second direction D2, the first direction D1 intersects the second direction D2, and are parallel to a light emitting surface of the display panel;

[0044] The first signal terminal 10 includes a first group of signal terminals Z1 and a second group of signal terminals Z2, the number of first signal terminals 10 included in the second group of signal terminals Z2 is greater than the number of first signal terminals 10 included in the first group of signal terminals Z1; along the first direction D1, the first group of signal terminals Z1 is located between the second group of signal terminals Z2 and an edge B1 of the display panel, where the edge B1 refers to an edge of the display panel extending along the second direction D2.

[0045] The pixel mentioned in the present disclosure may be embodied as a light-emitting element, specifically an inorganic light-emitting element (such as Mini LED or Micro LED, etc.) or an organic light-emitting element (such as OLED, etc.). The pixel circuit 20 connected to the pixel may include a plurality of transistors, Figure 3 The film structure shown only shows one transistor in the pixel circuit 20 connected to the same light-emitting element, and does not show other transistors in the pixel circuit 20. The pixel circuit 20 mentioned in the present disclosure can adopt the pixel circuit 20 in the related art, and is not limited to this. Some feasible pixel circuits 20 will be illustrated in the following embodiments. Optionally, the pixels mentioned in the present disclosure and the pixel circuits 20 connected to the pixels are both located in the display area, and the pixel circuits 20 are arranged in a matrix in the display area. Figure 1 The pixel circuit 20 is only schematically shown in a rectangular structure, and the actual outline shape of the pixel circuit 20 and the actual area occupied by the pixel circuit 20 in the display panel are not limited. It should be noted that Figure 1 The light emitting element connected to the pixel circuit 20 is not shown in the figure. The connection relationship between the two can be referred to in Figure 3 and subsequent embodiments.

[0046] The display panel of the present disclosure is provided with a plurality of first signal terminals 10 arranged along a first direction D1, each of which is electrically connected to a first signal line 11, and the first signal terminal 10 can provide a first power supply voltage signal to a pixel circuit 20 through the first signal line 11, so that the pixel circuit 20 generates a driving current for driving the pixel to emit light. In order to realize normal light emission of each pixel in the display panel, the first power supply voltage signal needs to be transmitted to each pixel circuit 20 in the display panel. Since different pixel circuits 20 are distributed at different positions in the display area, when the first power supply voltage signal is transmitted from the first signal terminal 10 to the pixel circuit 20 through the first signal line 11, due to the existence of the impedance of the first signal line 11, the first power supply voltage signal will generate a voltage drop during the transmission process. For this reason, in the related art, the first signal terminal is usually set at the middle position of one side of the display area, and the power supply voltage signal is provided to the entire display area through the first signal terminal located at the middle position of the bottom side of the display area. However, this design method also has the problem that the power supply voltage signal strength near the first signal terminal is large, while the power supply voltage signal in the area far from the first signal terminal is significantly weakened, resulting in the brightness of the display area near the first signal terminal being significantly higher than that of other display areas, which is also not conducive to improving the display brightness uniformity of the display product.

[0047] To this end, the present disclosure introduces a plurality of first signal terminals 10 in the display panel, the first signal terminals 10 include a first group of signal terminals Z1 arranged close to the edge B1 of the display panel along the first direction D1, and a second group of signal terminals Z2 arranged away from the edge B1 of the display panel along the first direction D1, that is, the second group of signal terminals Z2 is located on the side of the first group of signal terminals Z1 toward the center line of the display panel extending along the second direction D2. In other words, the first group of signal terminals Z1 is located on the side of the second group of signal terminals Z2 toward the edge B1 of the display panel extending along the second direction D2. It should be noted that Figure 1 and Figure 2Two different arrangement structures of the first signal terminals 10 and the corresponding first signal lines 11 included in the second group of signal terminals Z2 are illustrated respectively, but the present disclosure is not limited thereto. In the present disclosure, the number of first signal terminals 10 included in the second group of signal terminals Z2 is greater than the number of first signal terminals 10 included in the first group of signal terminals Z1, and each first signal terminal 10 is electrically connected to a different first signal line 11, and the first power supply voltage signal is provided to the pixel circuits 20 in different display areas of the display panel through the first signal line 11. In this way, it is equivalent to introducing the first signal line 11 connected to the first signal terminal 10 in the area near the center line extending along the second direction D2 of the display panel and the area near the edge B1 extending along the second direction D2 of the display panel, and providing the pixel circuits 20 in the display area with the first signal line 11. When the first power supply voltage signal is provided, each first signal terminal 10 in the first group of signal terminals Z1 and the second group of signal terminals Z2 transmits the first power supply voltage signal to the corresponding first signal line 11. Compared with the method of transmitting the power supply voltage signal only through one first signal terminal 10, the method of introducing multiple first signal terminals 10 and corresponding multiple first signal lines 11 in the present disclosure is conducive to improving the transmission rate of the first power supply voltage signal and reducing the overall voltage drop of the first power supply voltage signal, thereby helping to weaken or avoid the display unevenness caused by the voltage drop problem of the first power supply voltage signal of the display panel, so as to improve the overall display brightness uniformity of the display panel. Moreover, a small number of first signal terminals 10 are set in the first group of signal terminals Z1 close to the edge, and a large number of first signal terminals 10 are set in the second group of signal terminals Z2 far from the edge, so that the first signal terminals 10 can be arranged as evenly as possible along the first direction D1 and transmit the first power supply voltage signal to the corresponding first signal line 11, thereby helping to reduce the display brightness difference between the display area around the first signal terminal 10 and other display areas, thereby helping to improve the overall display brightness uniformity of the display panel.

[0048] It should be noted that Figure 1 The scheme that a plurality of pixel circuit columns L are included between two first signal lines 11 corresponding to the second group of signal terminals Z2 is shown. Figure 2 A solution is shown in which no pixel circuit column is included between two first signal lines 11 corresponding to the second group of signal terminals Z2 , but the present disclosure is not limited thereto. Figure 1 and Figure 2 The pixel circuit columns are for illustration only and do not represent the actual number. The number of pixel circuit columns L included between the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2, and the number of pixel circuit columns included between the first signal lines 11 corresponding to the second group of signal terminals Z2 are also for illustration only, and the present disclosure is not limited to this.

[0049] Figure 1 and Figure 2The embodiment shown is only described by taking the display panel including one second group signal terminal Z2 as an example, but does not limit the number of the second group signal terminals Z2 actually included in the display panel. In some other embodiments of the present disclosure, the display panel may also include two or more second groups of signal terminals Z2. For example, please refer to Figure 4 , Figure 4 Another structural schematic diagram of a display panel provided by an embodiment of the present disclosure is shown. In an optional implementation manner of the present disclosure, the number of the second group of signal terminals Z2 is greater than the number of the first group of signal terminals Z1.

[0050] Specifically, this embodiment is described by taking the display panel including two first signal terminals Z1 and three second signal terminals Z2 as an example, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the number of the second signal terminals Z2 may be more than three. In the present disclosure, the two first signal terminals Z1 are respectively located on the side of the second signal terminal Z2 facing the edge B1 of the display panel. Since the number of first signal terminals 10 included in a single second signal terminal group Z2 is greater than the number of first signal terminals 10 included in a single first signal terminal group Z1, and the number of second signal terminals Z2 is greater than the number of first signal terminals Z1, the total number of first signal terminals 10 included in the second signal terminal group Z2 is greater than the total number of first signal terminals 10 included in the first signal terminal group Z1, which is equivalent to introducing a larger number of first signal terminals 10 between the first signal terminals 10 corresponding to the first signal terminal group Z1, and each first signal terminal 10 is connected to the corresponding first signal line 11. The method of providing the first power supply voltage signal to the pixel circuit 20 through a larger number of first signal terminals 10 and the corresponding first signal line 11 is beneficial to improving the transmission efficiency of the first power supply voltage signal and reducing the voltage drop in the transmission process of the first power supply voltage signal, and further helps to weaken or avoid the display unevenness of the display panel caused by the voltage drop problem of the first power supply voltage signal, so it is beneficial to improve the overall display brightness uniformity of the display panel.

[0051] Please continue to refer to Figure 4In an optional embodiment of the present disclosure, the first group of signal terminals Z1 includes one first signal terminal 10, and the second group of signal terminals Z2 includes two first signal terminals 10. Since the first group of signal terminals Z1 is arranged on the side of the second group of signal terminals Z2 facing the edge B1 of the display panel, that is, the first group of signal terminals Z1 is arranged closer to the edge B1 of the display panel, at this time, when one first signal terminal 10 is introduced into a single first group of signal terminals Z1, the requirement of providing the first power supply voltage signal to the pixel circuit 20 in the edge area of ​​the display panel can be met. Considering that more pixel circuits 20 are arranged in the non-edge area of ​​the display area, a single second group signal terminal Z2 is arranged to include two first signal terminals 10, so that the first power supply voltage signal can be provided to more pixel circuits 20 in the non-edge area of ​​the display area. Moreover, by increasing the number of the second group signal terminals Z2, the number of the first signal terminals 10 included in the second group signal terminals Z2 as a whole can be further increased, so that a larger number of first signal terminals 10 can be utilized to provide the first power supply voltage signal to the pixel circuits 20 in the non-edge area, thereby facilitating the improvement of the transmission rate of the first power supply voltage signal provided by each first signal terminal 10 to the pixel circuit 20, reducing the transmission voltage drop of the first power supply voltage signal, and facilitating the weakening or avoiding the display unevenness of the display panel due to the voltage drop problem of the first power supply voltage signal, thereby further facilitating the improvement of the overall display brightness uniformity of the display panel.

[0052] Please continue to refer to Figure 4 In an optional embodiment of the present disclosure, along the first direction D1, the distance S01 between the first signal lines 11 corresponding to the second group of signal terminals Z2 is smaller than the distance S1 between the first signal lines 11 corresponding to the first group of signal terminals Z1 and the first signal lines 11 corresponding to the second group of signal terminals Z2. It should be noted that Figure 4 Only the distance between the first signal lines 11 corresponding to the adjacent first signal terminals Z1 and the second signal terminals Z2 in the display panel is used as an example for explanation, and the distance relationship between the first signal lines 11 corresponding to the non-adjacent first signal terminals Z1 and the second signal terminals Z2 is applicable. The adjacent first signal terminals Z1 and the second signal terminals Z2 refer to that no other second signal terminals Z2 are arranged between the first signal terminals Z1 and the second signal terminals Z2; the non-adjacent first signal terminals Z1 and the second signal terminals Z2 refer to that at least one second signal terminal Z2 is arranged between the first signal terminals Z1 and the second signal terminals Z2.

[0053] This embodiment is described by taking a single first group signal terminal Z1 including one first signal terminal 10 and a single second group signal terminal Z2 including two first signal terminals 10 as an example. The two first signal terminals 10 in the second group signal terminal Z2 are respectively connected to different first signal lines 11, and the distance between the two first signal lines 11 is S01; the distance S1 between the first signal line 11 corresponding to the first group signal terminal Z1 and the first signal line 11 corresponding to the second group signal terminal Z2 can be regarded as the distance between the first signal line 11 corresponding to the first signal terminal 10 and the first signal line 11 in the second group signal terminal Z2 that is closer to the first group signal terminal Z1. In this embodiment, S01<S1 is set, which is equivalent to arranging the first signal lines 11 corresponding to the second group of signal terminals Z2 more densely, that is, the first signal lines 11 that provide the first power supply voltage signal to the pixel circuits 20 in the non-edge area are arranged more densely. Since the number of pixel circuits 20 in the non-edge area is large, when the first power supply voltage signal is provided to this part of the pixel circuits 20 through the first signal lines 11 arranged more densely, it is beneficial to improve the transmission rate of the first power supply voltage signal transmitted to this part of the pixel circuits 20, thereby helping to reduce the voltage drop of the first power supply voltage signal, so that the first power supply voltage signal provided to each pixel circuit 20 meets the preset requirements, and thus helps to improve the uniformity of the overall display brightness.

[0054] Optionally, refer to Figure 4 The display panel includes two first signal terminals Z1, and the first signal terminals Z1 are located between the edge B1 and the second signal terminals Z2 of the display panel. The first signal terminals Z1 are located in the area near the left edge and the right edge of the display panel, and the corresponding first signal lines 11 can also be set in the area near the left edge and the right edge of the display panel. In this way, the first signal terminals Z1 and the corresponding first signal lines 11 can provide the first power supply voltage signal to the pixel circuit 20 near the edge area of ​​the display panel, thereby meeting the demand for the first power supply voltage signal in the display area near the edge area of ​​the display panel. Moreover, the first signal terminals Z1 and the second signal terminals Z2 provide the first power supply voltage signal to the edge area and the non-edge area of ​​the display area respectively, which is conducive to reducing the transmission voltage drop of the first power supply voltage signal and improving the uniformity of the overall display brightness of the display panel.

[0055] Please continue to refer to Figure 4The first group of signal terminals Z1 includes one first signal terminal 10 , and the second group of signal terminals Z2 includes two first signal terminals 10 , and each first signal terminal 10 is electrically connected to a first signal line 11 . In this way, the display panel can be divided into at least two sub-display areas A0 arranged along the first direction D1 through the first signal lines corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2. The first signal line 11 connected to the first signal terminal 10 in the first group of signal terminals Z1 is located between the edge of the display panel extending along the second direction D2 and the pixel circuit column adjacent to the edge, and the first signal line 11 connected to the two first signal terminals 10 in the second group of signal terminals Z2 is located between two adjacent sub-display areas A0. This arrangement of the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 divides the display panel into multiple sub-display areas A0 arranged along the first direction D1, and the more the number of sub-display areas A0 is, the fewer the number of pixel circuit columns in the sub-display area A0 is, and the smaller the distance between the pixel circuit in the pixel circuit column and the first signal line 11 closest to it is, which is more conducive to improving the transmission rate of the first power supply voltage signal and reducing the transmission voltage drop of the first power supply voltage signal, so it is beneficial to improving the overall display brightness uniformity of the display panel.

[0056] Optionally, when the second group of signal terminals Z2 includes two first signal terminals 10, the first signal lines 11 corresponding to the two first signal terminals 10 in the second group of signal terminals Z2 do not include pixel circuits 20, that is, the two first signal lines 11 corresponding to the same second group of signal terminals Z2 are located between two adjacent pixel circuit columns. In this way, the display panel can be divided into a plurality of sub-display areas A0 by the first signal lines 11 corresponding to the second group of signal terminals Z2, which is beneficial to reducing the distance between the pixel circuits in each pixel circuit column and the first signal line 11 closest thereto, effectively reducing the number of pixel circuit columns corresponding to a single first signal line 11, and is beneficial to reducing the load of the first signal line 11, and improving the rate of the first power supply voltage signal transmitted by the first signal line 11, so it is beneficial to reduce the voltage drop of the first power supply voltage signal and improve the overall display brightness uniformity of the display panel.

[0057] Please refer to Figure 2 and Figure 4 In an optional implementation of the present disclosure, along the first direction D1, the minimum distance between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 is S1, the width of the display panel along the first direction D1 is S0, S1 / S0≤1 / 2. Optionally, in the implementation of the present disclosure, the first signal line 11 extends along the second direction D2 and is directly connected to the first signal terminal 10.

[0058] The minimum distance S1 refers to the distance between the first signal line 11 in the first signal line 11 corresponding to the second signal terminal Z2 and the first signal line 11 in the first signal terminal Z1. Figure 2 The distance between the first signal line 11-1 corresponding to the first group of signal terminals Z1 and the first signal line 11-2 corresponding to the second group of signal terminals Z2. In this embodiment, it is set that S1 / S0≤1 / 2, that is, 2×S1≤S0, that is, among the first signal lines 11 corresponding to the second group of signal terminals Z2, at least one first signal line 11 is located between the center line of the display panel extending along the second direction D2 and the first signal line 11 of the first group of signal terminals Z1. In other words, the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 are arranged in the left and right half-screen areas of the display panel. These first signal lines 11 can be used to provide the first power supply voltage signal to the pixel circuit 20 of the corresponding half-screen area, respectively, so as to help improve the transmission rate of the first power supply voltage signal in the two half-screen areas of the display panel, reduce the voltage drop of the first power supply voltage signal to improve the overall display brightness uniformity of the display panel. It should be noted that the center line of the display panel extending along the second direction D2 is a central axis passing through the center point of the display panel and extending along the second direction D2. It is a virtual line, not a specific structure. The center line can be used to divide the display panel into two areas of equal area.

[0059] Figure 5 FIG. 1 is another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure, Figure 1 , Figure 2 and Figure 4 The difference is that the number of the second group of signal terminals Z2 is different. Figure 5 In the embodiment shown, the number of the second group of signal terminals Z2 is greater than Figure 1 , Figure 2 and Figure 4 The number of the second group of signal terminals Z2 in the embodiment shown. Figure 5 In an optional embodiment of the present disclosure, along the first direction D1, the minimum distance between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 is S1, and the width of the display panel along the first direction D1 is S0, S1 / S0≤1 / 10.

[0060] The minimum distance S1 refers to the distance between the first signal line 11 in the first signal line 11 corresponding to the second signal terminal Z2 and the first signal line 11 in the first signal terminal Z1. Figure 5The distance between the first signal line 11-1 corresponding to the first group of signal terminals Z1 and the first signal line 11-3 corresponding to the second group of signal terminals Z2. In this embodiment, S1 / S0≤1 / 10, that is, 10×S1≤S0.

[0061] When 10×S1=S0, it can be regarded as using the first signal lines 11 corresponding to the first signal terminals Z1 and the second signal terminals Z2 to approximately evenly divide the display area in the display panel into 10 sub-display areas A0 arranged along the first direction D1, and each display area has a corresponding first signal line 11 to provide the first power supply voltage signal to the pixel circuit 20 therein. When a single second signal terminal Z2 includes two first signal terminals 10, and each first signal terminal 10 corresponds to a first signal line 11, it is equivalent to being able to set two first signal lines 11 for each of the 10 sub-display areas A0, and the two first signal lines 11 send the first power supply voltage signal to the sub-display area A0. The number of pixel circuits 20 included in a single sub-display area A0 is relatively small, and the first power supply voltage signal is provided to these smaller number of pixel circuits 20 through two first signal lines 11, which is more conducive to improving the transmission rate of the first power supply voltage signal and reducing the voltage difference of the first power supply voltage signal between the area close to the first signal terminal 10 and the area far from the first signal terminal 10 in the sub-display area A0, thereby facilitating improving the display brightness uniformity of different areas in the sub-display area A0, and further facilitating improving the display brightness uniformity of the entire display panel.

[0062] When 10×S1<S0, it is equivalent to using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to divide the display area into more than 10 sub-display areas A0, and when the second group of signal terminals Z2 includes two first signal terminals 10, it can still ensure that each sub-display area A0 has two first signal lines 11 corresponding to it and provides the first power supply voltage signal thereto, and the number of pixel circuits 20 in the sub-display area A0 corresponding to the two first signal lines 11 will be smaller, which is more conducive to improving the transmission rate of the first power supply voltage signal and reducing the voltage difference of the first power supply voltage signal received by different areas in the sub-display area A0, thereby being more conducive to improving the display brightness uniformity of the sub-display area A0, and further being more conducive to improving the overall display brightness uniformity of the display panel.

[0063] Please continue to refer to Figure 4 and Figure 5 In an optional embodiment of the present disclosure, the display panel includes at least two groups of second signal terminals Z2, and along the first direction D1, the minimum distance between the first signal lines 11 corresponding to two adjacent groups of second signal terminals Z2 is S2, and the minimum distance between the first signal line 11 corresponding to the first signal terminal Z1 and the first signal line 11 corresponding to the second signal terminal Z2 is S1, and S2=S1.

[0064] Specifically, Figure 4 The embodiment shown shows a solution in which the display panel includes three groups of second signal terminals Z2. Figure 5 The embodiment shown shows a solution that the display panel includes nine groups of second signal terminals Z2, but does not limit the number of second signal terminals Z2 actually included in the display panel. Among them, along the first direction D1, the minimum distance between the first signal line 11 corresponding to the first signal terminal Z1 and the first signal line 11 corresponding to the second signal terminal Z2 is S1, and the minimum distance S1 refers to the distance between the first signal line 11 closest to the first signal line 11 corresponding to the first signal terminal Z1 among the first signal lines 11 corresponding to the second signal terminal Z2 and the first signal line 11 in the first signal terminal Z1. Along the first direction D1, the minimum distance between the first signal lines 11 corresponding to two adjacent groups of second signal terminals Z2 is S2, and the minimum distance S2 refers to the distance between the two first signal lines 11 corresponding to different second signal terminals Z2 and the closest to each other among the first signal lines 11 corresponding to the adjacent second signal terminals Z2. In this embodiment, S1=S2 is set, which is equivalent to the number of pixel circuit columns included between the first signal lines 11 corresponding to the first signal terminal Z1 and the second signal terminal Z2 adjacent thereto, being the same as the number of pixel circuit columns included between the first signal lines 11 corresponding to the two adjacent second signal terminals Z2, that is, the display panel is divided into a plurality of sub-display areas A0 by a plurality of first signal lines 11, the number of pixel circuit columns included in each sub-display area A0 is the same, and each sub-display area A0 corresponds to two first signal lines 11 transmitting the first power supply voltage signal to the pixel circuit 20 in the sub-display area A0. In this way, the transmission rate of the first power supply voltage signal is improved, and the transmission rates of the first power supply voltage signals in different sub-display areas A0 will be consistent or nearly consistent, which is helpful to reduce the display brightness difference corresponding to different sub-display areas A0 and improve the overall display brightness uniformity of the display panel.

[0065] Optionally, the distances between adjacent second-group signal terminals Z2 are equal. It should be noted that the equal distances mentioned in the present disclosure refer to distance values ​​being equal within the allowable range of error (±5%). The distance between adjacent second-group signal terminals Z2 mentioned in this embodiment can be regarded as the distance between two first signal terminals 10 that are closer in the adjacent second-group signal terminals Z2, that is, the width of the interval between two adjacent second-group signal terminals Z2. In this embodiment, the two first signal terminals 10 corresponding to the second-group signal terminals Z2 are located between two adjacent sub-display areas A0, and the corresponding two first signal lines 11 are also located between two adjacent sub-display areas A0. When the distances between adjacent second-group signal terminals Z2 are equal, the widths of the multiple sub-display areas A0 formed by the first signal lines 11 corresponding to different second-group signal terminals Z2 will be equal, that is, the number of pixel circuit columns contained in each sub-display area A0 is equal. In this way, the display panel is equally divided into multiple sub-display areas A0 and each sub-display area A0 has two corresponding first signal lines 11 to provide it with the first power supply voltage signal, which is beneficial to reducing the load of each first signal line 11, and the load of each first signal line 11 is the same or nearly the same, so it is beneficial to reduce the voltage drop of the first power supply voltage signal transmitted on the first signal line 11, and further helps to improve the overall display brightness uniformity of the display panel.

[0066] Please refer to Figure 4 and Figure 5In an optional embodiment of the present disclosure, the first signal line 11 connected to the first group of signal terminals Z1 is located between the first edge B1 of the display panel and the first signal line 11 connected to the second group of signal terminals Z2, and the pixel circuit 20 is not included between the first signal line 11 and the first edge, and the first edge B1 extends along the second direction D2. That is to say, in this embodiment, the first signal line 11 corresponding to the first group of signal terminals Z1 is located at the periphery of the pixel circuit column along the first direction D1, and the pixel circuit column is located on one side of the first signal line 11 along the first direction D1, and the other side is the first edge B1 of the display panel. In this way, the first power supply voltage signal transmitted by the first signal line 11 corresponding to the first group of signal terminals Z1 can be provided to the pixel column adjacent to the first edge B1 at the first time, avoiding the problem of uneven brightness of the edge and non-edge brightness of the display area caused by excessive voltage drop of the first power supply voltage signal transmitted to the pixel circuit column located in the edge area. In addition, when the first signal line 11 corresponding to the first group of signal terminals Z1 is set to be adjacent to the first edge B1 of the display panel, the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 can be used to divide the display area into multiple sub-display areas A0, and each sub-display area A0 has two corresponding first signal lines 11 to transmit the first power supply voltage signal thereto, which is more conducive to reducing the transmission voltage drop of the first power supply voltage signal and improving the overall display brightness uniformity of the display panel.

[0067] Please continue to refer to Figure 2 , Figure 4 and Figure 5 In an optional embodiment of the present disclosure, the display panel includes N1 pixel circuit columns L arranged along the first direction D1, and the minimum number of pixel circuit columns L included between the first signal line 11 connected to the first group of signal terminals Z1 and the first signal line 11 connected to the second group of signal terminals Z2 is N2, and N2 / N1≤1 / 2.

[0068] It should be noted that the pixel circuit columns L in the drawings of the present disclosure are for illustration only and do not limit the number of pixel circuit columns L actually included in the display panel. In this embodiment, the minimum number N2 of pixel circuit columns L included between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 refers to the number of pixel circuit columns L included between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 that is closest to the first signal line 11 and corresponds to the second group of signal terminals Z2. In the present embodiment, N2 / N1≤1 / 2, that is, 2×N2≤N1. When 2×N2=N1, it is equivalent to using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to divide the display area into two sub-display areas A0. The number of pixel circuit columns L contained in the two sub-display areas A0 is the same, and each sub-display area A0 corresponds to two first signal lines 11. The two first signal lines 11 are located on both sides of the corresponding sub-display area A0 and provide the first power supply voltage signal to the sub-display area A0. This is beneficial to balancing the loads of different first signal lines 11, reducing the voltage drop of the first power supply voltage signal transmission, and improving the display brightness uniformity of the display panel. When 2×N2<N1, it is equivalent to using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to divide the display area into more than two sub-display areas A0, each sub-display area A0 corresponds to two first signal lines 11, and the number of pixel circuit columns L contained in each sub-display area A0 is relatively small. Using two first signal lines 11 to provide the first power supply voltage signal to the smaller number of pixel circuit columns L is beneficial to further improve the transmission rate of the first power supply voltage signal line, reduce the voltage drop of the first power supply voltage signal, and improve the overall display brightness uniformity of the display panel.

[0069] Please refer to Figure 5 In an optional embodiment of the present disclosure, the display panel includes N1 pixel circuit columns L arranged along the first direction D1, and the minimum number of pixel circuit columns L included between the first signal line 11 connected to the first group of signal terminals Z1 and the first signal line 11 connected to the second group of signal terminals Z2 is N2, and N2 / N1≤1 / 10.

[0070] It should be noted that Figure 5The number of pixel circuit columns L arranged between the two first signal lines 11 is only for illustration and does not represent the actual number. In this embodiment, the minimum number N2 of pixel circuit columns L included between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 corresponding to the second group of signal terminals Z2 refers to the number of pixel circuit columns L included between the first signal line 11 corresponding to the first group of signal terminals Z1 and the first signal line 11 closest to the first signal line 11 and corresponding to the second group of signal terminals Z2. In this embodiment, N2 / N1≤1 / 10, that is, 10×N2≤N1. When 10×N2=N1, it is equivalent to using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to equally divide the display area into 10 sub-display areas A0 arranged along the first direction D1. The number of pixel circuit columns L included in each sub-display area A0 is the same, and each sub-display area A0 has two first signal lines 11 corresponding to it. When the display area is equally divided into 10 sub-display areas A0, the number of pixel circuit columns L contained in each sub-display area A0 is further reduced. When the first power supply voltage signal is provided to the sub-display area A0 with fewer pixel circuit columns L through two first signal lines 11, the number of pixel circuit columns L connected to each first signal line 11 will be smaller, which is equivalent to reducing the load of the first signal line 11, which is more conducive to improving the transmission rate of the first power supply voltage signal and reducing the voltage difference of the first power supply voltage signal between the area close to the first signal terminal 10 and the area far from the first signal terminal 10 in the sub-display area A0, thereby helping to improve the display brightness uniformity of different areas in the sub-display area A0, and further helping to improve the display brightness uniformity of the entire display panel.

[0071] When 10×N2<N1, it is equivalent to using the first signal line 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to divide the display area into more than 10 sub-display areas A0. The more sub-display areas A0 formed by the division, the fewer pixel circuit columns L contained in each sub-display area A0 will be, the fewer pixel circuit columns L driven by each first signal line 11 will be, and the smaller the load of the first signal line 11 will be. Therefore, the voltage drop of the first power supply voltage signal transmitted through the first signal line 11 will be smaller, which is more conducive to weakening or avoiding the problem of uneven display brightness caused by the large voltage drop of the first power supply voltage signal, thereby helping to improve the overall display brightness uniformity of the display panel. Moreover, when the second group of signal terminals Z2 includes two first signal terminals 10, it can still ensure that each sub-display area A0 has two first signal lines 11 corresponding to it and provides the first power supply voltage signal thereto, and the number of pixel circuits 20 in the sub-display area A0 corresponding to the two first signal lines 11 will be smaller, which is more conducive to improving the transmission rate of the first power supply voltage signal and reducing the voltage difference of the first power supply voltage signal received by different areas in the sub-display area A0, thereby being more conducive to improving the display brightness uniformity of the sub-display area A0, and further being more conducive to improving the overall display brightness uniformity of the display panel.

[0072] Please continue to refer to Figure 4 and Figure 5 In an optional embodiment of the present disclosure, the display panel includes a plurality of pixel circuit columns L arranged along a first direction D1, and the display panel includes at least two groups of second signal terminals Z2; along the first direction D1, in adjacent first signal terminals Z1 and second signal terminals Z2, the minimum number of pixel circuit columns L included between the first signal line 11 connected to the first signal terminal Z1 and the first signal line 11 connected to the second signal terminal Z2 is n1; in adjacent second signal terminals Z2, the number of pixel circuit columns L included between the first signal lines 11 respectively connected to the two groups of second signal terminals Z2 is n2, and n1=n2.

[0073] It should be noted that the pixel circuit columns L in the drawings of the present disclosure are only for illustration and do not limit the number of pixel circuit columns L actually included in the display panel. In this embodiment, the minimum number n1 refers to the number of pixel circuit columns L included between the first signal lines 11 corresponding to the adjacent first group of signal terminals Z1 and the second group of signal terminals Z2, wherein along the first direction D1, if no other second group of signal terminals Z2 are provided between the first group of signal terminals Z1 and the second group of signal terminals Z2, the two can be considered to be adjacent. Along the first direction D1, if no other second group of signal terminals Z2 are introduced between the two second group of signal terminals Z2, the two second group of signal terminals Z2 can be considered to be adjacent. In the present embodiment, the number n1 of pixel circuit columns L between the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 adjacent thereto is the same as the number of pixel circuit columns L between the first signal lines 11 corresponding to two adjacent second group of signal terminals Z2. This is equivalent to using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 to divide the display area into a plurality of sub-display areas A0 arranged along the first direction D1, and the number of pixel circuit columns L contained in each sub-display area A0 is equal, and each sub-display area A0 has two first signal lines 11 corresponding thereto, which is beneficial to improving the transmission rate of the first power supply voltage signal and reducing the voltage difference of the first power supply voltage signal received by different areas in the sub-display area A0, thereby being more beneficial to improving the display brightness uniformity of the sub-display area A0, and further being more beneficial to improving the overall display brightness uniformity of the display panel.

[0074] Figure 1 The embodiment shown shows a scheme in which a pixel circuit column L is included between two first signal lines 11 corresponding to the second group of signal terminals Z2. Figure 4 and Figure 5 The embodiment shows a solution in which the two first signal lines 11 corresponding to the second group of signal terminals Z2 do not include a pixel circuit column. Figure 4 and Figure 5In an optional embodiment of the present disclosure, in the second group of signal terminals Z2, the first signal lines 11 connected to at least two first signal terminals 10 do not include a pixel circuit 20, that is, the first signal lines 11 corresponding to the two first signal terminals 10 in the second group of signal terminals Z2 are located between two adjacent pixel circuit columns L. In this way, the display area can be divided into at least two sub-display areas A0 arranged along the first direction D1 through the first signal lines 11, and the two first signal lines 11 in the same second group of signal terminals Z2 can correspond to two adjacent sub-display areas A0, respectively, and provide the first power supply voltage signal to the adjacent sub-display areas A0, respectively. In this way, each sub-display area A0 has two first signal lines 11 corresponding to it and provides the first power supply voltage signal thereto, which is beneficial to reducing the load of a single first signal line 11 and improving the transmission rate of the first power supply voltage signal, thereby helping to reduce the voltage drop of the first power supply voltage signal and improving the overall display brightness uniformity of the display panel.

[0075] Figure 6 FIG. 1 is another schematic diagram of the structure of the display panel provided by the embodiment of the present disclosure, Figure 4 and Figure 5 The difference between the embodiments shown is that the arrangement of the first signal lines 11 corresponding to the first signal terminals 10 in the same second group of signal terminals Z2 is different. Figure 6 In an optional implementation of the present disclosure, in the second group of signal terminals Z2, a pixel circuit 20 is included between the first signal lines 11 connected to at least two first signal terminals 10.

[0076] Specifically, Figure 6 The embodiment shows a solution in which the display panel includes four second signal groups Z2, and each second signal group Z2 includes two first signal groups 10, but the present disclosure is not limited thereto. In the present embodiment, at least one pixel circuit column L is included between two first signal lines 11 corresponding to the same second signal group Z2, and the first signal lines 11 do not appear in pairs in the interval between two adjacent pixel circuit columns L. At this time, a single first signal line 11 can simultaneously provide a first power supply voltage signal to the pixel circuits 20 in the display area located on both sides thereof. Optionally, the number of pixel circuit columns L included between two first signal lines 11 corresponding to the same second signal group Z2, the minimum number of pixel circuit columns L included between first signal lines 11 corresponding to adjacent second signal groups Z2, and the minimum number of pixel circuit columns L included between the first signal group Z1 and the first signal line 11 corresponding to the second signal group Z2 adjacent thereto are all the same, for example Figure 6The above numbers are all 2. In this way, the first signal lines 11 are evenly arranged in the display panel, and the first signal terminals 10 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 can be arranged as evenly as possible in the display panel. When the first power supply voltage signal is provided to the pixel circuit columns L in different areas of the display panel through the evenly arranged first signal terminals 10 and the evenly arranged first signal lines 11, it is beneficial to improve the transmission rate of the first power supply voltage signal and reduce the voltage drop in the transmission process of the first power supply voltage signal, so it is also beneficial to improve the display brightness uniformity of the display panel.

[0077] Please continue to refer to Figure 5 In an optional embodiment of the present disclosure, the second group of signal terminals Z2 includes two first signal terminals 10, and along the first direction D1, a distance S01 between the first signal lines 11 connected to the two first signal terminals 10 in the second group of signal terminals Z2 is less than 625 μm.

[0078] In the manufacturing process of the display panel, two adjacent pixel circuit columns L are usually separated by a gap. To avoid short circuits between adjacent pixel circuit columns L, the width of the gap is set to be greater than or equal to 625 μm. To improve the screen-to-body ratio of the display panel, the width of the gap can be set to be equal to 625 μm. In the present disclosure, when the second group of signal terminals Z2 includes two first signal terminals 10, the first signal line 11 connected to the first signal terminal 10 is set in the gap between the pixel circuit columns L. In this embodiment, the distance between the two first signal lines 11 corresponding to the two first signal terminals 10 is limited to less than 625 μm, which is equivalent to setting the first signal line 11 connected to the two first signal terminals 10 in the same second group of signal terminals Z2 in the same pixel column gap, that is, in the second group of signal terminals Z2, the first signal lines 11 corresponding to the two first signal terminals 10 do not include the pixel circuit 20. In this way, the display panel can be divided into multiple sub-display areas A0 through the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2. Each sub-display area A0 has two first signal lines 11 corresponding to it and provides the first power supply voltage signal thereto. In other words, each sub-display area A0 has an exclusive first signal line 11 to provide the first power supply voltage signal thereto. This effectively improves the rate at which the first signal line 11 provides the first power supply voltage signal to the corresponding sub-display area A0, which is beneficial to reducing the transmission voltage drop of the first power supply voltage signal, and further helps to weaken or avoid the display unevenness of the display panel caused by the voltage drop problem of the first power supply voltage signal, so it is beneficial to improve the overall display brightness uniformity of the display panel.

[0079] Optionally, refer to Figure 5, the display panel includes two first signal terminals Z1, and the first signal terminals Z1 are located between the edge B1 and the second signal terminals Z2 of the display panel. That is to say, the first signal terminals Z1 are located in the area close to the left edge and the right edge of the display panel, and the corresponding first signal lines 11 can also be set in the area close to the left edge and the right edge of the display panel. In this way, the first signal terminals Z1 and the corresponding first signal lines 11 can provide the first power supply voltage signal to the pixel circuit 20 close to the edge area of ​​the display panel, thereby meeting the demand for the first power supply voltage signal in the display area close to the edge area of ​​the display panel. Moreover, the first signal terminals Z1 and the second signal terminals Z2 provide the first power supply voltage signal to the edge area and the non-edge area of ​​the display area respectively, which is conducive to reducing the transmission voltage drop of the first power supply voltage signal and improving the uniformity of the overall display brightness of the display panel.

[0080] Please continue to refer to Figure 5 Optionally, the first group of signal terminals Z1 includes one first signal terminal 10 , and the second group of signal terminals Z2 includes two first signal terminals 10 , and each first signal terminal 10 is electrically connected to one first signal line 11 . The first signal line 11 connected to the first signal terminal 10 in the first group of signal terminals Z1 is located between the edge of the display panel extending along the second direction D2 and the pixel circuit column adjacent to the edge, and the first signal line 11 connected to the two first signal terminals 10 in the second group of signal terminals Z2 is located between two adjacent sub-display areas A0. This arrangement of the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 divides the display panel into multiple sub-display areas A0 arranged along the first direction D1, and each sub-display area A0 corresponds to two first signal lines 11 to provide the first power supply voltage signal thereto, and the first signal lines 11 corresponding to each sub-display area A0 are different, which is beneficial to reducing the number of pixel circuit columns corresponding to each first signal line 11 and reducing the load of the first signal line 11, thereby facilitating the improvement of the transmission rate of the first power supply voltage signal line and reducing the transmission voltage drop of the first power supply voltage signal, thereby facilitating the improvement of the overall display brightness uniformity of the display panel.

[0081] Please continue to refer to Figure 4 and Figure 5In an optional embodiment of the present disclosure, the number of the second group of signal terminals Z2 is Q, Q≥3, and Q is an odd number. Specifically, this embodiment shows a scheme in which two first group of signal terminals Z1 are introduced into the display panel and the first signal lines 11 connected to the first group of signal terminals Z1 are respectively adjacent to two edges of the display panel extending along the second direction D2. Among them, the number of the second group of signal terminals Z2 is greater than the number of the first group of signal terminals Z1, and the number of the second group of signal terminals Z2 is an odd number greater than or equal to 3. Optionally, the two first signal lines 11 corresponding to the same second group of signal terminals Z2 are located in the same pixel column interval. In this way, the display area is divided into an even number of sub-display areas A0 using the first signal lines 11 in the first group of signal terminals Z1 and the second group of signal terminals Z2. When Q=3, the number of sub-display areas A0 formed by division is 4, and when Q>3, the number of sub-display areas A0 formed by division is an even number greater than 4. In this embodiment, each sub-display area A0 has two exclusive first signal lines 11 to provide it with a first power supply voltage signal, which effectively improves the transmission rate of the first power supply voltage signal in each sub-display area A0, helps to reduce the voltage drop of the first power supply voltage signal, and therefore helps to improve the overall display brightness uniformity of the display panel.

[0082] Optionally, the number Q of the second group of signal terminals Z2 included in the display panel is 9. When Q is 9, please refer to Figure 5 , which is equivalent to dividing the display panel into 10 sub-display areas A0 arranged along the first direction D1. The more sub-display areas A0 are formed by dividing the display panel using the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2, the fewer pixel circuit columns each sub-display area A0 will contain, the fewer pixel circuit columns driven by each first signal line 11 will be, the smaller the load of the first signal line 11 will be, and thus the smaller the voltage drop of the first power supply voltage signal transmitted through the first signal line 11 will be, which is more conducive to weakening or avoiding the problem of uneven display brightness caused by the large voltage drop of the first power supply voltage signal, thereby helping to improve the overall display brightness uniformity of the display panel.

[0083] Figure 7 FIG. 1 is another schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure, which differs from the above-mentioned embodiment in that at least the number of the second group of signal terminals Z2 included in the display panel is different and the number of pixel circuit columns included in the sub-display area A0 is different. Figure 7In an optional embodiment of the present disclosure, the display area includes N sub-display areas A0 arranged along the first direction D1 and having equal widths, and the second group of signal terminals Z2 is located between the nth sub-display area A0 and the n+1th sub-display area A0, wherein 1≤n≤N-1. It should be noted that the equal width mentioned in the present disclosure refers to the width values ​​being equal within the allowable range of error (±5%).

[0084] Specifically, the present embodiment divides the display area into N sub-display areas A0 arranged along the first direction D1, and the widths of the sub-display areas A0 are equal, that is, the number of pixel circuit columns contained in each sub-display area A0 is the same, which is equivalent to dividing the display area into equal parts. When the second group of signal terminals Z2 is introduced into the display panel, the second group of signal terminals Z2 can be set in the area between two adjacent sub-display areas A0. For example, when the second group of signal terminals Z2 includes two first signal terminals 10, the two first signal terminals 10 in the second group of signal terminals Z2 are both located between two adjacent sub-display areas A0, and the first signal lines 11 connected to the two first signal terminals 10 are also located between the corresponding two adjacent sub-display areas A0. In this way, the two first signal lines 11 corresponding to the same second group signal terminal Z2 can respectively transmit the first power supply voltage signal to different sub-display areas A0, so that each sub-display area A0 has two first signal lines 11 corresponding to it and transmits the first power supply voltage signal thereto, which is beneficial to reducing the number of pixel circuit columns connected to each first signal line 11 and reducing the load of the first signal line 11, thereby helping to reduce the voltage drop of the first power supply voltage signal transmitted through the first signal line 11, and helping to improve the overall display brightness uniformity of the display panel.

[0085] It should be noted that the relative position relationship between the first signal terminal and the first signal line corresponding thereto in the embodiment of the present disclosure is for illustration only. In the scheme currently shown, the first signal terminal is located directly below the first signal line connected thereto along the second direction D2, and this method makes it easy to achieve electrical connection between the two. Of course, in some other embodiments of the present disclosure, at least part of the first signal terminals may not be located directly below the corresponding first signal line, and the two may be connected through a fan-out line (curve or broken line), and the present disclosure does not limit this. In some other embodiments of the present disclosure, all of the first signal terminals are not located directly below the corresponding first signal line.

[0086] In an optional embodiment of the present disclosure, for example, please refer to Figure 5, the number of sub-display areas A0 included in the display area is N=10. The more sub-display areas A0 are divided, the fewer pixel circuit columns each sub-display area A0 includes, the smaller the distance between each pixel circuit column and the first signal line 11 closest to it, the fewer pixel circuit columns driven by each first signal line 11, the smaller the load of the first signal line 11, and thus the smaller the voltage drop of the first power supply voltage signal transmitted through the first signal line 11, which is more conducive to weakening or avoiding the problem of uneven display brightness caused by the large voltage drop of the first power supply voltage signal. Therefore, when the number of sub-display areas A0 is 10, it is more conducive to improving the uniformity of the overall display brightness of the display panel.

[0087] Please continue to refer to Figure 5 and Figure 7 In an optional embodiment of the present disclosure, the display panel includes two first signal terminals Z1, and the first signal terminals Z1 are located between an edge B1 of the display panel and the second signal terminals Z2.

[0088] Specifically, this embodiment shows that when the first group of signal terminals Z1 is introduced into the display panel, a first group of signal terminals Z1 is introduced at a position close to the left edge and a position close to the right edge of the display panel respectively. When the display panel includes a plurality of second group of signal terminals Z2, the first group of signal terminals Z1 is located on the side of the edge of the display panel facing the plurality of second group of signal terminals Z2. The left edge, right edge and edge of the display panel mentioned in this embodiment all refer to the edge of the display panel extending along the second direction D2. That is to say, the first group of signal terminals Z1 is located in the area close to the left edge and the right edge of the display panel, and the corresponding first signal line 11 can also be set in the area close to the left edge and the right edge of the display panel. In this way, the first group of signal terminals Z1 and the corresponding first signal line 11 can provide the first power supply voltage signal to the pixel circuit 20 close to the edge area of ​​the display panel, thereby meeting the demand for the first power supply voltage signal in the display area close to the edge area of ​​the display panel. Moreover, providing the first power supply voltage signal to the edge area and non-edge area of ​​the display area through the first group of signal terminals Z1 and the second group of signal terminals Z2 respectively helps to reduce the transmission voltage drop of the first power supply voltage signal and improve the overall display brightness uniformity of the display panel.

[0089] Please continue to refer to Figure 5 and Figure 7In an optional implementation of the present disclosure, the first group of signal terminals Z1 includes a first signal terminal 10 , and the second group of signal terminals Z2 includes two first signal terminals 10 , and each first signal terminal 10 is electrically connected to a first signal line 11 . The first signal line 11 connected to the first signal terminal 10 in the first group of signal terminals Z1 is located between the edge of the display panel extending along the second direction D2 and the pixel circuit column adjacent to the edge, and the first signal line 11 connected to the two first signal terminals 10 in the second group of signal terminals Z2 is located between two adjacent sub-display areas A0. This arrangement of the first signal lines 11 corresponding to the first group of signal terminals Z1 and the second group of signal terminals Z2 divides the display panel into multiple sub-display areas A0 arranged along the first direction D1, and each sub-display area A0 corresponds to two first signal lines 11 to provide the first power supply voltage signal thereto, and the first signal lines 11 corresponding to each sub-display area A0 are different, which is beneficial to reducing the number of pixel circuit columns corresponding to each first signal line 11 and reducing the load of the first signal line 11, thereby facilitating the improvement of the transmission rate of the first power supply voltage signal line and reducing the transmission voltage drop of the first power supply voltage signal, thereby facilitating the improvement of the overall display brightness uniformity of the display panel.

[0090] Please continue to refer to Figure 5 and Figure 7 In an optional embodiment of the present disclosure, when the second group of signal terminals Z2 includes two first signal terminals 10, the first signal lines 11 corresponding to the two first signal terminals 10 in the second group of signal terminals Z2 do not include pixel circuits 20, that is, the two first signal lines 11 corresponding to the same second group of signal terminals Z2 are located between two adjacent pixel circuit columns. In this way, the display panel can be divided into a plurality of sub-display areas A0 through the first signal lines 11 corresponding to the second group of signal terminals Z2, and the two first signal lines 11 corresponding to the same second group of signal terminals Z2 respectively provide the first power supply voltage signal to different sub-display areas A0, thereby effectively reducing the number of pixel circuit columns corresponding to a single first signal line 11, which is beneficial to reducing the load of the first signal line 11 and improving the rate of the first power supply voltage signal transmitted by the first signal line 11, so it is beneficial to reduce the voltage drop of the first power supply voltage signal and improve the overall display brightness uniformity of the display panel.

[0091] Please refer to Figure 5 and Figure 7In an optional embodiment of the present disclosure, the distances between adjacent second-group signal terminals Z2 are equal. The distance between adjacent second-group signal terminals Z2 mentioned in this embodiment can be regarded as the distance between two first signal terminals 10 that are closer in the adjacent second-group signal terminals Z2, that is, the width of the interval between two adjacent second-group signal terminals Z2. In this embodiment, the two first signal terminals 10 corresponding to the second-group signal terminals Z2 are located between two adjacent sub-display areas A0, and the corresponding two first signal lines 11 are also located between two adjacent sub-display areas A0. When the distances between adjacent second-group signal terminals Z2 are equal, the widths of the multiple sub-display areas A0 formed by the first signal lines 11 corresponding to different second-group signal terminals Z2 will be equal, that is, the number of pixel circuit columns contained in each sub-display area A0 is equal. In this way, the display panel is equally divided into multiple sub-display areas A0 and each sub-display area A0 has two corresponding first signal lines 11 to provide it with the first power supply voltage signal, which is beneficial to reducing the load of each first signal line 11, and the load of each first signal line 11 is the same or nearly the same, so it is beneficial to reduce the voltage drop of the first power supply voltage signal transmitted on the first signal line 11, and further helps to improve the overall display brightness uniformity of the display panel.

[0092] Figure 8 FIG. 1 is another schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Fig. 9 Said Figure 8 A connection diagram of the first signal line 11 and the first connecting line 31, please refer to Figure 8 and Fig. 9 In an optional embodiment of the present disclosure, the display panel further includes a plurality of first connection lines 31 extending along the first direction D1 and arranged along the second direction D2, the first connection lines 31 and the first signal lines 11 are arranged in different layers, and the first connection lines 31 are configured to transmit a first power supply voltage signal to the pixel circuit 20; along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the first signal lines 11 and the first connection lines 31 overlap to form a plurality of first overlapping areas JD1, and in the first overlapping areas JD1, the first signal lines 11 and the first connection lines 31 are electrically connected through the first connection holes K1.

[0093] Specifically, please combine Figure 8 and Fig. 9After the first power supply voltage signal of the first signal terminal 10 is transmitted to the first signal line 11, it is transmitted to the corresponding pixel circuit 20 through the first connecting line 31 extending along the first direction D1. In this embodiment, when the first signal line 11 and the first connecting line 31 are set in different film layers, it is helpful to avoid the problem of short circuit between the first signal line 11 and other signal lines when the two are set in the same layer. When the first signal line 11 and the first connecting line 31 are set in different film layers, along the direction perpendicular to the light emitting surface of the display panel, the first signal line 11 and the first connecting line 31 have a first overlapping area JD1, and the first signal line 11 and the first connecting line 31 form an electrical connection in part of the first overlapping area JD1 through the first connecting hole K1, so that the voltage on the first signal line 11 is transmitted to the pixel circuit 20 through the first connecting line 31.

[0094] Optionally, the first connecting line 31 extends from the left edge side of the display panel to the right edge side, and along the direction perpendicular to the light emitting surface of the display panel, the first connecting line 31 and each first signal line 11 in the display panel overlap to form a first overlapping area JD1, and each first overlapping area JD1 is provided with a first connecting hole K1, and the first connecting line 31 is electrically connected to different first signal lines 11 through different first connecting holes K1, respectively. In this way, multiple first signal lines 11 and multiple first connecting lines 31 form a grid structure, which is beneficial to reducing the overall impedance of the grid structure formed by the first signal lines 11 and the first connecting lines 31, thereby helping to reduce the voltage drop of the first power supply voltage signal transmitted on the first signal line 11, and improving the problem of uneven display brightness of the display panel due to the large voltage drop of the first power supply voltage signal line, so it is beneficial to improve the overall display brightness uniformity of the display panel.

[0095] Fig.10 FIG. 1 is another schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Fig.11 Said Fig.10 A connection diagram of the first signal line 11, the first connecting line 31 and the second connecting line 32, please refer to Fig.10 and Fig.11 In an optional embodiment of the present disclosure, the display panel also includes a plurality of second connection lines 32 extending along the second direction D2 and arranged along the first direction D1, and the second connection lines 32 are located between adjacent pixel circuit columns L; along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the second connection lines 32 and the first connection lines 31 overlap to form a plurality of second overlapping areas JD2, and in the second overlapping areas JD2, the first connection lines 31 and the second connection lines 32 are electrically connected through second connection holes K2.

[0096] Please continue to refer to Fig.10 and Fig.11This embodiment shows a scheme of simultaneously introducing the first connection line 31 and the second connection line 32 into the display panel, wherein the first connection line 31 extends along the first direction D1 and is arranged along the second direction D2, the second connection line 32 extends along the second direction D2 and is arranged along the first direction D1, and the extension direction and arrangement direction of the second connection line 32 are respectively the same as the extension direction and arrangement direction of the first signal line 11. Optionally, the second connection line 32 is arranged in the same layer as the first signal line 11, and the two can be manufactured in the same process, without introducing different manufacturing processes and film layer structures for the two, which is conducive to simplifying the manufacturing process and film layer structure of the display panel. Of course, in some other embodiments of the present disclosure, the second connection line 32 and the first signal line 11 can also be arranged in different film layers, which is not limited by the present disclosure. The end of the first signal line 11 along the second direction D2 is electrically connected to the first signal terminal 10 to obtain a first power supply voltage signal. The end of the second connection line 32 along the second direction D2 is not electrically connected to the first signal terminal 10. The second connection line 32 transmits the first power supply voltage signal by connecting to the first connection line 31.

[0097] In this embodiment, the second connection line 32 and the first connection line 31 are located in different film layers. In a direction perpendicular to the plane where the light emitting surface of the display panel is located, the second connection line 32 overlaps with the first connection line 31 to form a second overlapping area JD2. In the second overlapping area JD2, the second connection line 32 and the first connection line 31 are electrically connected through the second connection hole K2. In this way, the signal line for transmitting the first power supply voltage signal in the display panel includes the first signal line 11, the first connection line 31 and the second connection line 32. The first signal line 11 and the second connection line 32 extend along the second direction D2, and the first connection line 31 extends along the first direction D1. The three are staggered horizontally and vertically, and a denser mesh structure for transmitting the first power supply voltage signal is formed through the first connection hole K1 and the second connection hole K2, so as to be more conducive to reducing the overall impedance of the mesh structure, reducing the voltage drop of the first power supply voltage signal, and reducing the difference of the first power supply voltage signal obtained by the pixel circuit 20 in different areas of the display panel, so as to be more conducive to improving the overall display brightness uniformity of the display panel.

[0098] Please continue to refer to Fig.11In an optional embodiment of the present disclosure, along the first direction D1, the width of the second connection line 32 is greater than or equal to the width of the first signal line 11. When the width of the second connection line 32 is equal to the width of the first signal line 11, the second connection line 32 and the first signal line 11 can be made with the same width parameter, which is conducive to simplifying the manufacturing process of the display panel. Optionally, the number of the second connection lines 32 in the display panel is greater than the number of the first signal lines 11. The larger the number of the second connection lines 32, the more it is necessary to reduce its impedance to reduce the voltage drop of the first power supply voltage signal transmitted by it; when the display panel has space to set the second connection line 32 with a larger width, the width of the second connection line 32 can be set to be greater than the width of the first signal line 11. The larger the width of the second connection line 32, the smaller the impedance, which is more conducive to reducing the overall impedance of the mesh structure composed of the first signal line 11, the first connection line 31 and the second connection line 32, so as to be more conducive to reducing the voltage drop of the first power supply voltage signal transmitted on the above-mentioned mesh structure, so as to further improve the overall display brightness uniformity of the display panel. In addition, setting the width of the second connection line 32 to be greater than the width of the first signal line 11 is beneficial to simplifying the wiring of the second connection line 32, thereby facilitating simplifying the overall layout design.

[0099] Fig.12 FIG. 1 is a diagram showing a relative position relationship between the first signal line 11 and the second signal line 12 in the present disclosure. Fig.12 In an optional embodiment of the present disclosure, the display panel also includes a plurality of second signal lines 12 extending along the first direction D1 and arranged along the second direction D2, and the second signal lines 12 are configured to transmit display control signals to the pixel circuit 20; the first signal line 11 includes a plurality of first openings K01, and the first openings K01 overlap with the second signal lines 12 along a direction perpendicular to the plane where the light emitting surface of the display panel is located.

[0100] The second signal line 12 mentioned in this embodiment can be, for example, a scanning line that provides a scanning signal to the pixel circuit 20, or a light-emitting control signal line that provides a light-emitting control signal to the pixel circuit 20. The signal transmitted on the second signal line 12 is different from the signal transmitted on the first signal line 11. Therefore, when the first signal line 11 and the second signal line 12 overlap in a direction perpendicular to the plane where the light-emitting surface of the display panel is located, parasitic capacitance will be generated in the overlapping area, and the existence of parasitic capacitance is likely to cause signal crosstalk. To this end, in this embodiment, a plurality of first openings K01 are formed on the first signal line 11, so that the first openings K01 overlap with the second signal line 12, which is conducive to reducing the actual overlapping area of ​​the first signal line 11 and the second signal line 12, so as to reduce the parasitic capacitance between the first signal line 11 and the second signal line 12, thereby facilitating the improvement of the stability of the signal transmitted on the second signal line 12.

[0101] Fig.13 The figure shows a relative position relationship diagram of the first signal line 11, the second signal line 12 and the second connecting line 32 in the present disclosure. When the display panel includes the first signal line 11, the second signal line 12 and the second connecting line 32 at the same time, the second signal line 12 extends along the first direction D1, and the first signal line 11 and the second connecting line 32 extend along the second direction D2. Along the direction perpendicular to the plane where the light emitting surface of the display panel is located, the second signal line 12 will overlap with the first signal line 11 and the second connecting line 32 respectively. Therefore, in addition to introducing the first opening K01 on the first signal line 11, the second opening K02 may also be introduced on the second connecting line 32. Along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the first opening K01 and the second opening K02 overlap with the second signal line 12 respectively. This is beneficial to reducing the actual overlapping area of ​​the first signal line 11 and the second signal line 12, and is beneficial to reducing the actual overlapping area of ​​the second connecting line 32 and the second signal line 12, thereby helping to simultaneously reduce the parasitic capacitance between the first signal line 11 and the second signal line 12, and the parasitic capacitance between the second connecting line 32 and the second signal line 12, so it is beneficial to improve the stability of the signal transmitted on the second signal line 12.

[0102] Fig.12 and Fig.13 The illustrated embodiment only illustrates the first opening and the second opening through a rectangular structure, and does not limit the actual shape, size and number of the openings on the first signal line 11 and the second connecting line 32. In some other embodiments of the present disclosure, the first opening K01 and the second opening K02 may also adopt other shapes, and the present disclosure is not limited thereto.

[0103] It should be noted that Fig.12 and Fig.13 In the embodiment shown, the first opening K01 on the first signal line 11 is only arranged in the region overlapping with the second signal line 12, and the second opening K02 on the second connection line 32 is only arranged in the region overlapping with the second signal line 12. In the actual process, the first signal line 11 as a whole or the second connection line 32 as a whole can also be arranged to have a structure with multiple openings. For example, please refer to Fig.14 , Fig.14Another relative position relationship diagram of the first signal line 11, the second signal line 12 and the second connection line 32 in the present disclosure is shown. In the present embodiment, the second connection line 32 is set as a grid structure including a plurality of second openings K02. That is, in addition to the area overlapping with the second signal line 12, the area on the second connection line 32 that does not overlap with the second signal line 12 is also provided with a second opening K02. This is conducive to ensuring that the second connection line 32 has corresponding second openings K02 in most areas in the area overlapping with the second signal line 12, thereby facilitating the reduction of the actual overlapping area between the second connection line 32 and the second signal line 12, so that the parasitic capacitance between the second connection line 32 and the second signal line 12 is effectively reduced. Of course, in some other embodiments of the present disclosure, the first signal line 11 can also be set as a grid structure similar to the second connection line 32 in the present embodiment to ensure that the parasitic capacitance between the first signal line 11 and the second signal line 12 is effectively reduced, and the present disclosure does not specifically limit this.

[0104] Fig.15 FIG. 2 is a schematic diagram of a pixel circuit 20 provided in an embodiment of the present disclosure. Fig.16 Shown with Fig.15 For a corresponding timing diagram, please refer to Figure 5 , Fig.15 and Fig.16 In an optional embodiment of the present disclosure, the pixel circuit 20 is configured to provide a driving current to the pixel; the pixel circuit 20 includes a pulse amplitude modulation circuit 110 and a pulse width modulation circuit 120, the pulse amplitude modulation circuit 110 is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit 120 is configured to control the pulse width of the driving current; the pulse width modulation circuit 120 includes a first power supply terminal VDD_PWM, and the first power supply terminal VDD_PWM is electrically connected to the first signal terminal 10 through the first signal line 11.

[0105] It should be noted that Fig.15 The pixel circuit 20 shown is for illustration only, and the present disclosure does not limit the actual structure of the pixel circuit 20. In some other embodiments of the present disclosure, any other feasible pixel circuit 20 structure may be adopted. In the pixel circuit 20, the pulse width modulation circuit 120 is electrically connected to the pulse amplitude modulation circuit 110, and the pulse amplitude modulation circuit 110 is used to be electrically connected to the light emitting element, wherein the first power supply terminal VDD_PWM of the pulse width modulation circuit 120 refers to the positive power supply voltage terminal of the pulse width modulation circuit 120.

[0106] Please continue to refer to Fig.15 and Fig.16Optionally, the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 both include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, a storage capacitor C1 / C2 and a driving transistor Dr_PAM / Dr_PWM (wherein the pulse amplitude modulation circuit 110 includes an initialization unit 111, a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C1 and a driving transistor Dr_PAM; the pulse width modulation circuit 120 includes an initialization unit 121, The data writing unit 122, the threshold compensation unit 123, the light emitting control unit 124, the storage capacitor C2 and the driving transistor Dr_PWM), the initialization unit 111 / 121 is electrically connected between the initialization signal terminal VREF and the first node N11 / N12, and the initialization unit 111 / 121 is used to provide the initialization signal of the initialization signal terminal VREF to the first node N11 / N12 in the initialization phase t1 (the value of the initialization signal provided by the initialization signal terminal of the pulse amplitude modulation circuit 110 and the value of the initialization signal provided by the initialization signal terminal of the pulse width modulation circuit 120 may be the same or different). The data writing unit 112 / 122 is electrically connected between the data signal terminal DATA_PAM / DATA_PWM and the first electrode of the driving transistor Dr_PAM / Dr_PWM, and the gate of the driving transistor Dr_PAM / Dr_PWM and the first electrode plate of the storage capacitor C1 / C2 are electrically connected to the first node N11 / N12; the data writing unit 112 / 122 is used to provide the data voltage signal of the data signal terminal DATA_PAM / DATA_PWM to the first node N11 / N12 through the driving transistor Dr_PAM / Dr_PWM during the data writing phase t2. The threshold compensation unit 113 / 123 is electrically connected between the second electrode of the driving transistor Dr_PAM / Dr_PWM and the first node N11 / N12, and the threshold compensation unit 113 / 123 is used to compensate the threshold voltage of the driving transistor Dr_PAM / Dr_PWM to the first node N11 / N12.

[0107] In the pulse width modulation circuit 120, the second electrode plate of the storage capacitor C2 is electrically connected to the sweep signal terminal SWEEP, and the sweep signal terminal SWEEP receives the sweep signal. The light-emitting control unit 124 is electrically connected between the first power supply terminal VDD_PWM and the first node N11 in the pulse amplitude modulation circuit 110; the light-emitting control unit 124 is used to control the driving transistor Dr_PWM to generate a driving pulse in the light-emitting stage t3; the first power supply terminal VDD_PWM receives the first power supply voltage signal VDD_PWM (here the same characters are used to represent the signal terminal and the signal provided by the signal terminal), and the data signal terminal DATA_PWM receives the pulse width modulated data voltage DATA_PWM (here the same characters are used to represent the signal terminal and the signal provided by the signal terminal).

[0108] In the pulse amplitude modulation circuit 110, the second electrode plate of the storage capacitor C1 is electrically connected to the power signal terminal VDD_PAM, and the power signal terminal VDD_PAM receives the second power voltage signal VDD_PAM (the signal terminal and the signal provided by the signal terminal are represented by the same characters). The light-emitting control unit 114 is electrically connected between the power signal terminal VDD_PAM and the light-emitting element D0; the light-emitting control unit 114 is used to control the driving transistor Dr_PAM to generate a driving current to flow into the light-emitting element D0 in the light-emitting stage, so as to drive the light-emitting element D0 to emit light, and the data signal terminal DATA_PAM receives the pulse amplitude modulation data voltage DATA_PAM (the signal terminal and the signal provided by the signal terminal are represented by the same characters).

[0109] In this embodiment, the output end of the pulse width modulation circuit 120 is electrically connected to the first node N11 of the pulse amplitude modulation circuit 110, and is used to provide a control signal to the first node N11. Since the first node N11 is electrically connected to the gate of the driving transistor Dr_PAM, it is equivalent to providing a control signal to the gate of the driving transistor Dr_PAM. In the pulse width modulation circuit 120, when the voltage difference between the gate and the source of the driving transistor Dr_PWM is greater than the threshold voltage of the driving transistor Dr_PWM, the driving transistor Dr_PWM is in a cut-off state. At this time, the pulse width modulation circuit 120 does not provide a control signal to the first node N11 of the pulse amplitude modulation circuit 110, and the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 provides a driving current to the light-emitting element according to the pulse amplitude modulation data voltage DATA_PAM. As the voltage of the sweep signal SWEEP changes, the gate potential of the driving transistor Dr_PWM changes synchronously, until the voltage difference between the gate and the source of the driving transistor Dr_PWM is less than or equal to the threshold voltage of the driving transistor Dr_PWM, the driving transistor Dr_PWM is turned on, and the driving transistor Dr_PWM transmits the first power supply voltage signal VDD_PWM of the first power supply terminal VDD_PWM as the cut-off voltage to the first node N11 of the pulse amplitude modulation circuit 110, so that the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 is cut off, thereby stopping the driving current from being provided to the light-emitting element D0. It can be seen that the magnitude of the first power supply voltage signal VDD_PWM of the first power supply terminal VDD_PWM directly determines its ability to turn off the driving transistor Dr_PAM in the pulse amplitude modulation circuit 100. The first power supply terminal VDD_PWM obtains the first power supply voltage signal VDD_PWM through the first signal line 11 and the first signal terminal 10. In the related art, the voltage drop of the first power supply voltage signal is large in the area far from the first signal terminal 10, which reduces the ability to turn off the driving transistor Dr_PAM in the pulse amplitude modulation circuit, thus causing the problem of uneven display. Therefore, the present disclosure reduces the voltage drop of the first power supply voltage signal by introducing the first group of signal terminals Z1 and the second group of signal terminals Z2 and the corresponding first signal line 11, so that the first power supply voltage signal VDD_PWM transmitted to the pulse amplitude modulation circuit 110 in the pixel circuits of different areas tends to be consistent, so that the ability to turn off the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 tends to be consistent, which is beneficial to improve the overall display brightness uniformity of the display panel.

[0110] It should be noted that Fig.15 The driving circuit structure shown is an optional example of the present disclosure and is not a limitation on the display panel driving circuit. Fig.15The pulse amplitude modulation circuit and the pulse width modulation circuit shown in the figure both include a threshold compensation unit, which is used to compensate the data signal for the threshold voltage of the driving transistor when writing the data signal into the circuit, so as to ensure that the driving transistor provides an accurate driving current and avoid being affected by the threshold voltage of the driving transistor when writing data. The embodiment of the present disclosure is also applicable to a driving circuit structure without a threshold compensation unit, for example, Fig.15 The pulse amplitude modulation circuit and the pulse width modulation circuit shown are adjusted as follows: the threshold compensation unit 113 / 123 is removed, and the connection mode of the data writing unit 112 / 122 is adjusted to be connected between the data signal terminal DATA_PAM / DATA_PWM and the gate of the driving transistor Dr_PAM / Dr_PWM, so as to provide the data voltage signal of the data signal terminal DATA_PAM / DATA_PWM to the first node N11 / N12 through the data writing unit during the data writing stage. The present disclosure does not limit the specific structure of the pixel circuit.

[0111] In addition, in order to reduce the leakage current from other transistors in the pixel circuit 20 to the first node, Fig.15 The pulse amplitude modulation circuit and the pulse width modulation circuit shown are adjusted as follows: the initialization unit 111 / 121 and the threshold compensation unit 113 / 123 connected to the pulse amplitude modulation circuit 110 and the driving transistor Dr_PAM / Dr_PWM in the pulse width modulation circuit are adjusted to dual-gate transistors or oxide transistors.

[0112] Fig.17 FIG. 1 is another schematic diagram of a pixel circuit provided by an embodiment of the present disclosure, wherein the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 both include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, a storage capacitor C1 / C2 and a driving transistor Dr_PAM / Dr_PWM, and are connected to Fig.15 The embodiments shown are the same, and the working principle can also refer to Fig.15 The relevant descriptions of the illustrated embodiment will not be repeated here. Fig.17 The embodiment shown and Fig.15 One of the differences between the illustrated embodiments is that Fig.17The pulse amplitude modulation circuit 110 in the embodiment further includes a capacitor C3 and a compensation module 115. The compensation module 115 includes two transistors, and the gates of the two transistors are connected to the control signals K1 and K2 respectively. The first plate of the capacitor C3 is connected to the first node N11, and the second plate is connected to the compensation module 115. The compensation module 115 is configured to write a reference voltage Vp to the second plate of the capacitor C3 during a first period of operation of the pulse amplitude modulation circuit 110, and write a second power supply voltage signal VDD_PAM to the second plate of the capacitor C3 during a second period of operation of the pulse amplitude modulation circuit 110; in the working cycle of the pixel circuit, the first period and the second period do not overlap.

[0113] The compensation module 115 can write different voltages to the second plate of the capacitor C3 at different time periods when the pulse amplitude modulation circuit 110 is working. For example, the second time period at least includes the time period when the pulse amplitude modulation circuit 110 is working to generate the driving current (for example Fig.16 The first period is before the period in which the pulse amplitude modulation circuit 110 generates the driving current. Optionally, the first period includes the initialization period t1 of the pulse amplitude modulation circuit 110 and / or the data writing phase t2.

[0114] In the initialization phase t1 of the pulse amplitude modulation circuit 110, the initialization unit 111 is turned on to reset the gate of the driving transistor Dr_PAM. In the data writing phase t2 of the pulse amplitude modulation circuit 110, the data writing unit 112 and the threshold compensation unit 113 are turned on to write the data signal DATA_PAM to the gate of the driving transistor Dr_PAM and perform threshold compensation. The voltage of the gate of the driving transistor Dr_PAM is DATA_PAM-|Vth|. At this time, the compensation module 30 writes the reference voltage Vp to the second plate of the capacitor C3.

[0115] In the actual light-emitting period t31 in the light-emitting stage t3, the compensation module 30 writes the second power supply voltage signal VDD_PAM to the second plate of the capacitor C3. When the voltage of the second plate of the capacitor C3 jumps from the reference voltage Vp to the second power supply voltage signal VDD_PAM, its voltage change is VDD_PAM-Vp. Due to the coupling effect of the capacitor C3, the voltage of the gate of the driving transistor Dr_PAM jumps to DATA_PAM-|Vth|+VDD_PAM-Vp. In the actual light-emitting period, the light-emitting control unit 114 is turned on, and the driving transistor Dr_PAM generates a driving current under the control of its gate voltage. The calculation formula of the driving current is: the driving current I d =K*(Vgs-|Vth|) 2, Vgs is the voltage difference between the gate and source of the driving transistor. Applied in the driving transistor Dr_PAM, its gate voltage is DATA_PAM-|Vth|+VDD_PAM-Vp, and its source voltage is VDD_PAM, then Vsg=(DATA_PAM-|Vth|+VDD_PAM-Vp)-VDD_PAM-=DATA_PAM-|Vth|-Vp. d =K*(DATA_PAM-Vp) 2 , at this time, the driving current is related to the data signal DATA_PAM and the reference voltage Vp, and has nothing to do with the threshold voltage Vth and the second power supply voltage signal VDD_PAM. Thus, the compensation module 30 is used to compensate for the deviation of the second power supply voltage signal VDD_PAM that affects the driving current, so that the driving current is no longer affected by the deviation of the second power supply voltage signal VDD_PAM, avoiding uneven display caused by the deviation of the second power supply voltage signal VDD_PAM, and improving display uniformity.

[0116] Fig.15 and Fig.17 In the embodiment shown, the output end of the pulse width modulation circuit 120 is directly connected to the gate of the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110. In some other embodiments of the present disclosure, there are some other connection relationships between the pulse width modulation circuit and the pulse amplitude modulation circuit, as shown below. Figures 18 to 20 , some exemplary connection modes between the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 are introduced, Figures 18 to 20 Shown are respectively a connection schematic diagram of a pulse amplitude modulation circuit and a pulse width modulation circuit in the present disclosure.

[0117] like Fig.18 As shown, the pixel circuit may further include a connection capacitor C01 , and the pulse width modulation circuit 120 may be connected to the gate of the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 via the connection capacitor C01 .

[0118] Or, if Fig.19 As shown, the pulse amplitude modulation circuit 110 may further include a first control transistor T1, which is connected between the driving transistor Dr_PAM and the light emitting element D0. The output terminal of the pulse width modulation circuit 120 may be connected to the gate of the first control transistor T1.

[0119] Or, if Fig. 20 As shown, the pixel circuit may further include a connecting capacitor C02 , and the output end of the pulse width modulation circuit 120 may be connected to the gate of the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 through the connecting capacitor C02 .

[0120] It should be noted that the structure of any pulse amplitude modulation circuit 110 in the above embodiments can be combined with the structure of any pulse width modulation circuit 120 in other embodiments. Figures 18 to 20 The pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 are connected in any of the connection modes. It should also be noted that other structures of the pulse amplitude modulation circuit 110, other structures of the pulse width modulation circuit 120, and other connection modes between the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 are applicable to the embodiments described in the present disclosure.

[0121] Please continue to refer to Fig.15 Combined with Fig.21 , Fig.21 The figure shows a connection diagram of the second signal terminal 50 and the first connection portion 51 in the display panel provided by the present disclosure. In an optional embodiment of the present disclosure, the pulse amplitude modulation circuit 110 includes a second power supply terminal (corresponding to Fig.15 The display panel includes a second signal terminal 50 and a first connection portion 51, and the second power terminal VDD_PAM is electrically connected to the second signal terminal 50 through the first connection portion 51; the second signal terminal 50 is configured to transmit a second power voltage signal to the second power terminal VDD_PAM; the number of the second signal terminals 50 is greater than the number of the first signal terminals 10. In this embodiment, the second signal terminal 50 is a terminal for providing a second power voltage signal to the second power terminal in the pulse amplitude modulation circuit. Considering that the pulse amplitude modulation circuit is connected to the light-emitting element, the magnitude of the driving current driving the light-emitting element to emit light is closely related to the magnitude of the second power voltage signal, so the transmission uniformity of the second power voltage signal directly affects the display brightness uniformity of the light-emitting element in the display panel. In this embodiment, a large number of second signal terminals 50 are set in the display panel, and the second power voltage signal is provided to the pulse amplitude modulation circuit in the pixel circuit 20 through a large number of second signal terminals 50, which is conducive to reducing the voltage drop of the second power voltage signal and improving the uniformity of the second power voltage signal received by the pixel circuits 20 in different regions, so it is conducive to improving the overall display effect of the display panel.

[0122] Please continue to refer to Fig.15 and Fig.21In an optional embodiment of the present disclosure, the first connection portion 51 is a planar structure. When the first connection portion 51 is set as a planar structure, it is beneficial to reduce the overall impedance of the first connection portion 51 and increase the rate of the second power supply voltage signal transmitted on the first connection portion 51, so it is beneficial to reduce the size difference of the second power supply voltage signal in different areas and improve the overall display brightness uniformity of the display panel. When the first connection portion 51 is set as a planar structure, the second power supply terminal VDD_PAM in the pulse amplitude modulation circuit can be electrically connected to the first connection portion 51 by punching, without introducing a connecting wire, which is beneficial to simplify the wiring complexity of the display panel.

[0123] Fig. 22 Shown Figure 2 A CC cross-sectional view of the display panel. Fig. 22 Only the first signal terminal 10, the side connection line 91 and the electrical connection terminal 90 in the display panel are illustrated, and the detailed film layer structure of the display panel is not shown. The detailed film layer structure of the display panel can refer to the prior art, and the present disclosure does not specifically limit this. Please refer to Fig. 22 In an optional embodiment of the present disclosure, an electrical connection terminal 90 is provided on the non-light emitting surface M02 of the display panel, and the first signal terminal 10 is electrically connected to the electrical connection terminal 90 through a side connection line 91. The side connection line 91 is configured to extend from the light emitting surface M01 of the display panel through the side of the display panel to the non-light emitting surface M02 of the display panel. In this way, there is no need to set a binding area on the light emitting surface M01 of the display panel to bind the flexible circuit board or the driver chip, which is conducive to realizing an extremely narrow frame or a frameless design of the display panel, and multiple display panels of this structure can be spliced ​​to form a larger display product. It should be noted that other signal terminals located on the light emitting surface of the display panel can also be electrically connected to the electrical connection terminal located on the non-light emitting surface of the display panel in a manner similar to the first signal terminal 10, and this will not be illustrated in the present disclosure.

[0124] Based on the same inventive concept, the present disclosure also provides a display device, Fig.23 FIG. 2 is a schematic diagram of a structure of a display device 200 provided in an embodiment of the present disclosure. Fig.23 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book, or a television. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel in the above embodiments, which will not be repeated in this embodiment.

[0125] Understandably, Fig.23Only a rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0126] Fig.24 and Fig.25 Another schematic diagram of the structure of the display device 200 provided in the embodiment of the present disclosure is shown respectively. Fig.24 and Fig.25 In an optional embodiment of the present disclosure, the display device 200 includes a plurality of display panels 100 that are spliced ​​together, and along the second direction D2, the first signal terminal 10 is located on a first side of the corresponding display panel, or the first signal terminal is located on both sides of the corresponding display panel.

[0127] Fig.24 and Fig.25 The following description only takes the case where the display device includes two display panels as an example, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the display device may also include more than two display panels. Fig.24 and Fig.25 Only two display panels are arranged along the first direction for illustration. In some other embodiments of the present disclosure, the display panels may also be arranged along the second direction. If more than four display panels are spliced, they may also be arranged in an array along the first direction and the second direction. The present disclosure is not limited to this. In the display device formed by splicing, the first signal terminal may be located on the first side or both sides of the corresponding display panel along the second direction. The position of the first signal terminal may be flexibly set according to actual needs, and the present disclosure does not specifically limit this.

[0128] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0129] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, It is characterized in that include: A display area, wherein a plurality of pixels are arranged in the display area, and the pixels are electrically connected to the pixel circuit; a plurality of first signal terminals arranged along a first direction and first signal lines respectively connected to the first signal terminals, wherein the first signal terminals are configured to provide a first power supply voltage signal to the pixel circuit through the first signal lines; the first signal lines extend along a second direction, the first direction intersects with the second direction and are parallel to a light emitting surface of the display panel; The first signal end includes a first group of signal ends and a second group of signal ends, the number of the first signal ends included in the second group of signal ends is greater than the number of the first signal ends included in the first group of signal ends; along the first direction, the first group of signal ends is located between the second group of signal ends and the edge of the display panel.

2. The display panel according to claim 1, It is characterized in that The number of the second group of signal terminals is greater than the number of the first group of signal terminals.

3. The display panel according to claim 1, It is characterized in that The first group of signal terminals includes one first signal terminal, and the second group of signal terminals includes two first signal terminals.

4. The display panel according to claim 2, It is characterized in that Along the first direction, a distance between the first signal lines corresponding to the second group of signal terminals is smaller than a distance between the first signal lines corresponding to the first group of signal terminals and the first signal lines corresponding to the second group of signal terminals.

5. The display panel according to claim 1, It is characterized in that Along the first direction, a minimum distance between a first signal line corresponding to the first group of signal terminals and a first signal line corresponding to the second group of signal terminals is S1, a width of the display panel along the first direction is S0, and S1 / S0≤1 / 2.

6. The display panel according to claim 5, It is characterized in that S1 / S0≤1 / 10.

7. The display panel according to claim 5, It is characterized in that At least two groups of the second group of signal terminals are included, and along the first direction, the minimum distance between the first signal lines corresponding to two adjacent groups of the second group of signal terminals is S2, and S2=S1.

8. The display panel according to claim 1, It is characterized in that The first signal line connected to the first group of signal terminals is located between a first edge of the display panel and the first signal line connected to the second group of signal terminals, and the pixel circuit is not included between the first signal line and the first edge, and the first edge extends along the second direction.

9. The display panel according to claim 1, It is characterized in that The display panel includes N1 pixel circuit columns arranged along the first direction, and the minimum number of the pixel circuit columns included between the first signal line connected to the first group of signal terminals and the first signal line connected to the second group of signal terminals is N2, and N2 / N1≤1 / 2.

10. The display panel according to claim 9, It is characterized in that N2 / N1≤1 / 10.

11. The display panel according to claim 1, It is characterized in that The display panel comprises a plurality of pixel circuit columns arranged along the first direction, and the display panel comprises at least two groups of the second group of signal terminals; Along the first direction, in the adjacent first group of signal terminals and the second group of signal terminals, the minimum number of pixel circuit columns included between the first signal line connected to the first group of signal terminals and the first signal line connected to the second group of signal terminals is n1; in the adjacent second group of signal terminals, the number of pixel circuit columns included between the first signal lines respectively connected to two groups of the second group of signal terminals is n2, n1=n2.

12. The display panel according to claim 11, It is characterized in that In the second group of signal terminals, the first signal lines to which at least two of the first signal terminals are connected do not include the pixel circuit.

13. The display panel according to claim 1, It is characterized in that In the second group of signal terminals, the pixel circuit is included between the first signal lines connected to at least two of the first signal terminals.

14. The display panel according to claim 1, It is characterized in that The second group of signal terminals includes two of the first signal terminals, and along the first direction, a distance between the first signal lines connected to the two first signal terminals in the second group of signal terminals is less than 625 μm.

15. The display panel according to claim 1, It is characterized in that The number of the second group of signal terminals is Q, Q≥3, and Q is an odd number.

16. The display panel according to claim 15, It is characterized in that Q＝9。 17. The display panel according to claim 1, It is characterized in that The display area includes N sub-display areas arranged along a first direction and having equal widths, and the second group of signal terminals is located between the nth sub-display area and the (n+1)th sub-display area, wherein 1≤n≤N-1.

18. The display panel according to claim 17, It is characterized in that N＝10。 19. The display panel according to claim 18, It is characterized in that The display panel includes two first-group signal terminals, and the first-group signal terminals are located between an edge of the display panel and the second-group signal terminals.

20. The display panel according to claim 17, It is characterized in that The first group of signal terminals includes one first signal terminal, and the second group of signal terminals includes two first signal terminals.

21. The display panel according to claim 20, It is characterized in that In the second group of signal terminals, the pixel circuit is not included between the first signal lines correspondingly connected to two of the first signal terminals.

22. The display panel according to claim 21, It is characterized in that The distances between adjacent signal terminals of the second group are equal.

23. The display panel according to claim 1, It is characterized in that Also included are a plurality of first connection lines extending along the first direction and arranged along the second direction, the first connection lines and the first signal lines are arranged in different layers, and the first connection lines are configured to transmit the first power supply voltage signal to the pixel circuit; Along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the first signal line and the first connecting line overlap to form a plurality of first overlapping areas. In the first overlapping areas, the first signal line and the first connecting line are electrically connected through first connecting holes.

24. The display panel according to claim 23, It is characterized in that Also comprising a plurality of second connection lines extending along the second direction and arranged along the first direction, wherein the second connection lines are located between adjacent columns of the pixel circuits; Along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the second connecting lines overlap with the first connecting lines to form a plurality of second overlapping areas. In the second overlapping areas, the first connecting lines and the second connecting lines are electrically connected through second connecting holes.

25. The display panel according to claim 24, It is characterized in that Along the first direction, the width of the second connecting line is greater than or equal to the width of the first signal line.

26. The display panel according to claim 1, It is characterized in that It also includes a plurality of second signal lines extending along the first direction and arranged along the second direction, the second signal lines being configured to transmit display control signals to the pixel circuit; the first signal line includes a plurality of first openings, and the first openings overlap with the second signal lines along a direction perpendicular to the plane where the light emitting surface of the display panel is located.

27. The display panel according to claim 1, It is characterized in that The pixel circuit is configured to provide a drive current to the pixel; The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit, the pulse amplitude modulation circuit is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the driving current; The pulse width modulation circuit includes a first power supply terminal, and the first power supply terminal is electrically connected to the first signal terminal through the first signal line.

28. The display panel according to claim 27, It is characterized in that The pulse amplitude modulation circuit includes a second power supply terminal, the display panel includes a second signal terminal and a first connecting portion, the second power supply terminal is electrically connected to the second signal terminal through the first connecting portion; the second signal terminal is configured to transmit a second power supply voltage signal to the second power supply terminal; the number of the second signal terminals is greater than the number of the first signal terminals.

29. The display panel according to claim 28, It is characterized in that The first connecting portion is a planar structure.

30. The display panel according to claim 1, It is characterized in that The non-light-emitting surface of the display panel is provided with an electrical connection terminal, and the first signal end is electrically connected to the electrical connection terminal through a side connection line, and the side connection line is configured to extend from the light-emitting surface of the display panel through the side of the display panel to the non-light-emitting surface of the display panel.

31. A display device, It is characterized in that The display panel comprises any one of claims 1 to 30.

32. The display device according to claim 31, It is characterized in that At least two display panels are spliced ​​together, and along the second direction, the first signal end is located on a first side of the corresponding display panel, or the first signal end is located on two sides of the corresponding display panel.

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