A high-speed differential signal driving circuit and implementation method thereof

By designing the streamlined LVPECL and CML parts and sharing the input parts, the existing high-speed differential signal driving circuit has solved the problem of large circuit size and parasitic capacitance, and a driving circuit with lower power consumption and chip area is realized.

CN119171896BActive Publication Date: 2025-03-18上海奥令科电子科技有限公司
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Patent Information

Application Number
CN202411200259.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-08-29
Publication Date
2025-03-18
Estimated Expiration
2044-08-29

AI Technical Summary

Technical Problem

The existing high-speed differential signal driving circuit has large circuit scale and large parasitic capacitance, resulting in increased power consumption and chip area, and requires pre-drivers, which is not compact enough.

Method used

Design a streamlined LVPECL and CML sections, reduce circuit size and parasitic capacitance, and share input sections through the LVPECL and CML sections, eliminating common pre-drivers.

Benefits of technology

A high-speed differential signal driving circuit with lower power consumption and chip area is realized, which improves device utilization and reduces circuit complexity.

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Abstract

The present invention belongs to the field of high-speed analog integrated circuit design, and provides a high-speed differential signal driving circuit and an implementation method thereof, comprising: an input part, an LVPECL part, a CML part and an output part; the input part comprises: an adjustable current source, a first NMOS tube and a second NMOS tube; the LVPECL part comprises: third to eighth NMOS tubes, a first PMOS tube, a second PMOS tube, a first resistor and a second resistor; the CML part comprises: a ninth NMOS tube, a tenth NMOS tube, a third PMOS tube, a fourth PMOS tube, a third resistor and a fourth resistor; the output part comprises: a P output terminal and an N output terminal. The present invention reduces the circuit scale and parasitic capacitance, power consumption and chip area by designing a streamlined LVPECL part and a CML part; and the common pre-driver is omitted by sharing the input part between the LVPECL part and the CML part.
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