Electrostatic dust collection net

Abstract

The invention is suitable for the technical field of air purification, and provides an electrostatic dust collection net. Comprising a frame, a plurality of first integrated sheets and a plurality of second integrated sheets, the first integrated sheets and the second integrated sheets are alternately arranged in the frame, the first integrated sheets are connected to a first end of a power output end of the power supply device, and the second integrated sheets are connected to a second end of the power output end of the power supply device. Wherein the level values of the first end and the second end of the power output end of the power supply device are alternately switched. The level values of the first integrated chip and the second integrated chip are switched through the power supply device, so that the first integrated chip is high in level and the second integrated chip is low in level in a period of time, and then the levels of the first integrated chip and the second integrated chip are switched, so that the first integrated chip is low in level and the second integrated chip is high in level. And compared with the prior art that a single polar plate is used for collecting dust, the dust collecting amount is larger.

Description

Technical Field

[0001] The invention relates to the technical field of air purification, in particular to an electrostatic dust collecting net. Background Art

[0002] The principle of conventional electrostatic dust collecting nets currently on the market is to assemble them with one negative and one zero-pole sheet at intervals, and to use a negative ion generator or a negative charge field to allow tiny substances (such as dust particles, microorganisms, etc.) passing through the dust collecting net to carry the negative electrode, which repel each other with the negative electrode in the dust collecting net and adsorb to the zero-pole sheet, thereby achieving the purpose of adsorbing tiny substances; because only the zero-pole sheet adsorbs tiny substances, the cumulative purification amount of the electrostatic dust collecting net is usually relatively small. In order to solve this technical problem, an electrostatic dust collecting net is proposed. Summary of the invention

[0003] The object of the present invention is to provide an electrostatic dust collecting net to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] An electrostatic dust collecting net comprises: a frame, a plurality of first integrated chips and a plurality of second integrated chips alternately arranged inside the frame, and a power supply device, wherein the first integrated chips are connected to a first end of a power output terminal of the power supply device, and the second integrated chips are connected to a second end of the power output terminal of the power supply device, wherein the level values ​​of the first end and the second end of the power output terminal of the power supply device are alternately switched.

[0006] As a further solution of the present invention: the power supply device includes a control chip, a level switching circuit and a power supply, the output end of the power supply is connected to the first integrated chip and the second integrated chip; the control chip is connected to the level switching circuit, and the level switching circuit is connected to the connecting circuit; the first integrated chip and the second integrated chip are both connected to the connecting circuit.

[0007] As a further solution of the present invention: the connecting circuit includes an AC terminal and a BC terminal, the AC terminal is connected to the base of the first transistor, the collector of the first transistor is connected to the first ends of the first rectifier circuit and the second rectifier circuit, the third end of the first rectifier circuit is connected to the third end of the second rectifier circuit, and the third end of the first rectifier circuit is connected to the first integrated chip, the second end of the first rectifier circuit is connected to the high voltage output end of the power supply; the second end of the second rectifier circuit is connected to HGND; the emitter of the first transistor is grounded; the BC terminal is connected to the base of the second transistor, the collector of the second transistor is connected to the first ends of the fourth rectifier circuit and the fifth rectifier circuit, the third end of the fourth rectifier circuit is connected to the third end of the fifth rectifier circuit, and the third end of the fourth rectifier circuit is connected to the second integrated chip, the second end of the fourth rectifier circuit is connected to the high voltage output end of the power supply; the second end of the fifth rectifier circuit is connected to HGND; the emitter of the second transistor is grounded.

[0008] As a further solution of the present invention: the first transistor and the second transistor are both NPN transistors.

[0009] As a further solution of the present invention: the AC terminal and the BC terminal are respectively connected to two output terminals of the level switching circuit.

[0010] As a further solution of the present invention: a first resistor is connected in series to the base of the first transistor, and a second resistor is connected between the base and the emitter of the first transistor.

[0011] As a further solution of the present invention: a third resistor is connected in series to the base of the second triode, and a fourth resistor is connected between the base and the emitter of the second triode.

[0012] Compared with the prior art, the beneficial effect of the present invention is that: the level values ​​of the first integrated chip and the second integrated chip are switched through the power supply device, so that the first integrated chip is at a high level and the second integrated chip is at a low level for a period of time, and then the levels of the first integrated chip and the second integrated chip are switched, so that the first integrated chip is at a low level and the second integrated chip is at a high level, so that the first integrated chip and the second integrated chip are switched to collect dust, and the dust collection amount is greater than that of the single plate dust collection in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The figure is a schematic structural diagram of an electrostatic dust collecting net according to an embodiment of the present invention.

[0014] Figure 2 The present invention is a control principle diagram of an electrostatic dust collecting net according to an embodiment of the present invention.

[0015] Figure 3The present invention is a schematic structural diagram of a connection circuit in an electrostatic dust collecting net according to an embodiment of the present invention.

[0016] In the figure: 1-frame, 2-first integrated chip, 3-second integrated chip, 4-power supply device, 51-first transistor, 52-first rectifier circuit, 53-second rectifier circuit, 54-fourth rectifier circuit, 55-fifth rectifier circuit, 56-second transistor, 57-first resistor, 58-second resistor, 59-third resistor, 60-fourth resistor. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Example 1

[0019] See also Figures 1 to 3 , a structural diagram of an electrostatic dust collecting net provided in Example 1 of the present invention, the electrostatic dust collecting net comprises: a frame 1, a plurality of first integrated chips 2 and a plurality of second integrated chips 3 alternately arranged inside the frame 1, and a power supply device 4, wherein the first integrated chip 2 is connected to a first end of a power output terminal of the power supply device 4, and the second integrated chip 3 is connected to a second end of a power output terminal of the power supply device 4, wherein the level values ​​of the first end and the second end of the power output terminal of the power supply device 4 are alternately switched.

[0020] The present invention uses the power supply device 4 to switch the level values ​​of the first integrated chip 2 and the second integrated chip 3, so that the first integrated chip 2 is at a high level and the second integrated chip 3 is at a low level for a period of time, and then switches the levels of the first integrated chip 2 and the second integrated chip 3, so that the first integrated chip 2 is at a low level and the second integrated chip 3 is at a high level. In this way, the first integrated chip 2 and the second integrated chip 3 are switched to collect dust. Compared with the single plate dust collection in the prior art, the dust collection amount is larger.

[0021] In some embodiments, the power supply device 4 includes a control chip, a level switching circuit and a power supply, the output end of the power supply is connected to the first integrated chip 2 and the second integrated chip 3; the control chip is connected to the level switching circuit, the level switching circuit is connected to the connecting circuit; the first integrated chip 2 and the second integrated chip 3 are both connected to the connecting circuit. The control chip is set to control the level switching circuit to switch the output of high and low voltages.

[0022] In some embodiments, the connection circuit includes an AC terminal and a BC terminal, the AC terminal is connected to the base of the first transistor 51, the collector of the first transistor 51 is connected to the first terminal of the first rectifier circuit 52 and the second rectifier circuit 53, the third terminal of the first rectifier circuit 52 is connected to the third terminal of the second rectifier circuit 53, and the third terminal of the first rectifier circuit 52 is connected to the first integrated chip 2, the second terminal of the first rectifier circuit 52 is connected to the high voltage output terminal of the power supply; the second terminal of the second rectifier circuit 53 is connected to HGND; the first The emitter of the transistor 51 is grounded; the BC end is connected to the base of the second transistor 56, the collector of the second transistor 56 is connected to the first ends of the fourth rectifier circuit 54 and the fifth rectifier circuit 55, the third end of the fourth rectifier circuit 54 is connected to the third end of the fifth rectifier circuit 55, and the third end of the fourth rectifier circuit 54 is connected to the second integrated chip 3, the second end of the fourth rectifier circuit 54 is connected to the high voltage output end of the power supply; the second end of the fifth rectifier circuit 55 is connected to HGND; the emitter of the second transistor 56 is grounded.

[0023] In some embodiments, the first transistor 51 and the second transistor 56 are both NPN transistors.

[0024] In some embodiments, the AC terminal and the BC terminal are respectively connected to two output terminals of the level switching circuit.

[0025] In some embodiments, a first resistor 57 is connected in series to the base of the first transistor 51 to limit the current and stabilize the amplification factor. A second resistor 58 is connected between the base and the emitter of the first transistor 51.

[0026] In some embodiments, a third resistor 59 is connected in series to the base of the second transistor 56 to limit the current and stabilize the amplification factor. A fourth resistor 60 is connected between the base and emitter of the second transistor 56.

[0027] The working principle of the present invention is:

[0028] The control chip controls the level switching circuit to switch the levels of the two output terminals. When the AC terminal is initially at a high level and the BC terminal is at a low level, the first rectifier circuit 52 and the fifth rectifier circuit 55 are turned on, and the fourth rectifier circuit 54 and the second rectifier circuit 53 are turned off. At this time, the first integrated chip 2 is VH-, and the second integrated chip 3 is HGND. After running for a period of time, dust will accumulate on the second integrated chip 3; then switch the voltage, the AC terminal is at a ground level, and the BC terminal is at a high level, the first transistor 51 and the second rectifier circuit 53 are turned on, and the first rectifier circuit 52 and the fifth rectifier circuit 55 are turned off. At this time, the second integrated chip 3 is VH-, and the first integrated chip 2 is HGND. After running for a period of time, dust will accumulate on the first integrated chip 2.

[0029] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0031] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0033] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0034] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An electrostatic dust collecting net, characterized in that: include: A frame (1), a plurality of first integrated chips (2) and a plurality of second integrated chips (3) alternately arranged inside the frame (1), and a power supply device (4), wherein the first integrated chip (2) is connected to a first end of a power output terminal of the power supply device (4), and the second integrated chip (3) is connected to a second end of the power output terminal of the power supply device (4), wherein the level values ​​of the first end and the second end of the power output terminal of the power supply device (4) are alternately switched.

2. An electrostatic dust collecting net according to claim 1, characterized in that: The power supply device (4) comprises a control chip, a level switching circuit and a power supply, wherein the output end of the power supply is connected to a first integrated chip (2) and a second integrated chip (3); the control chip is connected to the level switching circuit, and the level switching circuit is connected to a connecting circuit; and the first integrated chip (2) and the second integrated chip (3) are both connected to the connecting circuit.

3. An electrostatic dust collecting net according to claim 2, characterized in that: The connection circuit comprises an AC terminal and a BC terminal, the AC terminal is connected to the base of the first triode (51), the collector of the first triode (51) is connected to the first end of the first rectifier circuit (52) and the first end of the second rectifier circuit (53), the third end of the first rectifier circuit (52) is connected to the third end of the second rectifier circuit (53), and the third end of the first rectifier circuit (52) is connected to the first integrated chip (2), the second end of the first rectifier circuit (52) is connected to the high voltage output end of the power supply; the second end of the second rectifier circuit (53) is connected to HGND; the first triode (51) ) is grounded; the BC terminal is connected to the base of the second triode (56); the collector of the second triode (56) is connected to the first ends of the fourth rectifier circuit (54) and the fifth rectifier circuit (55); the third end of the fourth rectifier circuit (54) is connected to the third end of the fifth rectifier circuit (55); the third end of the fourth rectifier circuit (54) is connected to the second integrated chip (3); the second end of the fourth rectifier circuit (54) is connected to the high voltage output end of the power supply; the second end of the fifth rectifier circuit (55) is connected to HGND; the emitter of the second triode (56) is grounded.

4. An electrostatic dust collecting net according to claim 3, characterized in that: The first transistor (51) and the second transistor (56) are both NPN transistors.

5. An electrostatic dust collecting net according to claim 3, characterized in that: The AC terminal and the BC terminal are respectively connected to two output terminals of the level switching circuit.

6. An electrostatic dust collecting net according to claim 5, characterized in that: The base of the first triode (51) is connected in series with a first resistor (57), and a second resistor (58) is connected between the base and the emitter of the first triode (51).

7. An electrostatic dust collecting net according to claim 5, characterized in that: The base of the second triode (56) is connected in series with a third resistor (59), and a fourth resistor (6) is connected between the base and the emitter of the second triode (56).

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