An electric leakage prevention circuit and method in a str state
By implementing leakage protection circuits and methods, the leakage problem between the SOC module and peripheral modules in STR state was solved, enabling power management in STR state, reducing malfunctions and quality issues, and improving product reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN HANGSHENG AUTOMOTIVE ELECTRONICS CO LTD
- Filing Date
- 2024-08-01
- Publication Date
- 2026-06-16
AI Technical Summary
In STR mode, leakage current can easily occur between the SOC module and peripheral modules, leading to faults that are difficult to troubleshoot.
Design a leakage current prevention circuit that controls the electrical signal connection between the SOC module and the peripheral module through the coordinated operation of the main control power supply, STR management module, power management module and peripheral management module. Ensure that the SOC module and the peripheral module are disconnected from power flow in STR state. Use pull-up resistors, pull-down resistors and level conversion module for level management.
It effectively prevents electrical leakage, reduces malfunctions during the design process, shortens the development cycle, improves customer satisfaction, and reduces user complaints.
Smart Images
Figure CN119200801B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of leakage protection design technology, and more specifically, to a leakage protection circuit and method in STR state. Background Technology
[0002] As automotive equipment demands increasingly faster system startup, a new STR state has been added. STR (Suspend to RAM) is a special power operation mode where all CPU cores, controllers, and IP cores enter a special power mode. Simultaneously, the SOC's internal bus clock drops to its lowest operating frequency, most of the PMIC's power supply is shut down, and the external DDR enters self-refresh mode. The system can switch back to normal power mode via external signals / interrupts using AOP (Always On Processor). In STR state, because the SOC's GPIO power supply is normal and GPIOs are connected to peripherals, improper handling of GPIOs when entering STR state can cause leakage. Many peripherals share one or more power supplies; if leakage occurs on the common power supply, it will spread between modules. Leakage can cause numerous faults that are difficult to troubleshoot. Summary of the Invention
[0003] One objective of this invention is to provide a leakage protection circuit in the STR state, solving the technical problem that leakage occurs when the SOC enters the STR state in the prior art; another objective of this invention is to provide a leakage protection method in the STR state.
[0004] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:
[0005] The first aspect of the present invention provides a leakage protection circuit in STR state, which manages leakage protection between a SOC module and a peripheral module. The SOC module and the peripheral module are bidirectionally electrically connected, and the circuit includes a main control power supply, an STR trigger module, an STR management module, a power management module, and a peripheral management module, wherein:
[0006] The main control power supply provides power to the SOC module and is electrically connected to the SOC module.
[0007] The input terminal of the STR management module is electrically connected to the signal output terminal of the main control power supply and the output terminal of the STR trigger module, respectively. The output terminal of the STR management module is electrically connected to the control terminal of the SOC module and the control terminal of the power management module, respectively.
[0008] The control terminal of the peripheral management module is electrically connected to the output terminal of the SOC module, and the output terminal of the peripheral management module is electrically connected to the control terminal of the power management module.
[0009] The peripheral management module configures the connection method between the peripheral module and the SOC module so that when the SOC module enters the STR state, the electrical signal between the peripheral module and the peripheral module is disconnected, and the power supply of the SOC module will not flow to the peripheral module.
[0010] The power management module configures the connection method between the peripheral module and the SOC module so that when the SOC module enters the STR state and disconnects the peripheral module, the power of the peripheral module will not flow to the SOC module.
[0011] In the above technical means, when the SOC module enters the STR state, the peripheral management module is started, and the peripheral management module controls the power management module. The power management module manages the power of the peripheral module, so that the power of the peripheral module does not flow to the SOC module.
[0012] Furthermore, the STR management module and the SOC module are connected via an SPI bus electrical signal.
[0013] Furthermore, it also includes a GPIO management module, the control terminal of which is electrically connected to the output terminal of the peripheral management module.
[0014] Furthermore, it also includes a bus management module, the control terminal of which is electrically connected to the output terminal of the peripheral management module.
[0015] Furthermore, it also includes an STR exception handling module, the control terminal of which is electrically connected to the output terminal of the peripheral management module.
[0016] Furthermore, when the voltage level of the peripheral module is the same as that of the SOC module, the power management module configures the connection method between the peripheral module and the SOC module, including:
[0017] The power management module uses the power supply of the peripheral module and is equipped with pull-up and pull-down resistors.
[0018] Furthermore, when the voltage level of the peripheral module is different from that of the SOC module, the power management module configures the connection method between the peripheral module and the SOC module, including:
[0019] A level conversion module is provided between the SOC module and the peripheral module.
[0020] A second aspect of the present invention provides a method for preventing leakage current in an STR state, the method being applied to a leakage current prevention circuit in the STR state, the method comprising the following steps:
[0021] The STR trigger module generates an STR trigger signal and sends it to the STR management module;
[0022] The STR management module transmits the STR trigger signal to the SOC module;
[0023] After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module;
[0024] After the SOC module enters the STR state, the main control power supply sends a SOC enters STR flag signal to the STR management module;
[0025] After receiving the SOC STR entry flag signal, the STR management module starts the peripheral management module;
[0026] The peripheral management module controls the power management module to configure the connection method between the peripheral module and the SOC module.
[0027] Furthermore, when the SOC module enters the STR state, it retains the wake-up signal trigger source. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up signal to the STR trigger module. The STR trigger module sends an exit STR signal to the STR management module. After the STR management module sends a wake-up signal to the SOC module, it wakes up the SOC module. After the SOC module is woken up, it starts the peripheral management module and performs power-on processing.
[0028] Furthermore, if the SOC module encounters an anomaly when entering or exiting the STR state, the STR anomaly handling module is used for diagnosis and recovery processing.
[0029] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:
[0030] This invention provides a leakage protection circuit in the STR state, which can greatly reduce various problems caused by leakage when the SOC module enters the STR state during the design process, shorten the development cycle, effectively prevent various quality problems caused by leakage, reduce user complaints, reduce company losses, and improve customer satisfaction. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of a leakage protection circuit structure in the STR state provided by an embodiment of the present invention;
[0032] Figure 2 This is a schematic diagram of another leakage protection circuit structure in the STR state provided by an embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram of the structure for setting pull-up resistors and pull-down resistors according to an embodiment of the present invention;
[0034] Figure 4 This is a connection diagram of the setting level conversion module provided in an embodiment of the present invention;
[0035] Figure 5 This is a flowchart illustrating a leakage prevention method in the STR state provided by an embodiment of the present invention. Detailed Implementation
[0036] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent.
[0037] To better illustrate this embodiment, some parts in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions;
[0038] It will be understood by those skilled in the art that certain well-known structures and their descriptions may be omitted in the accompanying drawings.
[0039] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0040] Example
[0041] This embodiment provides a leakage protection circuit in the STR state, such as... Figure 1 and Figure 2 As shown, leakage current protection management is implemented for the SOC module and peripheral modules. The SOC module and peripheral modules are bidirectionally electrically connected, including a main control power supply, an STR trigger module, an STR management module, a power management module, and a peripheral management module, wherein:
[0042] The main control power supply provides power to the SOC module and is electrically connected to the SOC module.
[0043] The input terminal of the STR management module is electrically connected to the signal output terminal of the main control power supply and the output terminal of the STR trigger module, respectively. The output terminal of the STR management module is electrically connected to the control terminal of the SOC module and the control terminal of the power management module, respectively.
[0044] The control terminal of the peripheral management module is electrically connected to the output terminal of the SOC module, and the output terminal of the peripheral management module is electrically connected to the control terminal of the power management module.
[0045] The peripheral management module configures the connection method between the peripheral module and the SOC module so that when the SOC module enters the STR state, the electrical signal between the peripheral module and the peripheral module is disconnected, and the power supply of the SOC module will not flow to the peripheral module.
[0046] The power management module configures the connection method between the peripheral module and the SOC module so that when the SOC module enters the STR state and disconnects the peripheral module, the power of the peripheral module will not flow to the SOC module.
[0047] In a specific embodiment, the main control power supply has the function of supplying power to the SOC module, receiving notification of the SOC module entering the STR state, and sending an STR entry flag signal to the STR management module.
[0048] The STR trigger module has the ability to generate STR trigger signals and STR deactivation signals, and then sends the generated STR trigger signals and STR deactivation signals to the STR management module;
[0049] When the STR management module receives the STR trigger signal, it sends a signal to the SOC module via the SPI bus port. At the same time, it receives the SOC enters STR flag signal from the main power supply. When the STR management module receives the exit STR signal, it sends a wake-up signal to the SOC module.
[0050] The SOC module is the core unit of the vehicle-mounted equipment, and it mainly has three working states: normal working state, STR working state, and sleep working state. When it receives the STR entry trigger signal transmitted by the STR management module through the SPI bus, the SOC module will start the peripheral management module and enter the STR state;
[0051] The peripheral management module is responsible for managing the power management module;
[0052] The power management module manages the power-on and power-off of all power modules, based on a pre-set control sequence.
[0053] In a further embodiment, the power supply in the system generally includes two parts. One part of the power supply is controlled by the SOC, such as the power supply of the peripherals of the SOC, which is generally controlled by the peripheral management module. The other part of the power supply is controlled by the STR management module. The STR management module includes the MCU, CAN and some hard-wired trigger signals, such as the trigger signal to enter the STR and the trigger signal to exit the STR. The MCU mainly performs low-power management and controls the main primary power supply and the PMIC power supply of the SOC.
[0054] In a further embodiment, the STR management module and the SOC module are connected via an SPI bus electrical signal.
[0055] In a further embodiment, a GPIO management module is also included, wherein the control terminal of the GPIO management module is electrically connected to the output terminal of the peripheral management module.
[0056] In a specific embodiment, the GPIO management module is controlled and managed by the peripheral management module. After power-on, it configures and manages all GPIOs. When the SOC module enters the STR state, it processes all GPIOs according to pre-set pull-up / pull-down, input / output, or disable settings, specifically:
[0057] When entering the STR (Structured Array of Independent Components), if there is an external pull-up resistor, the pull-up power supply will be turned off when entering the STR. Therefore, this type of SOC GPIO generally needs to be disabled when entering the STR. If there is no external pull-up or pull-down resistor for the GPIO port, it is generally pulled down when entering the STR. If there is an external pull-down resistor for the GPIO port, it needs to be disabled. If some GPIO ports use the SOC's own IO power supply for pull-up and there is no external pull-down resistor, this power supply will not be turned off when entering the STR, so it is generally set to pull up and output low.
[0058] In a further embodiment, a bus management module is also included, wherein the control terminal of the bus management module is electrically connected to the output terminal of the peripheral management module.
[0059] In a specific embodiment, the bus management module is controlled and managed by the peripheral management module. After power-on, it configures and manages the communication bus between modules to ensure normal communication during normal operation. Upon entering the STR (Short Streaming Service), it processes the bus according to a pre-defined bus processing method, specifically:
[0060] Buses typically include serial ports and I2C. When these bus ports enter STR, they generally need to be configured as ordinary GPIOs. The configuration of GPIO ports is the same as above, and the configuration should be made according to the external connection status and the status of the pull-up power supply.
[0061] In a further embodiment, an STR exception handling module is also included, wherein the control terminal of the STR exception handling module is electrically connected to the output terminal of the peripheral management module.
[0062] In a specific embodiment, the STR anomaly handling module is controlled and managed by the peripheral management module. It performs diagnosis when entering or exiting an STR state anomaly and performs recovery processing on the anomaly.
[0063] In a further embodiment, when the power level of the peripheral module is the same as that of the SOC module, the power management module configures the connection method between the peripheral module and the SOC module, including:
[0064] The power management module uses the power supply of the peripheral module and is equipped with pull-up and pull-down resistors.
[0065] In specific embodiments, such as Figure 3 As shown, the peripheral module and the SOC module are connected via resistors R1 and R2. A resistor R3 pulls the peripheral module's power supply up to the peripheral module's power supply, ensuring that when the peripheral is powered off during STR (Strong Array of Independent Devices) operation, power will not flow to the SOC through the pull-up resistor. Simultaneously, after configuring the SOC's GPIO and bus ports according to the peripheral management module's configuration method, SOC power will not flow to the peripheral. A resistor R4 pulls the peripheral module down to the ground system. Connections that do not require pull-up resistors should be pulled down to the ground system as much as possible to ensure that the connection line level is low when the SOC module enters STR state.
[0066] In a further embodiment, when the voltage level of the peripheral module is different from that of the SOC module, the power management module configures the connection method between the peripheral module and the SOC module, including:
[0067] A level conversion module is provided between the SOC module and the peripheral module.
[0068] In specific embodiments, such as Figure 4 As shown, the level conversion module converts signals of different voltages to ensure normal communication between the SOC module and peripheral module 2 when the voltage levels are different. The selected level conversion chip must not leak current when there is no power supply; specifically, the 74AVCH4T245PW-Q100 level conversion chip can be used.
[0069] The working principle of the entire circuit is as follows:
[0070] The STR trigger module sends an STR entry message. Upon receiving the STR entry trigger signal, the STR management module transmits the message to the SOC module via the SPI bus. The SOC, upon receiving the information from the bus, activates the peripheral management module. This module processes all GPIOs and buses connected to the power supply and peripherals according to pre-defined methods, including pull-up / pull-down configuration, input / output configuration, or disable configuration, ensuring no leakage current occurs between the SOC and the peripherals. For peripheral module connections, the pull-up power supply uses the peripheral module's power supply to ensure that when the peripheral is powered off during STR entry, power will not flow to the SOC through the pull-up resistor. Simultaneously, after configuring the SOC's GPIOs and bus ports according to the above configuration method of the peripheral management module, SOC power will not flow to the peripherals. Connections that do not require pull-up resistors are pulled down to the ground system as much as possible to ensure that the connection line level is low when entering STR. When the peripheral module's level is inconsistent with the SOC module's level, a level conversion chip that does not generate leakage current when not powered is selected. When entering STR, the power supply to the level conversion chip is disconnected to ensure no bidirectional leakage current occurs between the SOC and the peripherals. When the SOC enters the STR (Switchboard Execution System), the wake-up signal trigger source is retained, and the main power supply is notified. The main power supply then sends an STR entry flag signal to the STR management module. The STR will participate in power management, powering down any residual power after the SOC peripheral management module has processed it. When the STR trigger module sends an exit STR message, the STR management module, upon receiving the message, directly sends a wake-up signal to the SOC. Upon receiving the wake-up signal, the SOC starts the peripheral management module and poweres up the power according to the pre-set method, restoring the GPIO and bus to their normal operating mode configuration. When an abnormal exit from the STR state occurs, the STR exception handling module initiates diagnostics and recovery.
[0071] This embodiment also provides a method for preventing leakage current in the STR state, such as Figure 5 As shown, the leakage protection method is applied to the leakage protection circuit in the STR state, and the leakage protection method includes the following steps:
[0072] The STR trigger module generates an STR trigger signal and sends it to the STR management module;
[0073] The STR management module transmits the STR trigger signal to the SOC module;
[0074] After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module;
[0075] After the SOC module enters the STR state, the main control power supply sends a SOC enters STR flag signal to the STR management module;
[0076] After receiving the SOC STR entry flag signal, the STR management module starts the peripheral management module;
[0077] The peripheral management module controls the power management module to configure the connection method between the peripheral module and the SOC module.
[0078] In a further embodiment, when the SOC module enters the STR state, it retains the wake-up signal trigger source. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up signal trigger to the STR trigger module. The STR trigger module sends an exit STR signal to the STR management module. After the STR management module sends a wake-up signal to the SOC module, it wakes up the SOC module. After the SOC module is woken up, it starts the peripheral management module and performs power-on processing.
[0079] In a further embodiment, if the SOC module encounters an anomaly when entering or exiting the STR state, the STR anomaly handling module is used for diagnosis and recovery processing.
[0080] The same or similar labels correspond to the same or similar parts;
[0081] The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent.
[0082] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. An anti-creeping circuit in a state of STR, for anti-creeping management of a SOC module and a peripheral module, the SOC module and the peripheral module being connected by bidirectional electrical signals, characterized in that, The SOC module is powered by a main control power supply, an STR trigger module, an STR management module, a power management module and a peripheral management module. The main control power supply is connected with the SOC module by an electrical signal. The input end of the STR management module is connected with the signal output end of the main control power supply and the output end of the STR trigger module by an electrical signal. The control end of the peripheral management module is connected with the output end of the SOC module by an electrical signal. The peripheral management module configures the connection mode of the peripheral module and the SOC module, so that the electrical signal of the peripheral module is disconnected when the SOC module enters the STR state. The power management module configures the connection mode of the peripheral module and the SOC module, so that the power of the peripheral module does not flow to the SOC module when the peripheral module is disconnected when the SOC module enters the STR state. The control end of the GPIO management module is connected with the output end of the peripheral management module by an electrical signal. The GPIO management module is controlled and managed by the peripheral management module. The STR management module is connected with the SOC module by an electrical signal through an SPI bus.
2. The electric leakage prevention circuit in the state of STR according to claim 1, characterized by, The power management module is also controlled by the STR management module.
3. The electric leakage prevention circuit in the state of STR according to claim 1, characterized by, The control end of the bus management module is connected with the output end of the peripheral management module by an electrical signal.
4. The circuit for preventing leakage current in the state of STR according to claim 1, wherein The control end of the STR exception processing module is connected with the output end of the peripheral management module by an electrical signal.
5. The electric leakage prevention circuit in the state of STR according to claim 1, characterized by, When the electrical level of the peripheral module is the same as that of the SOC module, the power management module configures the connection mode of the peripheral module and the SOC module, including:
6. The electric leakage prevention circuit in the state of STR according to any one of claims 1 to 5, characterized by, The power management module uses the power of the peripheral module, and sets the pull-up resistor and the pull-down resistor. When the electrical level of the peripheral module is different from that of the SOC module, the power management module configures the connection mode of the peripheral module and the SOC module, including:
7. The electric leakage prevention circuit in the state of STR according to any one of claims 1 to 5, characterized by, A level conversion module is provided between the SOC module and the peripheral module.
8. A method for preventing leakage current in a state of STR, characterized by, The leakage protection method is applied to the leakage protection circuit in the STR state as described in any one of claims 1 to 7, and the leakage protection method includes the following steps: The STR trigger module generates an STR trigger signal and sends it to the STR management module; The STR management module transmits the STR trigger signal to the SOC module; After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module; After the SOC module enters the STR state, the main control power supply sends a SOC enters STR flag signal to the STR management module; After receiving the SOC STR entry flag signal, the STR management module starts the peripheral management module; The peripheral management module controls the power management module to configure the connection method between the peripheral module and the SOC module.
9. The method of preventing a leakage current in the state of the STR according to claim 8, wherein When the SOC module enters the STR state, it retains the wake-up signal trigger source. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up trigger signal to the STR trigger module. The STR trigger module sends an exit STR signal to the STR management module. After the STR management module sends a wake-up signal to the SOC module, it wakes up the SOC module. After the SOC module is woken up, it starts the peripheral management module and performs power-on processing.