Display driving circuit, display driving chip, display module and electronic device

Abstract

The application provides a display driving circuit, a display driving chip, a display module and an electronic device. The display driving circuit comprises a first digital-to-analog converter (DAC), a second DAC, a driving enhancement circuit and a buffer. The first DAC is configured to receive a first digital signal and perform digital-to-analog conversion on the first digital signal. The second DAC is connected to the output end of the first DAC and configured to receive a second digital signal and perform analog-to-digital conversion on the second digital signal. The buffer is configured to output a voltage signal, and the input end of the buffer is connected to the output end of the second DAC. The driving enhancement circuit is connected to the output end of the second DAC and configured to charge the output end of the second DAC. The application can reduce the brightness inversion of the pixel points on the display panel.

Description

Technical Field

[0001] This application relates to the field of display driver technology, and in particular to a display driver circuit, a display driver chip, a display module, and an electronic device. Background Technology

[0002] The source drive circuit is a circuit module integrated into the display driver chip. It receives digital signals and converts them into analog signals. The grayscale voltage corresponding to the analog signal is then applied to the pixel capacitors of the display panel, causing the pixel capacitors to emit brightness corresponding to the analog signal. To make the image displayed on the display panel more delicate and accurate, the grayscale voltage is usually divided into multiple levels.

[0003] Source driver circuits typically include a digital-to-analog converter (DAC). The DAC converts digital signals into corresponding analog signals for output. The more grayscale voltage levels there are, the more complex the DAC's structure and the larger its size. Therefore, to save area in the display driver chip, interpolation technology is usually used to convert digital signals to analog signals. That is, for multiple voltage levels, some levels are non-interpolated voltages, and others are interpolated voltages, with multiple interpolated voltages evenly interpolated between each pair of adjacent non-interpolated voltages.

[0004] However, in related technologies, there are often cases where the non-interpolation voltage is lower than the previous interpolation voltage, which causes the brightness of the pixels on the display panel to reverse, resulting in dark stripes on the display panel and making it impossible to achieve accurate image display. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a display driving circuit, a display driving chip, a display module, and an electronic device, which can reduce the brightness reversal of pixels on the display panel.

[0006] A first aspect of this application provides a display driving circuit, comprising: a first digital-to-analog converter (DAC), a second DAC, a driving enhancement circuit, and a buffer. The output terminal of the first DAC is connected to the input terminal of the second DAC, the output terminal of the second DAC is connected to the input terminal of the buffer, and the output terminal of the driving enhancement circuit is connected to the output terminal of the second DAC.

[0007] The display driver circuit of this application can be applied to a display driver chip, which further includes a timing control circuit that can send timing signals to the display driver circuit. A first DAC is used to receive a first digital signal, which may be several high-order bits of the timing signal. The first DAC performs analog-to-digital conversion on the first digital signal to obtain a first voltage signal. A second DAC is used to receive a second digital signal and the first voltage signal, where the second digital signal may be several low-order bits of the timing signal. The second DAC performs analog-to-digital conversion on the second digital signal and, based on the conversion result, divides the first voltage signal into multiple second voltage signals and outputs them. A drive enhancement circuit is used to charge the output of the second DAC, i.e., to enhance the voltage of the multiple second voltage signals output by the second DAC. A buffer is used to receive multiple second voltage signals and output one voltage signal (hereinafter referred to as the third voltage signal for ease of distinction). During the charging process of the drive enhancement circuit, when the voltage corresponding to the timing signal is a first-type voltage (hereinafter referred to as the non-interpolation voltage for ease of description), the drive enhancement circuit can charge the output of the second DAC; when the voltage corresponding to the timing signal is a second-type voltage (hereinafter referred to as the interpolation voltage for ease of description), the drive enhancement circuit can not charge the output of the second DAC. Therefore, when the voltage of the third voltage signal is a non-interpolation voltage, the voltage at the output of the second DAC can be increased, ensuring that the current non-interpolation voltage is always greater than the interpolation voltage of the previous level. This reduces the brightness inversion of pixels on the display panel and reduces the appearance of dark stripes on the display panel, thereby achieving accurate image display.

[0008] In some embodiments of this application, the drive enhancement circuit includes a first capacitor. A first terminal of the first capacitor is connected to a first power supply, and a second terminal of the first capacitor is connected to the output terminal of a second DAC. The first power supply can charge the first capacitor, meaning the potential of the first terminal of the first capacitor is the same as the potential of the output terminal of the first power supply. Furthermore, after the first power supply charges the first capacitor for a period of time, the potential of the second terminal of the first capacitor becomes the same as the potential of the first terminal. Since the second terminal of the first capacitor is connected to the output terminal of the second DAC, the potential of the output terminal of the second DAC is the same as the potential of the second terminal of the first capacitor, thus enabling the first capacitor to charge the output terminal of the second DAC. The drive enhancement circuit is implemented through the first capacitor, making the structure of this scheme relatively simple and easy to implement. In addition, when the potential of the output terminal of the second DAC is the same as the potential of the second terminal of the first capacitor, and after the first power supply stops charging the first capacitor, under the action of the first capacitor, the potential of the output terminal of the second DAC slowly decreases, and the voltage of the pixel capacitor also slowly decreases to slightly higher than its previous interpolation voltage. Before the pixel capacitor is fully charged, the current non-interpolation voltage is always higher than the previous interpolation voltage, thereby better preventing brightness reversal of pixels on the display panel.

[0009] Based on this, the drive enhancement circuit also includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to a second power supply, and the second terminal of the second capacitor is connected to the output terminal of the second DAC. The first terminal of the third capacitor is connected to a third power supply, and the second terminal of the third capacitor is connected to the output terminal of the second DAC. Since the voltage of the third voltage signal output by the buffer may be one of multiple non-interpolation voltages, and the magnitudes of different non-interpolation voltages are different, when the drive enhancement circuit also includes a second capacitor and a third capacitor, and the first terminal of the first capacitor is connected to the first power supply, the first terminal of the second capacitor is connected to the second power supply, and the first terminal of the third capacitor is connected to the third power supply, that is, the first terminals of the first, second, and third capacitors are respectively connected to different power supplies, the number of capacitors charging the output terminal of the second DAC can be controlled by each power supply, thereby controlling the degree of charging the output terminal of the second DAC, and thus achieving different degrees of charging for different non-interpolation voltages, so that the voltage of the third voltage signal output from the buffer after charging is closer to the theoretical value of the corresponding non-interpolation voltage, thereby improving the accuracy of brightness control of the display panel pixels.

[0010] In some embodiments of this application, the drive enhancement circuit further includes a first capacitor state control circuit. The input terminal of the first capacitor state control circuit is connected to the second terminal of the first capacitor, and the output terminal of the first capacitor state control circuit is connected to the output terminal of the second DAC. The first capacitor state control circuit is used to control whether the first capacitor charges the output terminal of the second DAC. In specific implementations, when the voltage corresponding to the timing signal is a non-interpolation voltage, the first capacitor state control circuit controls the first capacitor to charge the output terminal of the second DAC; when the voltage corresponding to the timing signal is an interpolation voltage, the first capacitor state control circuit controls the first capacitor not to charge the output terminal of the second DAC, thereby making the charging of the output terminal of the second DAC more accurate. In addition, when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply charges the first capacitor, and the first capacitor does not need to charge the output terminal of the second DAC; when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply has completed charging the first capacitor, and the first capacitor can charge the output terminal of the second DAC, thereby avoiding additional clock cycles and improving the charging speed of the pixel capacitor.

[0011] In a specific implementation, the first capacitor state control circuit can receive the lower bits of the digital signal in the timing signal and determine whether the corresponding voltage is an interpolation voltage or a non-interpolation voltage based on the lower bits of the digital signal. Thus, when the voltage corresponding to the timing signal is a non-interpolation voltage, the circuit controls the first capacitor to charge the output terminal of the second DAC.

[0012] Furthermore, the drive enhancement circuit also includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to a first power supply, and the first terminal of the third capacitor is also connected to the first power supply. The drive enhancement circuit further includes a second capacitor state control circuit and a third capacitor state control circuit. The input terminal of the second capacitor state control circuit is connected to the second terminal of the second capacitor, and the output terminal of the second capacitor state control circuit is connected to the output terminal of the second DAC. Thus, the second capacitor state control circuit can control whether the second capacitor charges the output terminal of the second DAC. The input terminal of the third capacitor state control circuit is connected to the second terminal of the third capacitor, and the output terminal of the third capacitor state control circuit is connected to the output terminal of the second DAC. Thus, the third capacitor state control circuit can control whether the third capacitor charges the output terminal of the second DAC. Therefore, in this application, when the drive enhancement circuit includes multiple capacitors, each capacitor state control circuit can control whether the corresponding capacitor charges the output terminal of the second DAC.

[0013] In some embodiments of this application, the first capacitor state control circuit includes a first switching transistor. The first terminal of the first switching transistor is connected to the second terminal of the first capacitor, and the second terminal of the first switching transistor is connected to the output terminal of the second DAC. The control terminal of the first switching transistor can be used to receive the low-order digital signal in the timing signal. In one example, when the low-order digital signal is 0, the first switching transistor is off; when the low-order digital signal is 1, the first switching transistor is on. In another example, when the low-order digital signal is 1, the first switching transistor is off; when the low-order digital signal is 0, the first switching transistor is on. When the first switching transistor is on, it can connect the second terminal of the first capacitor to the output terminal of the second DAC and charge the output terminal of the second DAC. This scheme is simple in structure, easy to implement, and relatively reliable.

[0014] In some cases, the second DAC can receive multiple bits of digital signal from the timing signal, and each switch can receive one bit of digital signal. Therefore, in order to receive each bit of digital signal from the multiple bits of digital signal, in one embodiment, the capacitor state control circuit may further include a second switch and a third switch. The first terminal of the second switch is connected to the second terminal of the first switch, the first terminal of the third switch is connected to the second terminal of the second switch, and the second terminal of the third switch is connected to the output terminal of the second DAC. That is, the first switch, the second switch, and the third switch are connected in series. The control terminals of the first switch, the second switch, and the third switch can each receive one bit of digital signal from the multiple bits of digital signal. When each bit of digital signal is 1, the first switch, the second switch, and the third switch are all closed, thereby charging the first capacitor to the output terminal of the second DAC.

[0015] In another embodiment, the second DAC can receive two digital signals from the timing signal. The first capacitor state control circuit can then include two switching transistors, a first switching transistor and a second switching transistor. The first terminal of the second switching transistor is connected to the second terminal of the first switching transistor, and the second terminal of the second switching transistor is connected to the output terminal of the second DAC. Therefore, when the digital signals received by the control terminals of both the first and second switching transistors are 1, the first, second, and third switching transistors are all closed, allowing the first capacitor to charge the output terminal of the second DAC.

[0016] It is understood that in other embodiments, if the second DAC can receive four digital signals from the timing signal, then the first capacitor state control circuit may include four switching transistors; if the second DAC can receive five digital signals from the timing signal, then the first capacitor state control circuit may include five switching transistors; and so on.

[0017] In some embodiments of this application, the drive enhancement circuit further includes a second capacitor and a third capacitor. A first terminal of the second capacitor is connected to a first power supply, and a second terminal of the third capacitor is also connected to the first power supply. In this case, the drive enhancement circuit further includes a charging level control circuit. The second terminals of the first, second, and third capacitors are all connected to the input terminal of the charging level control circuit. The output terminal of the charging level control circuit is connected to the output terminal of the second DAC. The charging level control circuit controls the number of capacitors charging the output terminal of the second DAC. That is, the charging level control circuit can control whether the first capacitor charges the output terminal of the second DAC, control whether the second capacitor charges the output terminal of the second DAC, and control whether the third capacitor charges the output terminal of the second DAC. The first, second, and third capacitors can form a capacitor array. The more capacitors charging the output terminal of the second DAC, the larger the capacitance value of the capacitor array, and the faster the voltage build-up speed and the higher the voltage at the output terminal of the second DAC. This allows for the selection of different numbers of capacitors to charge the output of the second DAC based on the magnitude of the voltage corresponding to the timing signal, thereby controlling the degree of charging to the output of the second DAC. This enables different levels of charging for different non-interpolation voltages, making the voltage of the third voltage signal output from the buffer after charging closer to the theoretical value of the corresponding non-interpolation voltage. This, in turn, improves the accuracy of brightness control for the pixels of the display panel.

[0018] In a specific implementation, the received signal of the drive enhancement circuit can be the same as the received signal of the first DAC. For example, both are the higher bits of the timing signal. The drive enhancement circuit can determine the number of capacitors to charge the output of the second DAC based on the magnitude relationship between the higher bits of the digital signal.

[0019] Specifically, the charging level control circuit includes a fourth, a fifth, and a sixth switching transistor. The first terminal of the fourth switching transistor is connected to the second terminal of the first capacitor, and the second terminal of the fourth switching transistor is connected to the output terminal of the second DAC. The first terminal of the fifth switching transistor is connected to the second terminal of the second capacitor, and the second terminal of the fifth switching transistor is connected to the output terminal of the second DAC. The first terminal of the sixth switching transistor is connected to the second terminal of the third capacitor, and the second terminal of the sixth switching transistor is connected to the output terminal of the second DAC. In other words, the fourth switching transistor controls whether the first capacitor charges the output terminal of the second DAC, the fifth switching transistor controls whether the second capacitor charges the output terminal of the second DAC, and the sixth switching transistor controls whether the third capacitor charges the output terminal of the second DAC. For example, when the fourth, fifth, and sixth switches are all closed, the first, second, and third capacitors can all charge the output of the second DAC, meaning that three capacitors charge the output of the second DAC. When two of the fourth, fifth, and sixth switches are closed, two capacitors charge the output of the second DAC. When one of the fourth, fifth, and sixth switches is closed, one capacitor charges the output of the second DAC.

[0020] In practice, the control electrodes of the fourth, fifth, and sixth switches can each receive three bits from the higher-order digital signals. When the fourth switch receives a digital signal of 1, it closes; when it receives a digital signal of 0, it opens, allowing the first capacitor to charge the output of the second DAC. Similarly, when the fifth switch is closed, the second capacitor charges the output of the second DAC. When the sixth switch is closed, the third capacitor charges the output of the second DAC.

[0021] It is understandable that the number of capacitors in the drive enhancement circuit can be the same as the number of bits in the higher-order digital signals of the timing signal received by the first DAC. For example, when the first DAC receives the higher 6 bits of digital signal, the drive enhancement circuit may include 6 capacitors. Correspondingly, the number of switching transistors in the charging level control circuit can also be the same as the number of bits in the higher-order digital signals of the timing signal received by the first DAC, that is, also 6. This allows for more precise control of the charging level of the second DAC's output by the drive enhancement circuit.

[0022] A second aspect of this application also provides a display driver chip, including a timing control circuit and a display driver circuit according to any of the above embodiments, wherein the timing control circuit is electrically connected to the display driver circuit. The display driver chip is capable of achieving all the effects of the display driver circuit.

[0023] A third aspect of this application also provides a display module, including a display panel and the aforementioned display driver chip, wherein the display panel and the display driver chip are electrically connected. The display module is capable of achieving all the effects of the display driver chip.

[0024] A fourth aspect of this application also provides an electronic device, including a controller and the aforementioned display module, wherein the controller is electrically connected to the display module. The electronic device is capable of displaying all the effects of the module. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the display module structure in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the specific structure of the power supply, display driver chip and display panel in the embodiments of this application;

[0028] Figure 3 The voltage change curves during the charging process of the pixel capacitor are shown for non-interpolation voltage 127 and interpolation voltage 126.

[0029] Figure 4 This is a schematic diagram of the display driving circuit in an embodiment of this application;

[0030] Figure 5 for Figure 4 The diagram shows the specific structure of the display driver circuit.

[0031] Figure 6a for Figure 5 The diagram shows a specific structure of the drive enhancement circuit and its connection structure with the second DAC and the first power supply in the display drive circuit shown.

[0032] Figure 6b for Figure 5 The diagram shows another specific structure of the drive enhancement circuit in the display driver circuit shown, as well as the connection structure between the second DAC and the first power supply, the second power supply, and the third power supply.

[0033] Figure 7 The voltage change curves of non-interpolation voltage 127 and interpolation voltage 126 during the charging process of the pixel capacitor in this embodiment, and the voltage change curve of non-interpolation voltage 127 during the charging process of the pixel capacitor C when the display driving circuit 50 does not include the driving enhancement circuit 54.

[0034] Figure 8a for Figure 5 The diagram shows the third specific structure of the drive enhancement circuit and its connection structure with the second DAC and the first power supply in the display driver circuit shown.

[0035] Figure 8b for Figure 5 The diagram shows the fourth specific structure of the drive enhancement circuit in the display driver circuit shown, as well as the connection structure between the second DAC and the first power supply, the second power supply, and the third power supply.

[0036] Figure 9 for Figure 5 The diagram shows the fifth specific structure of the drive enhancement circuit and the connection structure between it and the first power supply, second power supply and third power supply of the second DAC in the display driver circuit shown.

[0037] Figure 10 for Figure 5 The diagram shows the sixth specific structure of the drive enhancement circuit and the connection structure between it and the first power supply, second power supply and third power supply of the second DAC in the display driver circuit shown.

[0038] Figure 11 for Figure 5 The diagram shows the seventh specific structure of the drive enhancement circuit and the connection structure between it and the first power supply, second power supply and third power supply of the second DAC in the display driver circuit shown.

[0039] Figure 12 for Figure 5 The diagram shows the eighth specific structure of the drive enhancement circuit in the display driver circuit, as well as the connection structure between the second DAC and the first, second, and third power supplies.

[0040] Icons: 1000 - Display driver chip; 10 - Power conversion circuit; 11 - First power supply; 12 - Second power supply; 13 - Third power supply; 20 - Reference voltage generation circuit; 30 - Timing control circuit; 40 - Gate drive circuit; 50 - Source drive circuit; 51 - First DAC; 52 - Second DAC; 53 - Buffer; 531 - Differential circuit; 5311 - Differential pair; 532 - Power amplifier; 54 - Drive enhancement circuit; 541 - First capacitor state control circuit; 542 - Second capacitor state control circuit; 543 - Third capacitor state control circuit; 544 - Charging level control circuit; 200 - Power supply; 300 - Flexible ribbon cable; 400 - Display panel; 1000 - Display module. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0043] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0044] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0045] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0047] Electronic devices typically include a display module and a controller. The display module is electrically connected to the controller, which can send control signals to the display module to control the display module to display images, text, and other information.

[0048] Here, electronic devices can be, for example, consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc., and this application embodiment does not limit this. Illustrated, the aforementioned consumer electronics can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics can be smart door locks, televisions, smart speakers, robot vacuum cleaners, etc. Automotive electronics can be car navigation systems, car displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc.

[0049] like Figure 1 As shown, the display module 1000 may include a display panel 400, a power supply 200, a display driver chip 1000, and a flexible flat cable 300. The display panel 400 and the display driver chip 1000 are connected through the flexible flat cable 300, and the power supply 200 is connected to the display driver chip 1000.

[0050] like Figure 2 As shown, the display panel 400 may include a plurality of pixel capacitors C arranged in a rectangular array, each pixel capacitor C corresponding to each pixel on the display panel 400, and the corresponding pixel will light up after the pixel capacitor C is charged.

[0051] like Figure 2 As shown, the display driver chip 1000 may include a power conversion circuit 10, a reference voltage generation circuit 20, a timing control circuit 30, a gate driving circuit 40, and a source driving circuit 50. The input terminal of the power conversion circuit 10 can be connected to an external power supply 200, and the output terminal of the power conversion circuit 10 can be connected to the input terminal of the reference voltage generation circuit 20. The output terminal of the power conversion circuit 10 can also be connected to the power supply terminals of the gate driving circuit 40, the timing control circuit 30, and the source driving circuit 50, respectively. The external power supply 200 can provide a raw voltage to the power conversion circuit 10, which can convert the received raw voltage into voltages of different specifications and provide them to the reference voltage generation circuit 20, the timing control circuit 30, the gate driving circuit 40, and the source driving circuit 50, respectively.

[0052] like Figure 2 As shown, the output of the timing control circuit 30 is also connected to the input of the gate driving circuit 40. The timing control circuit 30 receives the display data signal, generates a first timing signal based on the display data signal, and sends the first timing signal to the gate driving circuit 40. After receiving the first timing signal, the gate driving circuit 40 generates a gate driving signal and sends the gate driving signal to the display panel 400, thereby selecting a certain pixel capacitor C from the multiple pixel capacitors C of the display panel 400 as the pixel capacitor C that needs to be charged.

[0053] like Figure 2 As shown, the output of the timing control circuit 30 is also connected to the input of the source drive circuit 50. The timing control circuit 30 receives the display data signal and generates a second timing signal based on the display data signal, then sends the second timing signal to the source drive circuit 50. The second timing signal can be a digital signal. After receiving the second timing signal, the source drive circuit 50 converts the second timing signal into a voltage signal and sends the voltage signal to the display panel 400. This voltage signal can charge the pixel capacitor C selected by the gate drive signal, thereby charging the pixel capacitor C and illuminating the pixel corresponding to the C pixel capacitor.

[0054] The larger the area of ​​the display panel 400, the longer the trace length of the source drive circuit 50, and the larger the parasitic capacitance generated. In high-resolution (more pixels) and high-refresh-rate (higher frequency of brightness switching for each pixel) applications, the charging time of the pixels is constantly compressed. In other words, the display driver chip 1000 is required to charge the pixel capacitor C in the display panel 400 faster.

[0055] against Figure 2The voltage of any pixel capacitor C shown determines the brightness of the corresponding pixel. To achieve more precise brightness control and a more detailed and accurate display, a wider range of voltage levels is required. Taking an 8-bit binary digital signal as an example, the voltage is divided into 256 levels. In the display driver chip 1000, directly implementing 8-bit digital-to-analog conversion would be difficult, require a large number of switches, and consume significant chip area. Therefore, interpolation techniques are commonly used in related technologies. For example, a 6-bit DAC first generates 64 non-interpolated voltage levels, and then a 2-bit interpolated DAC evenly inserts 3 interpolated voltage levels between adjacent non-interpolated voltage levels. Thus, the conversion of 8-bit data is achieved through the 6-bit and 2-bit DACs. Furthermore, the voltage levels have multiple levels, some of which are non-interpolated voltage levels and others are interpolated voltage levels, with multiple interpolated voltage levels evenly inserted between each pair of adjacent non-interpolated voltage levels. Both 6-bit and 2-bit DACs have relatively simple structures and require fewer components, thus saving chip area.

[0056] Taking pixel capacitor C with voltages of 127 and 126 as examples, the charging effect of pixel capacitor C is analyzed. Here, voltage 127 is the non-interpolation voltage, and voltage 126 is the interpolation voltage. Theoretically, voltage 127 should be higher than voltage 126. Figure 3 127 pairs of non-interpolation order voltages are shown. Figure 2 The voltage change curve (curve a) during the charging process of the pixel capacitor C is shown, along with the interpolation voltage pairs 126. Figure 2 The curve shown is the voltage change curve (curve b) during the charging process of the pixel capacitor C. From... Figure 3 As can be seen, charging begins on the rising edge, and the charging result is output shortly after the falling edge. Figure 2 As shown in the image, the pixel capacitor C corresponding to voltage 127 has not yet been fully charged, and the voltage is lower than 126. This will cause brightness reversal, and dark stripes will appear on the display panel 400.

[0057] Based on this, embodiments of this application provide a display driving circuit, which can be used for... Figure 2 The source drive circuit 50 is shown. (As shown in the image...) Figure 4 As shown, the display driving circuit may include a first DAC 51, a second DAC 52, a buffer 53, and a driving enhancement circuit 54. The output of the first DAC 51 is connected to the input of the second DAC 52, the output of the second DAC 52 is connected to the input of the buffer 53, and the output of the driving enhancement circuit 54 is also connected to the output of the second DAC 52.

[0058] In this embodiment, the first DAC51 can be connected with... Figure 2The timing control circuit 30 shown is connected to receive a first digital signal, which can be... Figure 2 The higher-order bits of the timing signal sent by the timing control circuit 30 shown are the number of bits in the first digital signal, which is less than the number of bits in the timing signal. For example, when the timing signal has 8 bits, the first digital signal can have 4, 5, 6, or 7 bits, etc. The following explanation uses a 6-bit first digital signal. Therefore, the first digital signal can be the higher 6 bits of the timing signal. For example, when the timing signal is 1111100 (corresponding to voltage 124), 1111101 (corresponding to voltage 125), 1111110 (corresponding to voltage 126), and 1111111 (corresponding to voltage 127), the first digital signal is always 111111.

[0059] The first DAC 51 performs digital-to-analog conversion on the first digital signal to obtain and output a first voltage signal. This first voltage signal may include two sub-voltage signals, which are named the first sub-voltage signal and the second sub-voltage signal for ease of description. The voltage of the first sub-voltage signal is obtained by subtracting 1 from the first digital signal and using this as the high 6 bits, then setting the low 2 bits to 11. The voltage of the second sub-voltage signal can also be obtained by using the first digital signal as the high 6 bits and setting the low 2 bits to 11. For example, when the voltages corresponding to the timing signals are 124, 125, 126, and 127, the voltage of the first sub-voltage signal output by the first DAC 51 is 123, and the voltage of the second sub-voltage signal is 127. The voltages of the first and second sub-voltage signals differ by 4.

[0060] In specific implementation, such as Figure 5 As shown, the first DAC51 may include multiple resistors R connected in series and a multiplexer Mux, wherein the first resistor R of the multiple resistors R can be connected to Figure 2 The power conversion circuit 10 shown has a last resistor R among multiple resistors that can be grounded. The multiplexer Mux has multiple inputs, each connected between every two resistors R. Multiplexers connected to different locations can receive different voltages. The multiplexer Mux can receive a first digital signal and select the corresponding first sub-voltage signal and second sub-voltage signal based on the first digital signal, outputting them from the multiplexer Mux's output terminal.

[0061] like Figure 5 As shown, the second DAC52 can be used to receive a second digital signal, which can be... Figure 2The timing signal sent by the timing control circuit 30 shown contains the lower digits, and the sum of the number of bits in the second digital signal and the first digital signal can be equal to the number of bits in the timing signal. For example, when the timing signal has 8 bits and the first digital signal has 5 bits, the second digital signal can have 3 bits; when the first digital signal has 6 bits, the second digital signal can have 2 bits; and when the first digital signal has 7 bits, the second digital signal can have 1 bit. The following explanation uses a second digital signal with 2 bits as an example. Therefore, the second digital signal is the lower 2 bits of the timing signal output by the timing control circuit 30. For example, when the timing signal is 1111100, the second digital signal is 00.

[0062] When the timing signal is 1111100 (corresponding to a voltage of 124), the voltage 124 can be calculated from 0.75×123+0.25×127, where 0.75 and 0.25 are weighting coefficients. When the timing signal is 1111101 (corresponding to a voltage of 125), the voltage 125 can be calculated from 0.5×123+0.5×127, where 0.5 and 0.5 are weighting coefficients. When the timing signal is 1111110 (corresponding to a voltage of 126), it can be calculated from 0.75×123+0.25×127, where 0.75 and 0.25 are weighting coefficients. When the timing signal is 1111111 (corresponding to a voltage of 127), it can be calculated from 0×123+1×127, where 0 and 1 are weighting coefficients. It can be seen that the weighting coefficients differ depending on the lower two bits of the timing signal, i.e., the second digit. Therefore, a correspondence between the second digital signal and the weighting coefficients can be pre-established. After receiving the second digital signal, the second DAC52 can determine the weighting coefficients based on the second digital signal. When the second digital signal is 00, the weighting coefficients are determined to be 0.75 and 0.25. When the second digital signal is 01, the weighting coefficients are determined to be 0.5 and 0.5. When the second digital signal is 10, the weighting coefficients are determined to be 0.25 and 0.75. When the second digital signal is 11, the weighting coefficients are determined to be 0 and 1.

[0063] The second DAC52 can also receive two first voltage signals sent by the first DAC51, and divide the two first voltage signals into four second voltage signals according to a weighting coefficient. For example, when... Figure 1When the timing signal output by the timing control circuit 30 is 1111100 (corresponding to a voltage of 124), and the weighting coefficients are 0.75 and 0.25, then of the four output second voltage signals, three of the second voltage signals are the first sub-voltages, and the other second voltage signal is the second sub-voltage. When the weighting coefficients are 0.5 and 0.5, then of the four output second voltage signals, two of the second voltage signals are the first sub-voltages, and the other two are the second sub-voltages. When the weighting coefficients are 0.25 and 0.75, then of the four output second voltage signals, one of the second voltage signals is the first sub-voltage, and the other three are the second sub-voltages. When the weighting coefficients are 0 and 1, then all four output second voltage signals are the first sub-voltages.

[0064] like Figure 4 As shown, the output terminal of the drive enhancement circuit 54 is connected to the output terminal of the second DAC 52, and the drive enhancement circuit 54 can be used to charge the output terminal of the second DAC 52. Since the output terminal of the second DAC 52 outputs multiple second voltage signals, the drive enhancement circuit 54 can enhance the voltage of each second voltage signal.

[0065] like Figure 5 As shown, the buffer 53 may include a differential circuit 531 and a power amplifier 532. The differential circuit 531 may include multiple differential pairs 5311, the number of which is the same as the number of second voltage signals output by the second DAC 52. Therefore, in this embodiment, as... Figure 4 As shown, buffer 53 may include four differential pairs 5311. Each differential pair 5311 corresponds to one second voltage signal. When the voltage corresponding to the timing signal is 124, and the weighting coefficients are 0.75 and 0.25, among the four second voltage signals, three of the second voltage signals correspond to the first sub-voltage, and the other second voltage signal corresponds to the second sub-voltage. Therefore, the first sub-voltage drives three differential pairs 5311, and the second sub-voltage drives one differential pair 5311. That is, all four differential pairs 5311 are driven by both the first and second sub-voltages. Similarly, when the voltage corresponding to the timing signal is 125, and the weighting coefficients are 0.5 and 0.5, and when the voltage corresponding to the timing signal is 126, and the weighting coefficients are 0.75 and 0.25, all four differential pairs 5311 are driven by both the first and second sub-voltages. When the voltage corresponding to the timing signal is 127 and the weighting coefficients are 1 and 0, the voltages corresponding to the four output second voltage signals are all the first sub-voltages. Therefore, the four differential pairs 5311 are driven by the first sub-voltage. The four differential pairs 5311 can output one voltage signal to the power amplifier 532 for amplification and output a third voltage signal to... Figure 1 The display panel 400 shown is shown.

[0066] The voltage of the third voltage signal corresponds to the timing signal. It can be the same as the second sub-voltage output by the first DAC51, or it can be obtained using the first and second sub-voltages and their respective weighting coefficients. Since the voltage corresponding to the timing signal is divided into 256 levels, the voltages of 64 levels are the same as the first or second sub-voltage output by the first DAC51 and are not obtained through interpolation. These voltages can be called non-interpolated voltages. The remaining voltages are obtained through interpolation and can therefore be called interpolated voltages. For example, among the four voltages 124, 125, 126, and 127 mentioned above, 124, 125, and 126 are interpolated voltages, and 127 is a non-interpolated voltage.

[0067] For non-interpolation voltages, four differential pairs of the 5311 need to be driven simultaneously. For interpolation voltages, they can be driven by two voltages simultaneously, thus the charging speed of interpolation voltages is faster than that of non-interpolation voltages. For example, for... Figure 3 The charging process diagram shown indicates that voltage 126 charges faster than voltage 127, thus voltage 126 is actually higher than voltage 127, resulting in... Figure 2 The pixel capacitor C shown exhibits brightness reversal. Based on this, in this embodiment, the drive enhancement circuit 54 can charge the output of the second DAC 52 when the voltage corresponding to the timing signal is a non-interpolation voltage. This improves the charging speed of the non-interpolation voltage, thereby reducing the occurrence of pixel capacitor brightness reversal and thus reducing... Figure 2 The dark stripes appear on the display panel 400 shown, thus achieving accurate display of the image.

[0068] In this embodiment, as Figure 6a As shown, the drive enhancement circuit 54 includes a first capacitor C1. A first terminal of the first capacitor C1 is connected to a first power supply 11, and a second terminal of the first capacitor C1 is connected to the output terminal of the second DAC 52. The first power supply 11 can... Figure 1 Under the control of the display module 1000, the first capacitor C1 is charged, meaning the potential of the first terminal of the first capacitor C1 is the same as the potential of the output terminal of the first power supply 11. Furthermore, after the first power supply 11 charges the first capacitor C1 for a period of time, the potential of the second terminal of the first capacitor C1 becomes the same as the potential of the first terminal. Since the second terminal of the first capacitor C1 is connected to the output terminal of the second DAC 52, the potential of the output terminal of the second DAC 52 is the same as the potential of the second terminal of the first capacitor C1, thus enabling the first capacitor C1 to charge the output terminal of the second DAC 52. The drive enhancement circuit 54 is implemented through the first capacitor C1, making the structure of this scheme relatively simple and easy to implement.

[0069] Furthermore, in this embodiment, the first capacitor C1 can be a general-purpose capacitor or a metal-oxide-semiconductor field-effect transistor (MOS) capacitor. When the first capacitor C1 is a MOS capacitor, it can save... Figure 1 The area of ​​the display driver chip 1000 is shown.

[0070] Furthermore, when the potential at the output terminal of the second DAC52 is the same as the potential at the second terminal of the first capacitor C1, and after the first power supply 11 stops charging the first capacitor C1, the potential at the output terminal of the second DAC52 slowly decreases under the action of the first capacitor C1, and the voltage of the pixel capacitor C also slowly decreases. The specific change process is as follows... Figure 7 As shown. Figure 7 Curve a1 represents the voltage change curve during the charging of pixel capacitor C by non-interpolation voltage 127 in this embodiment; curve a2 represents the voltage change curve during the charging of pixel capacitor C by non-interpolation voltage 127 when the display driving circuit 50 does not include the driving enhancement circuit 54; and curve b represents the voltage change curve during the charging of pixel capacitor C by interpolation voltage 126 in this embodiment. Figure 7 As can be seen, the voltage of pixel capacitor C also decreases slowly. Furthermore, in this embodiment, the voltage of the pixel capacitor corresponding to the non-interpolation voltage 127 is always higher than the voltage of the pixel capacitor corresponding to the interpolation voltage 126. That is, during the charging process of the pixel capacitor, the current non-interpolation voltage is always higher than the previous interpolation voltage, thus better avoiding… Figure 2 The brightness of the pixels on the display panel 400 shown is reversed.

[0071] In other embodiments of this application, such as Figure 6b As shown, with Figure 6a The difference between the illustrated embodiments lies in the number of capacitors. Specifically, the drive enhancement circuit 54 also includes a second capacitor C2 and a third capacitor C3. The first terminal of the second capacitor C2 is connected to the second power supply 12, and the second terminal of the second capacitor C2 is connected to the output terminal of the second DAC 52. The first terminal of the third capacitor C3 is connected to the third power supply 13, and the second terminal of the third capacitor C3 is connected to the output terminal of the second DAC 52. Because... Figure 4The voltage of the third voltage signal output by the buffer 53 shown may be one of several non-interpolation voltages, and the magnitudes of the different non-interpolation voltages are different. In this embodiment, the drive enhancement circuit 54 also includes a second capacitor C2 and a third capacitor C3, and the first terminal of the first capacitor C1 is connected to the first power supply 11, the first terminal of the second capacitor C2 is connected to the second power supply 12, and the first terminal of the third capacitor C3 is connected to the third power supply 13. That is, the first terminals of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are respectively connected to different power supplies. Thus, the number of capacitors charging the output terminal of the second DAC 52 can be controlled by each power supply, thereby controlling the degree of charging of the output terminal of the second DAC 52, and thus achieving different degrees of charging for different non-interpolation voltages, so that the voltage of the third voltage signal output from the buffer 53 after charging is closer to the corresponding non-interpolation voltage, thereby improving the performance of the second DAC 52. Figure 2 The precision of brightness control of the pixels in the display panel 400 shown.

[0072] In specific implementation, it can be done through Figure 1 The controller in the display module 1000, as illustrated, exemplifies how, when one or more capacitors need to charge the output of the second DAC 52, the controller controls one or more corresponding power supplies to begin supplying voltage to the corresponding capacitors. For instance, when two capacitors need to charge the output of the second DAC 52, the controller can send control signals to the first power supply 11 and the second power supply 12. The first power supply 11 can receive the control signal and begin supplying voltage to the first capacitor C1, thus charging the output of the second DAC 52. Similarly, the second power supply 12 can also receive the control signal and begin supplying voltage to the second capacitor C2, thus charging the output of the second DAC 52.

[0073] In other embodiments of this application, such as Figure 8a As shown, with Figure 6a The difference shown is that, in Figure 6a The illustrated embodiment includes an additional first capacitor state control circuit 541. Specifically, the drive enhancement circuit 54 further includes the first capacitor state control circuit 541, the input terminal of which is connected to the second terminal of the first capacitor C1, and the output terminal of which is connected to the output terminal of the second DAC 52. The first capacitor state control circuit 541 can be used to control whether the first capacitor C1 charges the output terminal of the second DAC 52.

[0074] In practical implementation, when the voltage corresponding to the timing signal is a non-interpolation voltage, the first capacitor state control circuit 541 controls the first capacitor C1 to charge the output terminal of the second DAC 52; when the voltage corresponding to the timing signal is an interpolation voltage, the first capacitor state control circuit 541 controls the first capacitor C1 not to charge the output terminal of the second DAC 52, thereby making the charging of the output terminal of the second DAC 52 more accurate. Furthermore, when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply 11 can charge the first capacitor C1, and the first capacitor C1 does not need to charge the output terminal of the second DAC 52; when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply 11 has completed charging the first capacitor C1, and the first capacitor C1 can charge the output terminal of the second DAC 52. This also avoids additional clock cycles, thereby improving the accuracy of the charging process. Figure 2 The charging speed of the pixel capacitor C shown.

[0075] Furthermore, the first capacitor state control circuit 541 can receive the lower bits of the timing signal and determine whether the corresponding voltage is an interpolation voltage or a non-interpolation voltage based on the lower bits of the timing signal. Therefore, when the voltage corresponding to the timing signal is a non-interpolation voltage, it controls the first capacitor C1 to charge the output terminal of the second DAC 52. When the voltage corresponding to the timing signal is an interpolation voltage, it controls the first capacitor C1 not to charge the output terminal of the second DAC 52, at which time the first power supply 11 can charge the first capacitor C1.

[0076] In other embodiments of this application, such as Figure 8b As shown, with Figure 8a The difference between the embodiments shown is that the drive enhancement circuit 54 in Figure 8a Based on the embodiment shown, a second capacitor C2, a third capacitor C3, a second capacitor state control circuit 542, and a third capacitor state control circuit 543 are added.

[0077] Specifically, such as Figure 8b As shown, the first terminal of the second capacitor C2 is connected to the first power supply 11, the second terminal of the second capacitor C2 is connected to the input terminal of the second capacitor state control circuit 542, and the output terminal of the second capacitor state control circuit 542 is connected to the output terminal of the second DAC 52. Thus, the second capacitor state control circuit 542 can control whether the second capacitor C2 charges the output terminal of the second DAC 52.

[0078] like Figure 8bAs shown, the first terminal of the third capacitor C3 is connected to the first power supply 11, the second terminal of the third capacitor C3 is connected to the input terminal of the third capacitor state control circuit 543, and the output terminal of the third capacitor state control circuit 543 is connected to the output terminal of the second DAC 52. Thus, the third capacitor state control circuit 543 can control whether the third capacitor C3 charges the output terminal of the second DAC 52. Therefore, in this embodiment, when the drive enhancement circuit 54 includes multiple capacitors, each capacitor state control circuit can control whether the corresponding capacitor charges the output terminal of the second DAC 52.

[0079] Based on this, such as Figure 9 As shown, the first capacitor state control circuit 541 includes a first switching transistor M1. The first terminal S1 of the first switching transistor M1 is connected to the second terminal of the first capacitor C1, and the second terminal D1 of the first switching transistor M1 is connected to the output terminal of the second DAC 52. The control terminal G1 of the first switching transistor M1 can be used to receive the low-order digital signal in the timing signal. In one example, when the low-order digital signal is 0, the first switching transistor M1 is open; when the low-order digital signal is 1, the first switching transistor M1 is closed. In another example, when the low-order digital signal is 1, the first switching transistor M1 is open; when the low-order digital signal is 0, the first switching transistor M1 is closed. When the first switching transistor M1 is closed, it can connect the second terminal of the first capacitor C1 to the output terminal of the second DAC 52 and charge the output terminal of the second DAC 52. This scheme is simple in structure, easy to implement, and relatively reliable.

[0080] In some cases, the second DAC52 can receive multiple bits of digital signal in the timing signal, with each switch receiving one bit of digital signal. Therefore, in order to achieve the ability to receive every bit of digital signal in a multi-bit digital signal, in one embodiment, such as Figure 9 As shown, the first capacitor state control circuit 541 may further include a second switch M2 and a third switch M3. The first terminal S2 of the second switch M2 is connected to the second terminal D1 of the first switch M1, the first terminal S3 of the third switch M3 is connected to the second terminal D2 of the second switch M2, and the second terminal D3 of the third switch M3 is connected to the output terminal of the second DAC 52. That is, the first switch M1, the second switch M2, and the third switch M3 are connected in series. The control terminal G1 of the first switch M1, the control terminal G2 of the second switch M2, and the control terminal G3 of the third switch M3 can each receive one bit of a multi-bit digital signal. When each bit of the digital signal is 1, the first switch M1, the second switch M2, and the third switch M3 are all closed, thereby charging the first capacitor C1 to the output terminal of the second DAC 52.

[0081] In another embodiment, the second DAC 52 can receive two digital signals from the timing signal. The first capacitor state control circuit 541 can then include two switching transistors, namely a first switching transistor M1 and a second switching transistor M2. The first terminal S2 of the second switching transistor M2 is connected to the second terminal D1 of the first switching transistor M1, and the second terminal D2 of the second switching transistor M2 is connected to the output terminal of the second DAC 52. Therefore, when the digital signals received by the control terminals G1 of the first switching transistor M1 and G2 of the second switching transistor M2 are both 1, the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 are all closed, thereby allowing the first capacitor C1 to charge the output terminal of the second DAC 52.

[0082] It is understood that in other embodiments, if the second DAC52 can receive four digital signals in the timing signal, then the first capacitor state control circuit 541 may include four switching transistors; if the second DAC52 can receive five digital signals in the timing signal, then the first capacitor state control circuit 541 may include five switching transistors; and so on.

[0083] In other embodiments of this application, such as Figure 10 As shown, with Figure 6b The difference between the illustrated embodiments is that the drive enhancement circuit 54 in Figure 6b The illustrated embodiment includes an additional charging level control circuit 544. The second terminals of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are all connected to the input terminal of the charging level control circuit 544. The output terminal of the charging level control circuit 544 is connected to the output terminal of the second DAC 52. The charging level control circuit 544 controls the number of capacitors charging the output terminal of the second DAC 52. In other words, the charging level control circuit 544 can control whether the first capacitor C1, the second capacitor C2, and the third capacitor C3 charge the output terminal of the second DAC 52. The first capacitor C1, the second capacitor C2, and the third capacitor C3 can form a capacitor array. The more capacitors charging the output terminal of the second DAC 52, the larger the capacitance value of the capacitor array, resulting in a faster voltage build-up speed and a higher voltage at the output terminal of the second DAC 52. This allows for the selection of different numbers of capacitors to charge the output of the second DAC52 based on the magnitude of the voltage corresponding to the timing signal, thereby controlling the degree of charging of the output of the second DAC52. This enables different degrees of charging for different non-interpolation voltages, making the voltage of the third voltage signal output from the buffer 53 after charging closer to the theoretical value of the corresponding non-interpolation voltage. This improves the accuracy of brightness control of the pixels of the display panel 400.

[0084] In a specific implementation, the received signal of the drive enhancement circuit 54 can be the same as the received signal of the first DAC 51. For example, both are the higher bits of the timing signal. The drive enhancement circuit 54 can determine the number of capacitors to charge the output terminal of the second DAC 52 based on the magnitude relationship between the higher bits of the digital signal.

[0085] like Figure 11 As shown, the charging level control circuit 544 includes a fourth switch M4, a fifth switch M5, and a sixth switch M6. The first terminal S4 of the fourth switch M4 is connected to the second terminal of the first capacitor C1, and the second terminal D4 of the fourth switch M4 is connected to the output terminal of the second DAC 52. The first terminal S5 of the fifth switch M5 is connected to the second terminal of the second capacitor C2, and the second terminal D5 of the fifth switch M5 is connected to the output terminal of the second DAC 52. The first terminal S6 of the sixth switch M6 is connected to the second terminal of the third capacitor C3, and the second terminal D6 of the sixth switch M6 is connected to the output terminal of the second DAC 52. In other words, the fourth switch M4 controls whether the first capacitor C1 charges the output terminal of the second DAC 52, the fifth switch M5 controls whether the second capacitor C2 charges the output terminal of the second DAC 52, and the sixth switch M6 controls whether the third capacitor C3 charges the output terminal of the second DAC 52. For example, when the fourth switch M4, the fifth switch M5, and the sixth switch M6 are all closed, the first capacitor C1, the second capacitor C2, and the third capacitor C3 can all charge the output of the second DAC52. That is, the number of capacitors charging the output of the second DAC52 is three. When two of the fourth switch M4, the fifth switch M5, and the sixth switch M6 are closed, the number of capacitors charging the output of the second DAC52 is two. When one of the fourth switch M4, the fifth switch M5, and the sixth switch M6 is closed, the number of capacitors charging the output of the second DAC52 is one.

[0086] In practice, the control electrodes of the fourth switch M4, the fifth switch M5, and the sixth switch M6 can each receive three bits from the higher-order digital signals. When the digital signal received by the fourth switch M4 is 1, it closes; when the received digital signal is 0, it opens, allowing the first capacitor C1 to charge the output of the second DAC52. Similarly, when the fifth switch M5 is closed, the second capacitor C2 charges the output of the second DAC52. When the sixth switch M6 is closed, the third capacitor C3 charges the output of the second DAC52.

[0087] It is understood that the number of capacitors in the drive enhancement circuit 54 can be the same as the number of bits of the higher-order digital signals in the timing signal received by the first DAC 51. For example, when the first DAC 51 receives the higher 6 bits of digital signals, the drive enhancement circuit 54 can include 6 capacitors. Correspondingly, the number of switching transistors in the charging level control circuit 544 can also be the same as the number of bits of the higher-order digital signals in the timing signal received by the first DAC 51, that is, also 6. This allows for more precise control of the charging level of the drive enhancement circuit 54 to the output of the second DAC 52.

[0088] It is understood that in the embodiments of this application, the first terminal of each switch can be the source, and the second terminal of each switch can be the drain. In other embodiments, the first terminal of each switch can be the drain, and the second terminal of each switch can be the source.

[0089] exist Figure 8b and Figure 9 In the illustrated embodiment, the drive enhancement circuit 54 includes a first capacitor state control circuit 541, a second capacitor state control circuit 542, and a third capacitor state control circuit 543, but does not include a charging level control circuit 544; Figure 10 and Figure 11 In the illustrated embodiment, the drive enhancement circuit 54 includes a charging level control circuit 544, but excludes the first capacitor state control circuit 541, the second capacitor state control circuit 542, and the third capacitor state control circuit 543. In other embodiments of this application, such as... Figure 12 As shown, the drive enhancement circuit 54 may include a first capacitor state control circuit 541, a second capacitor state control circuit 542, a third capacitor state control circuit 543, and a charging level control circuit 544. Specifically, in the charging level control circuit 544, the first terminal S4 of the fourth switch M4 is connected to the second terminal of the first capacitor C1; the second terminal D4 of the fourth switch M4 is connected to the first terminal S1 of the first switch M1 in the first capacitor state control circuit 541; and the second terminal D3 of the switch M3 is connected to the output terminal of the second DAC 52. In the charging level control circuit 544, the first terminal S5 of the fifth switch M5 is connected to the second terminal of the second capacitor C2; the second terminal D5 of the fifth switch M5 is connected to the first terminal S1 of the first switch M1 in the second capacitor state control circuit 542; and the second terminal D3 of the switch M3 in the second capacitor state control circuit 542 is connected to the output terminal of the second DAC 52. In the charging level control circuit 544, the first terminal S6 of the sixth switch M6 is connected to the second terminal of the first capacitor C1, the second terminal D6 of the sixth switch M6 is connected to the first terminal S1 of the first switch M1 in the third capacitor state control circuit 543, and the second terminal D3 of the switch M3 in the third capacitor state control circuit 543 is connected to the output terminal of the second DAC 52.

[0090] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A display driving circuit, characterized in that, include: First digital-to-analog converter (DAC), second DAC, drive enhancement circuitry, and buffer; The first DAC is used to receive the first digital signal and perform digital-to-analog conversion on the first digital signal; The second DAC has its input terminal connected to the output terminal of the first DAC, and is used to receive the second digital signal and perform digital-to-analog conversion on the second digital signal; The buffer is used to output a voltage signal, and the input terminal of the buffer is connected to the output terminal of the second DAC. The drive enhancement circuit has its output terminal connected to the output terminal of the second DAC, and is used to charge the output terminal of the second DAC when the voltage signal output by the buffer is a non-interpolation voltage.

2. The display driving circuit according to claim 1, characterized in that, The drive enhancement circuit includes a first capacitor, a first end of which is connected to a first power supply, and a second end of which is connected to the output of the second DAC.

3. The display driving circuit according to claim 2, characterized in that, The drive enhancement circuit further includes a second capacitor and a third capacitor. The first end of the second capacitor is used to connect to the second power supply, and the second end of the second capacitor is connected to the output terminal of the second DAC. The first end of the third capacitor is used to connect to the third power supply, and the second end of the third capacitor is connected to the output of the second DAC.

4. The display driving circuit according to claim 2, characterized in that, The drive enhancement circuit further includes a first capacitor state control circuit. The input terminal of the first capacitor state control circuit is connected to the second terminal of the first capacitor, and the output terminal of the first capacitor state control circuit is connected to the output terminal of the second DAC. The first capacitor state control circuit is used to control whether the first capacitor charges the output terminal of the second DAC.

5. The display driving circuit according to claim 4, characterized in that, The drive enhancement circuit further includes a second capacitor and a third capacitor, wherein a first terminal of the second capacitor is used to connect to a first power supply, and a first terminal of the third capacitor is used to connect to the first power supply. The drive enhancement circuit further includes a second capacitor state control circuit and a third capacitor state control circuit. The input terminal of the second capacitor state control circuit is connected to the second terminal of the second capacitor, and the output terminal of the second capacitor state control circuit is connected to the output terminal of the second DAC. The input terminal of the third capacitor state control circuit is connected to the second terminal of the third capacitor, and the output terminal of the third capacitor state control circuit is connected to the output terminal of the second DAC.

6. The display driving circuit according to claim 4 or 5, characterized in that, The capacitor state control circuit includes a first switching transistor, the first terminal of which is connected to the second terminal of the capacitor, and the second terminal of which is connected to the output terminal of the second DAC.

7. The display driving circuit according to claim 6, characterized in that, The capacitor state control circuit includes a second switch and a third switch. The first terminal of the second switch is connected to the second terminal of the first switch, the first terminal of the third switch is connected to the second terminal of the second switch, and the second terminal of the third switch is connected to the output terminal of the second DAC.

8. The display driving circuit according to any one of claims 2, 4, 5, and 7, characterized in that, The drive enhancement circuit further includes a second capacitor and a third capacitor, wherein a first terminal of the second capacitor is used to connect to a first power supply, and a first terminal of the third capacitor is used to connect to the first power supply. The drive enhancement circuit further includes a charging level control circuit. The second terminals of the first capacitor, the second capacitor, and the third capacitor are all connected to the input terminal of the charging level control circuit. The output terminal of the charging level control circuit is connected to the output terminal of the second DAC. The charging level control circuit is used to control the number of capacitors charging the output terminal of the second DAC.

9. The display driving circuit according to claim 8, characterized in that, The charging level control circuit includes a fourth switch, a fifth switch, and a sixth switch. The first terminal of the fourth switch is connected to the second terminal of the first capacitor, and the second terminal of the fourth switch is connected to the output terminal of the second DAC. The first terminal of the fifth switch is connected to the second terminal of the second capacitor, and the second terminal of the fifth switch is connected to the output terminal of the second DAC. The first terminal of the sixth switch is connected to the second terminal of the third capacitor, and the second terminal of the sixth switch is connected to the output terminal of the second DAC.

10. A display driver chip, characterized in that, It includes a timing control circuit and a display driving circuit as described in any one of claims 1-9, wherein the timing control circuit is electrically connected to the display driving circuit.

11. A display module, characterized in that, It includes a display panel and the display driver chip as described in claim 10, wherein the display panel is electrically connected to the display driver chip.

12. An electronic device, characterized in that, It includes a controller and the display module as described in claim 11, wherein the controller is electrically connected to the display module.

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