Ion implantation layer correction method, device and semiconductor device

Abstract

The present application relates to the field of semiconductor technology, and discloses a correction method, device and semiconductor device for an ion implantation layer, wherein the method comprises: obtaining structural information associated with the ion implantation layer in a semiconductor material, wherein the structural information is used to characterize the distribution relationship between the ion implantation layer and other structural layers; dividing the ion implantation layer into a plurality of areas to be corrected according to the distribution relationship characterized by the structural information, wherein different areas to be corrected have different thicknesses of photoresist corresponding to them; establishing a special correction model for any area to be corrected, and correcting the area to be corrected based on the special correction model to generate a correction result for the area to be corrected; and splicing the correction results of each area to be corrected to obtain an overall correction result for the ion implantation layer, thereby solving the technical problem of inaccurate OPC correction of the ion implantation layer in the related art, and achieving the technical effect of further reducing the edge placement error.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method and device for correcting an ion implantation layer and a semiconductor device. Background Art

[0002] Ion implantation refers to the use of an ion implanter to implant ions into the exposed silicon wafer area at a predetermined dose and energy under the protection of a photoresist to form an ion implantation layer with the required doping concentration and depth. Under the influence of the optical proximity effect, the ion implantation layer is deformed and deviates from the designed pattern, which in turn leads to quality problems such as reduced product yield or device leakage. The OPC (optical proximity correction) model is generally used to correct the ion implantation layer. The OPC correction method involved in the related art generally uses a single correction model, which cannot match the actual structure of the semiconductor material, resulting in low correction accuracy. Summary of the invention

[0003] The present application provides a correction method for an ion implantation layer, which solves the technical problem that the OPC correction process of the ion implantation layer in the related art is not accurate enough, and achieves the technical effect of further reducing the edge placement error.

[0004] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0005] In a first aspect, an embodiment of the present application provides a method for correcting an ion implantation layer, the method comprising: obtaining structural information associated with the ion implantation layer in a semiconductor material, the structural information being used to characterize a distribution relationship between the ion implantation layer and other structural layers; dividing the ion implantation layer into a plurality of regions to be corrected according to the distribution relationship characterized by the structural information, wherein different regions to be corrected have different thicknesses of photoresist corresponding to them; for any region to be corrected, establishing a dedicated correction model for the region to be corrected, and correcting the region to be corrected based on the dedicated correction model to generate a correction result for the region to be corrected; and splicing the correction results of each region to be corrected to obtain an overall correction result for the ion implantation layer.

[0006] An embodiment of the present application provides a correction method for an ion implantation layer, comprising obtaining structural information associated with the ion implantation layer in a semiconductor material, wherein the structural information is used to characterize the distribution relationship between the ion implantation layer and other structural layers; dividing the ion implantation layer into a plurality of areas to be corrected according to the distribution relationship characterized by the structural information, wherein different areas to be corrected have different thicknesses of photoresist corresponding to them; for any area to be corrected, establishing a special correction model for the area to be corrected, and correcting the area to be corrected based on the special correction model to generate a correction result for the area to be corrected; and splicing the correction results of each area to be corrected to obtain an overall correction result for the ion implantation layer, thereby solving the technical problem of inaccurate OPC correction of the ion implantation layer in the related art, providing an OPC correction method that is more compatible with the semiconductor material structure, and achieving the technical effect of further reducing edge placement errors.

[0007] Among them, the edge placement error is used to characterize the difference between the actual manufacturing pattern of the ion implantation layer and the original design pattern.

[0008] Optionally, according to the distribution relationship characterized by the structural information, the ion implantation layer is split into multiple areas to be corrected, including: in the direction of ion implantation, identifying the first type of area where the ion implantation layer and other structural layers exist at the same time, and identifying the second type of area where only the ion implantation layer exists; for any local area in the first type of area, determining the thickness of the photoresist between the upper surface of the ion implantation layer and the upper surface of the other structural layers in the local area; dividing the first type of area into one or more first sub-areas according to the determined thickness of the photoresist, wherein different first sub-areas have corresponding photoresist thicknesses; and treating each of the first sub-areas and the second type of area as multiple areas to be corrected obtained by splitting.

[0009] Optionally, establishing a dedicated correction model for the area to be corrected includes: acquiring photolithography data of the area to be corrected, the photolithography data at least including photoresist parameters and exposure conditions, wherein the photoresist parameters are used to characterize at least one of the number of photoresist layers, the thickness of each photoresist layer, and the transmittance of each photoresist layer, and the exposure conditions are used to characterize at least one of exposure energy, exposure focal length, and exposure light source; according to the exposure conditions, establishing an optical model for simulating light source information, and according to the photoresist parameters, establishing a photoresist model for simulating chemical reactions occurring in the photoresist; and determining the optical model and the photoresist model as the established dedicated correction model.

[0010] Optionally, adjacent areas between the first area to be corrected and the second area to be corrected are determined on the surface of the semiconductor material; the edge contour of the ion implantation layer in the adjacent area is identified, and a standard smoothing coefficient of the edge contour is calculated; in the process of correcting the first area to be corrected based on the first special correction model and correcting the second area to be corrected based on the second special correction model, after the correction of the current correction round is completed, the correction results of the current correction round are simulated and spliced, and the edge smoothing coefficient in the adjacent area after the simulated splicing is calculated; the error between the edge smoothing coefficient and the standard smoothing coefficient is determined, and the error is transferred to the next correction round, so as to correct the correction process in the next correction round through the error.

[0011] Optionally, calculating the standard smoothing coefficient of the edge profile includes: determining an original design profile of the ion implantation layer, and determining a reference line matching the edge profile in the original design profile; calculating a distance mean and a distance variance between the edge profile and the reference line, and using the distance mean and the distance variance as the standard smoothing coefficient of the edge profile.

[0012] Optionally, calculating the edge smoothing coefficient in the adjacent area after simulated stitching includes: identifying a simulated edge contour after simulated stitching in the adjacent area, calculating a distance mean and a distance variance between the simulated edge contour and the reference line, and using the distance mean and distance variance corresponding to the simulated edge contour as the edge smoothing coefficient.

[0013] Optionally, correcting the correction process in the next correction round through the error includes: taking the error as a joint correction coefficient, inputting it into the first special correction model and the second special correction model respectively, so that the first special correction model and the second special correction model can identify the correction direction represented by the error when generating their respective correction results, and adjust the initially generated correction results along the correction direction.

[0014] Optionally, when the ion implantation layer is split into a plurality of areas to be corrected, each of the areas to be corrected obtained by the splitting is assigned a respective splitting identifier, and a merge baseline of each area to be corrected is determined, and the merge baseline is inherited into the correction result of the area to be corrected; splicing the correction results of each of the areas to be corrected includes: according to the splitting identifiers of each area to be corrected, determining the splicing order of each correction result, and during the splicing process, aligning the merge baselines in each correction result.

[0015] In a second aspect, an embodiment of the present application provides a correction device for an ion implantation layer, the device comprising: a structural information acquisition unit, used to acquire structural information associated with the ion implantation layer in a semiconductor material, the structural information being used to characterize the distribution relationship between the ion implantation layer and other structural layers; a region splitting unit, used to split the ion implantation layer into a plurality of regions to be corrected according to the distribution relationship characterized by the structural information, wherein different regions to be corrected have different thicknesses of photoresist corresponding to them; a correction unit, used to establish a special correction model for any region to be corrected, and correct the region to be corrected based on the special correction model to generate a correction result for the region to be corrected; and a splicing unit, used to splice the correction results of each of the regions to be corrected to obtain an overall correction result for the ion implantation layer.

[0016] In a third aspect, an embodiment of the present application provides a semiconductor device, wherein an ion implantation layer in the semiconductor device is corrected according to the above-mentioned method for correcting an ion implantation layer.

[0017] In a fourth aspect, an embodiment of the present application provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the above-mentioned method for correcting the ion implantation layer by executing the computer instructions.

[0018] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the above-mentioned method for correcting the ion implantation layer.

[0019] In a sixth aspect, an embodiment of the present application provides a computer program product, including computer instructions, wherein the computer instructions are used to enable a computer to execute the above-mentioned method for correcting the ion implantation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a schematic cross-sectional view of a structure associated with an ion implantation layer in one scenario;

[0022] Figure 2 is a schematic top view of a structure associated with an ion implantation layer in one scenario;

[0023] Figure 3 A flow chart of a method for correcting an ion implantation layer provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of the splicing result of the current sequence provided in the embodiment of the present application;

[0025] Figure 5 A schematic diagram of the original design outline provided for the embodiment of the present application;

[0026] Figure 6 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0028] Ion implantation refers to the use of an ion implanter to implant ions into the exposed silicon wafer area at a predetermined dose and energy under the protection of photoresist to form an ion implantation layer with the required doping concentration and depth. Under the influence of the optical proximity effect, the ion implantation layer is deformed and deviates from the designed pattern, which leads to quality problems such as reduced product yield or device leakage. Related technologies generally use a single OPC (optical proximity correction) model to correct the ion implantation layer. Since the thickness of the photoresist in different areas of the ion implantation layer is different during photolithography exposure, only a single correction model is used for OPC correction, which cannot match the actual structure of the semiconductor material, resulting in low correction accuracy.

[0029] Specifically, Figure 1 is a schematic cross-sectional view of a structure associated with an ion implantation layer in one scenario, Figure 2 FIG. 1 is a top view schematic diagram of a structure associated with an ion implantation layer in a scenario. Figure 1 As shown in the figure, the first type of area contains the ion implantation layer and other structural layers, and the thickness of the photoresist is a. The second type of area only contains the ion implantation layer, and the thickness of the photoresist is b. The single OPC correction model only considers the condition that the thickness of the photoresist is a (or the thickness of the photoresist is b). Therefore, when using the single OPC correction model for correction, Figure 2 As shown, the correction result of the width c of the first type of area is accurate, but the correction result of the width d of the second type of area is inaccurate.

[0030] An embodiment of the present application provides a method for correcting an ion implantation layer. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0031] Please refer to Figure 3 , Figure 3 is a flow chart of a method for correcting an ion implantation layer provided in an embodiment of the present application, such as Figure 3 As shown, the process includes the following steps:

[0032] Step S1, obtaining structural information associated with an ion implantation layer in a semiconductor material, wherein the structural information is used to characterize a distribution relationship between the ion implantation layer and other structural layers.

[0033] The structural information includes the layout, shape, size and spatial position relationship between the ion implantation layer and other structural layers. Other structural layers can be structures such as polysilicon layers. The structural information can be stored in the GDS file. There may be different structural layers such as ion implantation layers and polysilicon layers in the silicon wafer at the same time.

[0034] Step S3, dividing the ion implantation layer into a plurality of regions to be corrected according to the distribution relationship represented by the structural information, wherein different regions to be corrected have different corresponding photoresist thicknesses.

[0035] Among them, Figure 1 As shown in FIG. 1 , the thickness of the photoresist can be represented by the distance between the upper surface of the ion implantation layer and the upper surface of other structural layers. The ion implantation layer can be divided into multiple regions to be corrected. Regions with the same photoresist thickness can be divided into the same region to be corrected. Different regions to be corrected have different corresponding photoresist thicknesses, such as Figure 1 As shown, the ion implantation layer can be divided into two areas to be corrected, and the thicknesses of the photoresist corresponding to the two areas to be corrected are a and b respectively.

[0036] Step S5: for any area to be corrected, a special correction model for the area to be corrected is established, and the area to be corrected is corrected based on the special correction model to generate a correction result for the area to be corrected.

[0037] A dedicated correction model is established for each area to be corrected. Different areas to be corrected correspond to different dedicated correction models. Different dedicated correction models involve different parameter settings. Each area to be corrected is corrected by the corresponding dedicated correction model to obtain a corresponding correction result.

[0038] Step S7, combining the correction results of the areas to be corrected to obtain an overall correction result of the ion implantation layer.

[0039] The ion implantation layer is divided into a plurality of areas to be corrected, and each area to be corrected is corrected by a dedicated correction model to obtain its own correction result, and then each correction result is spliced ​​in a corresponding order to obtain an overall correction result after the ion implantation layer is corrected as a whole. If the ion implantation layer contains only one area to be corrected, that is, the thickness of the photoresist in the ion implantation layer is evenly distributed, only the same dedicated correction model is needed to complete the correction. If the ion implantation layer contains multiple areas to be corrected, that is, the thickness of the photoresist in the ion implantation layer is unevenly distributed, multiple dedicated correction models corresponding to different photoresist thicknesses are required to achieve more accurate correction.

[0040] An embodiment of the present application provides a correction method for an ion implantation layer, comprising obtaining structural information associated with the ion implantation layer in a semiconductor material, wherein the structural information is used to characterize the distribution relationship between the ion implantation layer and other structural layers; dividing the ion implantation layer into a plurality of areas to be corrected according to the distribution relationship characterized by the structural information, wherein different areas to be corrected correspond to different photoresist thicknesses; for any area to be corrected, establishing a special correction model for the area to be corrected, and correcting the area to be corrected based on the special correction model to generate a correction result for the area to be corrected; and splicing the correction results of each area to be corrected to obtain an overall correction result for the ion implantation layer, thereby solving the technical problem that the OPC correction process of the ion implantation layer in the related art is not accurate enough, providing an OPC correction method that is more compatible with the semiconductor material structure, and achieving the technical effect of further reducing the edge placement error.

[0041] In some embodiments, according to the distribution relationship characterized by the structural information, the ion implantation layer is split into multiple areas to be corrected, including: in the direction of ion implantation, identifying the first type of area where the ion implantation layer and other structural layers exist at the same time, and identifying the second type of area where only the ion implantation layer exists; for any local area in the first type of area, determining the thickness of the photoresist between the upper surface of the ion implantation layer and the upper surface of the other structural layers in the local area; dividing the first type of area into one or more first sub-areas according to the determined thickness of the photoresist, wherein different first sub-areas have corresponding photoresist thicknesses; and treating each of the first sub-areas and the second type of area as multiple areas to be corrected obtained by splitting.

[0042] Wherein, in the direction of ion implantation, if there are both ion implantation layers and other structural layers, the ion implantation layers are classified as the first type of regions; if there is only the ion implantation layers, the ion implantation layers are classified as the second type of regions. Figure 1 As shown, from the cross-section, the direction of ion implantation is from top to bottom. The first type of area may include multiple local areas, some of which have the same thickness of photoresist, and some of which have different thicknesses. In the first type of area, the first type of area is divided into different first sub-areas according to the different thicknesses of the photoresist. Different first sub-areas correspond to different thicknesses of photoresist and have different corresponding dedicated correction models. The multiple areas to be corrected obtained by splitting the ion implantation layer may include multiple first sub-areas and second type areas. Among them, multiple first sub-areas correspond to multiple different OPC correction models; the thickness of the photoresist in the second type of area is evenly distributed, corresponding to one OPC correction model.

[0043] In some embodiments, establishing a dedicated correction model for the area to be corrected includes: acquiring photolithography data of the area to be corrected, the photolithography data at least including photoresist parameters and exposure conditions, wherein the photoresist parameters are used to characterize at least one of the number of photoresist layers, the thickness of each photoresist layer, and the transmittance of each photoresist layer, and the exposure conditions are used to characterize at least one of exposure energy, exposure focal length, and exposure light source; according to the exposure conditions, establishing an optical model for simulating light source information, and according to the photoresist parameters, establishing a photoresist model for simulating chemical reactions occurring in the photoresist; and determining the optical model and the photoresist model as the established dedicated correction model.

[0044] Among them, the optical model is used to simulate the light source information. The photoresist model is used to simulate the chemical reactions occurring in the photoresist. The speed and intensity of the chemical reactions occurring in photoresists of different thicknesses are different. Generally, a large amount of lithography data, such as thousands of lithography data, is required to facilitate the construction of a database required for training a special correction model. For example, the special correction model can be trained and constructed through OPCEDA software. The special correction model is continuously iterated and optimized using OPC EDA software until the model meets the predetermined accuracy requirements. The trained special correction model is applied to the actual lithography process to perform graphic correction so that the correction result is as close to the original design contour as possible and the edge placement error is as small as possible.

[0045] Specifically, each dedicated correction model is provided with a photoresist model, and different dedicated correction models are provided with at least different photoresist models. If the ion implantation layer includes multiple areas to be corrected, multiple dedicated correction models are provided accordingly. The multiple areas to be corrected contain photoresists of different thicknesses, and correspondingly, different dedicated correction models are required to perform different OPC corrections. Compared with the related art, in which areas of photoresists of different thicknesses correspond to a single OPC model, the OPC correction method provided in the embodiment of the present application can achieve more accurate OPC correction of the ion implantation layer, which is more compatible with the actual structure of the semiconductor material.

[0046] In some embodiments, correcting the area to be corrected based on the dedicated correction model includes: for adjacent first and second areas to be corrected, determining the adjacent areas of the first area to be corrected and the second area to be corrected on the surface of the semiconductor material; identifying the edge contour of the ion implantation layer in the adjacent area, and calculating the standard smoothing coefficient of the edge contour; in the process of correcting the first area to be corrected based on the first dedicated correction model and correcting the second area to be corrected based on the second dedicated correction model, after the correction of the current correction round is completed, simulating and splicing the correction results of the current correction round, and calculating the edge smoothing coefficient in the adjacent area after the simulated splicing; determining the error between the edge smoothing coefficient and the standard smoothing coefficient, and transferring the error to the next correction round, so as to correct the correction process in the next correction round through the error.

[0047] Among them, in the process of correcting the area to be corrected based on the special correction model, the ion implantation layer is divided into multiple areas to be corrected, and the special correction models corresponding to each area to be corrected are different. There is redundancy in the model accuracy range of each special correction model, resulting in height differences between the areas to be corrected when they are spliced ​​after correction, that is, the edge contour after correction is not smooth enough.

[0048] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the splicing result of the current sequence provided in the embodiment of this application. Please refer to Figure 5 , Figure 5 Schematic diagram of the original design contour provided for the embodiment of the present application. In theory, the connection between the first area to be corrected and the second area to be corrected should be a straight line, but due to the different dedicated correction models, there is error redundancy between the correction results, which will cause the joint after splicing to be uneven and have protrusions. In order to eliminate this height difference and make the corrected edge contour smoother, the correction method of the adjacent area is proposed.

[0049] Specifically, the process of correcting the area to be corrected based on the special correction model includes multiple correction rounds. After the current correction round is completed, the correction result of the current correction round is obtained. The adjacent area includes at least part of the first area to be corrected and part of the second area to be corrected. The standard smoothing coefficient is used to characterize the smoothness of the edge contour of the adjacent area in the original design contour, and is used to guide the correction direction. For example, the standard smoothing coefficient can be characterized by continuously deriving the curve function of the edge contour of the adjacent area in the original design contour or the curve slope. Simulate the splicing of multiple correction results to obtain the adjacent area of ​​the simulated splicing. The edge smoothing coefficient refers to the smoothness of the edge contour of the adjacent area after the simulated splicing. For example, the edge smoothing coefficient can be characterized by continuously deriving the curve function of the edge contour of the adjacent area in the simulated splicing or the curve slope. Calculate the error between the edge smoothing coefficient and the standard smoothing coefficient, and use it to guide the correction process in the next correction round, so that the edge contour of the adjacent area in the correction process is smoother.

[0050] In some embodiments, calculating the standard smoothing coefficient of the edge profile includes: determining an original design profile of the ion implantation layer, and determining a reference line that matches the edge profile in the original design profile; calculating a distance mean and a distance variance between the edge profile and the reference line, and using the distance mean and the distance variance as the standard smoothing coefficient of the edge profile.

[0051] The mean and variance of the distance between the original design contour and the reference line are calculated. Specifically, the method may be: using image processing to identify a set of pixel points of the original design contour; determining the position of the reference line, which may be a straight line, for example, Figure 4 As shown in the figure, the center line is set as the reference line; the distance from each pixel on the edge contour to the reference line is calculated; the distance mean is obtained by summing up all the calculated distances and dividing by the total number of pixels; the distance variance is obtained by calculating the square of the difference between the distance of each pixel and the mean, summing them up and dividing by the total number of pixels. The standard smoothing coefficient can be expressed by multiplying the distance mean and distance variance of the pixels of the original design contour by their respective weight coefficients.

[0052] In some embodiments, calculating the edge smoothing coefficient in the adjacent area after simulated stitching includes: identifying a simulated edge contour after simulated stitching in the adjacent area, calculating the distance mean and distance variance between the simulated edge contour and the reference line, and using the distance mean and distance variance corresponding to the simulated edge contour as the edge smoothing coefficient.

[0053] The distance mean and distance variance between the simulated edge contour and the reference line are calculated, and the specific method can be: using image processing to identify a set of pixel points of the simulated edge contour; determining the position of the reference line, which can be a straight line, for example, setting the center line as the reference line; calculating the distance from each pixel point on the simulated edge contour to the reference line; summing up all the calculated distances and dividing them by the total number of pixels to obtain the distance mean; by calculating the square of the difference between the distance of each pixel point and the mean, summing them and dividing them by the total number of pixels, the distance variance can be obtained. For example, the edge smoothing coefficient can be expressed by multiplying the distance mean and distance variance of the pixel points of the simulated edge contour by their respective weight coefficients.

[0054] In some embodiments, correcting the correction process in the next correction round through the error includes: taking the error as a joint correction coefficient, inputting it into the first dedicated correction model and the second dedicated correction model respectively, so that the first dedicated correction model and the second dedicated correction model can identify the correction direction represented by the error when generating their respective correction results, and adjust the initially generated correction results along the correction direction.

[0055] The error includes the distance mean error and the distance variance error. For example, the joint correction coefficient can be expressed by multiplying the distance mean error and the distance variance error by the corresponding weight coefficient. When the dedicated correction model generates the respective correction results according to the joint correction coefficient, the correction direction represented by the error is identified. For example, Figure 4 As shown, for the first area to be corrected, the first dedicated correction model is corrected according to the joint correction coefficient, so that the correction result of the first area to be corrected is adjusted along the "upward" correction direction. For the second area to be corrected, the second dedicated correction model is corrected according to the joint correction coefficient, so that the correction result of the second area to be corrected is adjusted along the "downward" correction direction. The adjacent area between the first area to be corrected and the second area to be corrected can be connected more smoothly, thereby eliminating the height difference.

[0056] In some embodiments, when the ion implantation layer is split into multiple areas to be corrected, each area to be corrected obtained by the splitting is assigned a respective splitting identifier, and a merge baseline of each area to be corrected is determined, and the merge baseline is inherited to the correction result of the area to be corrected; splicing the correction results of each area to be corrected includes: according to the splitting identifier of each area to be corrected, determining the splicing order of each correction result, and in the splicing process, aligning the merge baselines in each correction result.

[0057] Among them, the split mark is used to guide the stitching order of the correction results during the stitching process. For example, the split mark can be a number, a letter, or a combination of the two, which is used to uniquely identify and reference each area to be corrected during the stitching process. The merge baseline can be the above-mentioned reference line, which is used as an alignment reference for the correction results during the stitching process. The correction result includes the split mark and the merge baseline. During the stitching process, the correction results are spliced ​​in the order determined by the split mark, and the merge baselines of the correction results are aligned by adjusting the relative positions of the correction results, so that the edge placement error between the overall correction result and the original design contour is as small as possible.

[0058] An embodiment of the present application also provides a correction device for an ion implantation layer, the device comprising: a structural information acquisition unit, used to acquire structural information associated with the ion implantation layer in a semiconductor material, the structural information being used to characterize the distribution relationship between the ion implantation layer and other structural layers; a region splitting unit, used to split the ion implantation layer into a plurality of regions to be corrected according to the distribution relationship characterized by the structural information, wherein different regions to be corrected have different thicknesses of photoresist corresponding to them; a correction unit, used to establish a special correction model for any region to be corrected, and correct the region to be corrected based on the special correction model to generate a correction result for the region to be corrected; and a splicing unit, used to splice the correction results of the respective regions to be corrected to obtain an overall correction result for the ion implantation layer.

[0059] An embodiment of the present application further provides a semiconductor device, wherein an ion implantation layer in the semiconductor device is corrected according to the above-mentioned method for correcting an ion implantation layer.

[0060] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0061] The correction device for the ion implantation layer in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0062] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application, such as Figure 6As shown, the computer device includes: one or more processors, memory, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other, and can be installed on a common mainboard or installed in other ways as required. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor is taken as an example.

[0063] The processor may be a central processing unit, a network processor or a combination thereof. The processor may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0064] The memory stores instructions executable by at least one processor, so that the at least one processor executes the method shown in the above embodiment.

[0065] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0066] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory may also include a combination of the above types of memory. The computer device also includes a communication interface for the computer device to communicate with other devices or communication networks.

[0067] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0068] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0069] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0070] The apparatus described in the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0071] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0072] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0073] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0074] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0075] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0077] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0078] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0079] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for correcting an ion implantation layer, characterized in that: The method comprises: Acquiring structural information associated with the ion implantation layer in the semiconductor material, wherein the structural information is used to characterize the distribution relationship between the ion implantation layer and other structural layers; According to the distribution relationship represented by the structural information, the ion implantation layer is divided into a plurality of regions to be corrected, wherein different regions to be corrected have different thicknesses of photoresist; For any area to be corrected, a special correction model for the area to be corrected is established, and the area to be corrected is corrected based on the special correction model to generate a correction result for the area to be corrected; wherein, correcting the area to be corrected based on the special correction model includes: for adjacent first and second areas to be corrected, determining the adjacent areas of the first area to be corrected and the second area to be corrected on the surface of the semiconductor material; identifying the edge contour of the ion implantation layer in the adjacent area, and calculating the standard smoothing coefficient of the edge contour; in the process of correcting the first area to be corrected based on the first special correction model and correcting the second area to be corrected based on the second special correction model, after the correction of the current correction round is completed, the correction results of the current correction round are simulated and spliced, and the edge smoothing coefficient in the adjacent area after the simulated splicing is calculated; determining the error between the edge smoothing coefficient and the standard smoothing coefficient, and transferring the error to the next correction round, so as to correct the correction process in the next correction round by the error; The correction results of each of the areas to be corrected are spliced ​​together to obtain an overall correction result of the ion implantation layer.

2. The method according to claim 1, characterized in that According to the distribution relationship represented by the structural information, splitting the ion implantation layer into a plurality of areas to be corrected comprises: In the direction of ion implantation, identifying a first type of region where both the ion implantation layer and other structural layers exist, and identifying a second type of region where only the ion implantation layer exists; For any local area in the first type of area, determining the thickness of the photoresist between the upper surface of the ion implantation layer and the upper surface of other structural layers in the local area; Dividing the first type of area into one or more first sub-areas according to the determined thickness of the photoresist, wherein different first sub-areas have corresponding photoresist thicknesses of different types; The first sub-regions and the second-type regions are taken as a plurality of regions to be corrected obtained by splitting.

3. The method according to claim 1 or 2, characterized in that: Establishing the dedicated correction model for the area to be corrected includes: Acquire photolithography data of the area to be corrected, the photolithography data at least including photoresist parameters and exposure conditions, wherein the photoresist parameters are used to characterize at least one of the number of photoresist layers, the thickness of each photoresist layer, and the transmittance of each photoresist layer, and the exposure conditions are used to characterize at least one of exposure energy, exposure focal length, and exposure light source; According to the exposure conditions, an optical model for simulating light source information is established, and according to the photoresist parameters, a photoresist model for simulating chemical reactions occurring in the photoresist is established; The optical model and the photoresist model are determined as established dedicated correction models.

4. The method according to claim 1, characterized in that The standard smoothing coefficient for calculating the edge profile includes: Determining an original design profile of the ion implantation layer, and determining a reference line matching the edge profile in the original design profile; The mean distance and the distance variance between the edge contour and the reference line are calculated, and the mean distance and the distance variance are used as standard smoothing coefficients of the edge contour.

5. The method according to claim 4, characterized in that Calculating the edge smoothing coefficient in the adjacent area after simulated splicing includes: The simulated edge contour after simulated splicing is identified in the adjacent area, and the distance mean and distance variance between the simulated edge contour and the reference line are calculated, and the distance mean and distance variance corresponding to the simulated edge contour are used as the edge smoothing coefficient.

6. The method according to any one of claims 4 or 5, characterized in that: Correcting the correction process in the next correction round by using the error includes: The error is used as a joint correction coefficient and input into the first special correction model and the second special correction model respectively, so that the first special correction model and the second special correction model can identify the correction direction represented by the error when generating their respective correction results, and adjust the initially generated correction results along the correction direction.

7. The method according to claim 1, characterized in that When the ion implantation layer is split into a plurality of regions to be corrected, a split identifier is assigned to each of the split regions to be corrected, and a merge baseline of each region to be corrected is determined, and the merge baseline is inherited into the correction result of the region to be corrected; The step of splicing the correction results of the areas to be corrected comprises: According to the splitting marks of each area to be corrected, the splicing order of each correction result is determined, and during the splicing process, the merging baselines in each correction result are aligned.

8. A device for correcting an ion implantation layer, characterized in that: A method for correcting an ion implantation layer according to any one of claims 1 to 7 can be implemented, wherein the device comprises: A structural information acquisition unit, used to acquire structural information associated with the ion implantation layer in the semiconductor material, wherein the structural information is used to characterize the distribution relationship between the ion implantation layer and other structural layers; A region splitting unit, used for splitting the ion implantation layer into a plurality of regions to be corrected according to the distribution relationship represented by the structural information, wherein different regions to be corrected have different thicknesses of photoresist; A correction unit, for establishing a special correction model for any area to be corrected, and correcting the area to be corrected based on the special correction model to generate a correction result for the area to be corrected; The splicing unit is used to splice the correction results of each of the areas to be corrected to obtain the overall correction result of the ion implantation layer.

9. A semiconductor device, characterized in that: The ion implantation layer in the semiconductor device is corrected according to the method for correcting an ion implantation layer according to any one of claims 1 to 7.

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