Current detection and circuit protection method and system for chip

Abstract

The present invention provides a current detection and circuit protection method and system for a chip, which relates to the field of chip technology, and includes obtaining a current detection result of a target chip; comparing the current detection result with a preset current threshold, and if the target chip is overcurrent, adaptively determining multiple protection levels corresponding to the comparison result based on the comparison result of the current detection result and the preset current threshold, and determining a corresponding protection strategy based on the multiple protection levels; according to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling an adjustable current limiting module in a power supply circuit of the target chip, and at the end of each recovery stage, determining whether the current detection result exceeds the preset current threshold, and if so, returning to the previous recovery stage to continue recovery, until the power supply current of the target chip is restored to a normal working state within a preset recovery time.

Description

Technical Field

[0001] The present invention relates to chip technology, and in particular to a current detection and circuit protection method and system for a chip. Background Art

[0002] In the prior art, there are two main methods for chip overcurrent protection: one is to set an overcurrent protection circuit outside the chip, detect the power supply current of the chip, and cut off the chip power supply when overcurrent occurs, thereby protecting the chip from overcurrent damage. This method requires additional current detection and control circuits, which increases the cost and complexity of the system. The other is to integrate an overcurrent protection circuit inside the chip, and trigger a protection action when overcurrent occurs by monitoring the current of internal key nodes. Although this method saves external circuits, due to the limited space and resources inside the chip, the integrated overcurrent protection circuit is usually simple, and the protection granularity and strategy flexibility are insufficient.

[0003] In addition, most traditional overcurrent protection uses a single current threshold comparison and a one-size-fits-all protection strategy, that is, when the chip current exceeds the preset threshold, the power supply of the entire chip is directly cut off. Although this protection method is simple and reliable, it ignores the diversity of overcurrent faults and the different requirements of chip functions, and there are problems of insufficient protection or overprotection, which may lead to reduced chip availability or unnecessary protection actions. Summary of the invention

[0004] The embodiments of the present invention provide a current detection and circuit protection method and system for a chip, which can solve the problems in the prior art.

[0005] According to a first aspect of the embodiments of the present invention,

[0006] Provides a current detection and circuit protection method for a chip, including:

[0007] A clock source is set in the target chip, a high-frequency clock signal is generated by the clock source, and the high-frequency clock signal is divided and shaped in combination with a frequency divider and a comparator to obtain a chopping signal; an analog switch is used to perform chopping modulation on the current signal to be measured of the target chip; a multi-stage current mirror structure is used, and a fuzzy control algorithm is used to determine the gain control amount of the current signal to be measured, so as to realize dynamic detection of the current signal to be measured and obtain a current detection result;

[0008] Compare the current detection result with a preset current threshold to determine whether the target chip is overcurrent; if the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result according to the comparison result between the current detection result and the preset current threshold, and determine corresponding protection strategies based on the multiple protection levels;

[0009] According to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip. At the end of each recovery stage, it is judged whether the current detection result exceeds the preset current threshold. If it exceeds, it returns to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within the preset recovery time. The recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes.

[0010] According to a second aspect of the embodiments of the present invention,

[0011] Provide current detection and circuit protection systems for chips, including:

[0012] The first unit is used to set a clock source in the target chip, generate a high-frequency clock signal through the clock source, divide and shape the high-frequency clock signal in combination with a frequency divider and a comparator to obtain a chopping signal; use an analog switch to chop and modulate the current signal to be measured of the target chip; use a multi-stage current mirror structure and a fuzzy control algorithm to determine the gain control amount of the current signal to be measured, thereby realizing dynamic detection of the current signal to be measured and obtaining a current detection result;

[0013] The second unit is used to compare the current detection result with a preset current threshold to determine whether the target chip is overcurrent, and if the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result according to the comparison result between the current detection result and the preset current threshold, and determine a corresponding protection strategy based on the multiple protection levels;

[0014] The third unit is used to gradually restore the power supply current of the target chip in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip according to the protection strategy, and judge whether the current detection result exceeds the preset current threshold at the end of each recovery stage. If exceeded, return to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within a preset recovery time, wherein the recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes.

[0015] According to a third aspect of the embodiments of the present invention,

[0016] An electronic device is provided, comprising:

[0017] processor;

[0018] a memory for storing processor-executable instructions;

[0019] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0020] A fourth aspect of the embodiments of the present invention is:

[0021] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0022] The present invention adopts a method combining high-frequency clock signal generation with chopping modulation, which can effectively eliminate the DC component and low-frequency noise in the current signal to be measured, improve the sensitivity and accuracy of current detection, and realize reliable detection of small overcurrent signals. The dynamic amplification of the current signal to be measured is realized through a multi-level current mirror structure and a fuzzy control algorithm, and the amplification factor can be adaptively adjusted according to the change of the current amplitude, which can not only meet the detection requirements of different ranges, but also avoid signal saturation distortion, and expand the dynamic range of overcurrent detection.

[0023] According to the comparison between the current detection result and the preset threshold, multiple protection levels are adaptively determined, and corresponding protection strategies are adopted to achieve dynamic adjustment of the overcurrent protection granularity. Protection resources can be reasonably configured according to the severity of the overcurrent fault, which improves the availability of the chip while ensuring chip reliability. A phased recovery strategy is adopted to smoothly transition the chip's power supply current by controlling the adjustable current limiting module in the power supply circuit, avoiding secondary damage to the chip caused by current mutations during the recovery process, and improving the safety and reliability of overcurrent protection.

[0024] In the recovery process, a phased judgment and fallback mechanism is introduced to dynamically monitor the current recovery situation. Once an abnormality is found, it will return to the previous recovery stage in time, ensuring the stability and convergence of the recovery process and improving the success rate of recovery. Recovery curves with different slopes such as fast recovery, medium recovery and slow recovery are used for different overcurrent fault levels, which can balance the recovery speed and smoothness, minimize the recovery time and ensure the safety and controllability of the recovery process.

[0025] In summary, the adaptive multi-level overcurrent detection and protection method provided by the present invention overcomes the shortcomings of the prior art, such as insufficient overcurrent detection sensitivity, single protection granularity, and simple and crude recovery strategy, and realizes chip-level multi-level and refined overcurrent protection, which improves chip reliability while maximizing the system availability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of a current detection and circuit protection method for a chip according to an embodiment of the present invention;

[0027] Figure 2The figure is a schematic diagram of the structure of a current detection and circuit protection system for a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0030] Figure 1 FIG. 1 is a flow chart of a current detection and circuit protection method for a chip according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0031] S101. A clock source is set in the target chip, a high-frequency clock signal is generated by the clock source, and the high-frequency clock signal is divided and shaped by combining a frequency divider and a comparator to obtain a chopping signal; an analog switch is used to chop and modulate the current signal to be measured of the target chip; a multi-stage current mirror structure is used, and a gain control amount of the current signal to be measured is determined by a fuzzy control algorithm to achieve dynamic detection of the current signal to be measured, and obtain a current detection result;

[0032] S102. Compare the current detection result with the preset current threshold to determine whether the target chip is overcurrent. If the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result based on the comparison result of the current detection result with the preset current threshold, and determine the corresponding protection strategy based on the multiple protection levels;

[0033] S103. According to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip. At the end of each recovery stage, it is determined whether the current detection result exceeds the preset current threshold. If it exceeds, the recovery is returned to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within the preset recovery time. The recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes.

[0034] For example, in order to achieve refined control of the power supply current, it is necessary to integrate an adjustable current limiting module into the power supply circuit of the target chip. The main function of the adjustable current limiting module is to dynamically adjust the upper limit of the chip's power supply current according to the control signal to prevent the current from exceeding the safety threshold. The specific design steps of the adjustable current limiting module are as follows:

[0035] Current detection circuit: A sampling resistor is connected in series to the power supply line of the chip, and a differential amplifier is connected to both ends of the sampling resistor to achieve real-time detection of the power supply current. The output voltage of the differential amplifier is linearly related to the power supply current and can be used as the current detection result.

[0036] Threshold comparison circuit: compares the current detection result with the preset current threshold to determine whether the current supply current exceeds the safe range. The comparison circuit can be implemented in the form of an analog comparator or an ADC + digital comparator.

[0037] Current limiting control circuit: According to the threshold comparison result and the recovery phase control signal, the parameters of the current limiting circuit (such as reference voltage, feedback resistance, etc.) are dynamically adjusted to change the upper limit of the supply current. The current limiting control circuit can be implemented using components such as digital potentiometers and analog switches.

[0038] Current limiting execution circuit: The current limiting execution circuit usually adopts a linear regulator topology composed of a PMOS tube or an NMOS tube. By controlling the gate voltage of the MOS tube, its on-resistance can be adjusted, thereby changing the size of the supply current. In order to improve the current limiting accuracy and response speed, a multi-level nested current limiting execution circuit can be used.

[0039] By integrating the above functional modules, the adjustable current limit module can realize dynamic regulation and precise control of the target chip power supply current, providing hardware support for the phased recovery strategy.

[0040] After the overcurrent protection is triggered, the phased and gradual recovery strategy restores the power supply current of the target chip in stages and gradually by controlling the adjustable current limiting module until it returns to the normal operating level.

[0041] Recovery phase division: The recovery process is divided into several phases, each corresponding to a different current recovery slope and duration. The division of the recovery phase needs to comprehensively consider factors such as the chip's current-time characteristics, thermal capacitance effect, and load characteristics. Generally, it can be divided into three phases: fast recovery, medium recovery, and slow recovery. The fast recovery phase has the largest current slope and the shortest recovery time; the slow recovery phase has the smallest current slope and the longest recovery time.

[0042] Switching during the recovery phase: When recovery begins, the system first enters the fast recovery phase, and gradually increases the upper limit of the power supply current with a larger current slope by controlling the adjustable current limit module. At the end of the fast recovery phase, it is determined whether the current current detection result exceeds the preset threshold: if it does not exceed the threshold, it means that the fast recovery is successful, and the system enters the medium-speed recovery phase to continue to increase the power supply current; if it exceeds the threshold, it means that the fast recovery is too aggressive and may trigger a secondary overcurrent, and the system needs to return to the previous recovery state and switch to the slow recovery phase.

[0043] Similarly, at the end of the medium-speed recovery stage, if the current detection result exceeds the threshold, the system returns to the fast recovery stage; otherwise, the system enters the slow recovery stage.

[0044] Recovery completion judgment: In each recovery stage, the difference between the current current detection result and the preset threshold is monitored in real time, and the control parameters of the adjustable current limit module are dynamically adjusted according to the difference. When the current detection result is stable within the preset threshold and the duration exceeds a certain range, the current recovery stage is judged to be completed and enter the next recovery stage.

[0045] Recovery timeout processing: In order to prevent the recovery process from falling into an infinite loop, a recovery timeout mechanism needs to be set. When the recovery starts, a recovery timer is started to record the duration of the entire recovery process. When the recovery timer exceeds the preset recovery timeout threshold, the recovery process is forced to end and a recovery failure event is reported.

[0046] Recovery success judgment: When the power supply current of the target chip is successfully restored to the normal working range and remains stable for a period of time, the entire recovery process is judged to be successfully completed. At this time, the control of the adjustable current limit module can be released to return the chip to a non-protected state.

[0047] The key to the phased recovery strategy is to dynamically adjust the recovery slope and switch the recovery phase according to the current detection results and the preset threshold, so as to shorten the recovery time as much as possible while ensuring the recovery reliability. By reasonably dividing the recovery phases and setting appropriate phase switching conditions and timeout mechanisms, the supply current can be smoothly and controllably restored, avoiding current mutations or secondary overcurrents during the recovery process.

[0048] In summary, this application proposes a phased and gradual recovery strategy for overcurrent protection, which realizes phased and refined control of the power supply current by integrating an adjustable current limiting module in the power supply circuit of the target chip. The recovery process dynamically switches the recovery stage and adjusts the recovery slope according to the current detection result, shortening the recovery time while preventing secondary overcurrent. Compared with the traditional one-time recovery strategy, the phased and gradual recovery strategy has the advantages of reliable recovery, controllable time, and strong adaptability. It can significantly improve the completeness and robustness of the chip overcurrent protection and reduce the impact of overcurrent faults on chip availability.

[0049] The present invention adopts a method combining high-frequency clock signal generation with chopping modulation, which can effectively eliminate the DC component and low-frequency noise in the current signal to be measured, improve the sensitivity and accuracy of current detection, and realize reliable detection of small overcurrent signals. The dynamic amplification of the current signal to be measured is realized through a multi-level current mirror structure and a fuzzy control algorithm, and the amplification factor can be adaptively adjusted according to the change of the current amplitude, which can not only meet the detection requirements of different ranges, but also avoid signal saturation distortion, and expand the dynamic range of overcurrent detection.

[0050] According to the comparison between the current detection result and the preset threshold, multiple protection levels are adaptively determined, and corresponding protection strategies are adopted to achieve dynamic adjustment of the overcurrent protection granularity. Protection resources can be reasonably configured according to the severity of the overcurrent fault, which improves the availability of the chip while ensuring chip reliability. A phased recovery strategy is adopted to smoothly transition the chip's power supply current by controlling the adjustable current limiting module in the power supply circuit, avoiding secondary damage to the chip caused by current mutations during the recovery process, and improving the safety and reliability of overcurrent protection.

[0051] In the recovery process, a phased judgment and fallback mechanism is introduced to dynamically monitor the current recovery situation. Once an abnormality is found, it will return to the previous recovery stage in time, ensuring the stability and convergence of the recovery process and improving the success rate of recovery. Recovery curves with different slopes such as fast recovery, medium recovery and slow recovery are used for different overcurrent fault levels, which can balance the recovery speed and smoothness, minimize the recovery time and ensure the safety and controllability of the recovery process.

[0052] In summary, the adaptive multi-level overcurrent detection and protection method provided by the present invention overcomes the shortcomings of the prior art, such as insufficient overcurrent detection sensitivity, single protection granularity, and simple and crude recovery strategy, and realizes chip-level multi-level and refined overcurrent protection, which improves chip reliability while maximizing the system availability.

[0053] In an optional embodiment,

[0054] A clock source is set in the target chip, a high-frequency clock signal is generated by the clock source, and the high-frequency clock signal is divided and shaped in combination with a frequency divider and a comparator to obtain a chopping signal; an analog switch is used to chop and modulate the current signal to be measured of the target chip; a multi-stage current mirror structure is used, and a fuzzy control algorithm is used to determine the gain control amount of the current signal to be measured, so as to realize dynamic detection of the current signal to be measured, and the current detection results obtained include:

[0055] A clock source is used to generate a high-frequency clock signal, and a frequency divider is used to divide the high-frequency clock signal, and a comparator is used to shape the divided high-frequency clock signal to obtain a square wave signal as a chopping signal; an analog switch is used to perform chopping modulation on the current signal to be measured, and the chopping signal is used to control the conduction and shutdown of the analog switch to achieve modulation of the current signal to be measured, and a holding capacitor is connected in parallel to the output end of the analog switch to hold the modulated current signal to be measured;

[0056] A multi-stage current mirror structure is adopted, an adjustable resistor or an adjustable current source is added to the bias circuit of each stage of the current mirror, and the modulated current signal to be measured is amplified to obtain an amplified current signal to be measured;

[0057] Based on a pre-constructed fuzzy rule base, a fuzzy control algorithm is adopted, and the gain of the multi-stage current mirror is adaptively adjusted according to the amplitude of the amplified current signal to be measured, and the amplitude of the amplified current signal to be measured is divided into several fuzzy subsets, and a corresponding gain control strategy is set for each fuzzy subset. The gain control amount of the current signal to be measured is determined by using fuzzy reasoning and defuzzification methods, so as to realize dynamic detection of the current signal to be measured and obtain the current detection result.

[0058] For example, in order to achieve high-precision and high-sensitivity chip overcurrent detection, this paper proposes a current detection method based on chopping modulation. First, a clock source is set in the target chip, and a high-frequency clock signal is generated through the clock source. Considering that directly using a high-frequency clock signal for chopping modulation may introduce large switching noise, it is necessary to preprocess the high-frequency clock signal.

[0059] This scheme uses a frequency divider to divide the high-frequency clock signal, reduce the frequency of the clock signal, and reduce the switching noise in the chopping modulation process. Although the frequency of the divided clock signal is reduced, the waveform quality is reduced, and there is a problem of slow rising and falling edges, which is not conducive to the accuracy and efficiency of chopping modulation. To this end, this scheme connects a comparator in series at the back of the frequency divider, and uses the hysteresis characteristics of the comparator to shape the divided clock signal to obtain a square wave signal with steep edges as the chopping signal.

[0060] After obtaining the chopping signal, the analog switch is used to chop and modulate the current signal to be measured of the target chip. Specifically, the chopping signal is used to control the on and off of the analog switch. When the chopping signal is at a high level, the analog switch is turned on, and the current signal to be measured is sampled and output through the analog switch; when the chopping signal is at a low level, the analog switch is turned off, and the current signal to be measured is blocked. The modulation of the current signal to be measured is achieved through the periodic change of the chopping signal.

[0061] In order to maintain the modulated current signal to be measured, a holding capacitor is connected in parallel to the output end of the analog switch. When the analog switch is turned on, the holding capacitor samples and holds the modulated current signal to be measured; when the analog switch is turned off, the holding capacitor maintains the voltage value of the last sample until the next chopping cycle arrives. The holding capacitor avoids the loss of the modulated signal and provides a continuous signal input for subsequent current detection.

[0062] Although chopping modulation can effectively extract the current signal to be measured, the amplitude of the modulated signal is small and the signal-to-noise ratio is not high, which is not conducive to subsequent current detection and overcurrent judgment. In order to amplify the modulated current signal to be measured, this scheme adopts a multi-stage current mirror structure to amplify the signal.

[0063] The multi-stage current mirror structure is composed of multiple basic current mirror units connected in series. Each stage of the current mirror amplifies the input signal by a certain multiple. The total amplification factor of the multi-stage current mirror is equal to the product of the amplification factors of each stage. Compared with the single-stage current mirror, the multi-stage current mirror can provide a higher amplification factor and has better isolation and linearity.

[0064] In order to achieve the adjustability of the current mirror gain, an adjustable resistor or an adjustable current source is added to the bias circuit of each current mirror. By adjusting the adjustable element in the bias circuit, the amplification factor of the current mirror can be continuously changed to achieve dynamic amplification of the current signal to be measured. Compared with the fixed gain current mirror, the adjustable gain current mirror can adaptively adjust the amplification factor according to the amplitude of the signal to be measured, maximize the signal-to-noise ratio while ensuring that the signal is not distorted, and expand the dynamic range of current detection.

[0065] In order to further optimize the dynamic amplification performance of the multi-stage current mirror structure, this scheme introduces an adaptive gain control strategy. Based on fuzzy control theory, a fuzzy control algorithm is used to adaptively adjust the gain of the current mirror. The core of this strategy is to dynamically determine the control amount of the current mirror gain according to the amplitude characteristics of the current signal to be measured, so as to optimize the signal amplification process.

[0066] First, a complete fuzzy rule base is pre-built based on expert experience and test data. The fuzzy rule base defines the fuzzy mapping relationship between the amplitude of the current signal to be measured and the gain of the current mirror, which is expressed in the form of IF-THEN statements, for example: "IF the signal amplitude is small THEN the gain is large". The establishment of the fuzzy rule base needs to comprehensively consider multiple performance indicators such as signal detection accuracy, amplification linearity, noise suppression, etc., in order to obtain the best gain control effect.

[0067] Secondly, the amplitude of the amplified current signal to be measured is divided into several fuzzy subsets, such as small, medium, large, etc. Each fuzzy subset corresponds to a specific amplitude range, and the membership function is used to describe the degree to which the measured signal belongs to each fuzzy subset. Commonly used membership functions include triangular function, trapezoidal function, Gaussian function, etc., and the appropriate function type can be selected according to actual needs.

[0068] Then, the fuzzy control amount of the current mirror gain is determined by combining the fuzzy rule base and the membership function. The fuzzy reasoning process includes three steps: 1) calculating the membership of the amplitude of the measured signal to each fuzzy subset; 2) activating the corresponding fuzzy control rules according to the membership and fuzzy rule base; 3) synthesizing the activated fuzzy control rules to obtain the fuzzy control amount of the gain. Commonly used fuzzy reasoning methods include Mamdani reasoning and Sugeno reasoning. The former reasoning result is a fuzzy set, and the latter reasoning result is a definite value.

[0069] Finally, through defuzzification, the fuzzy control quantity of the gain is converted into an actual executable precise control quantity. The purpose of defuzzification is to extract the definite value that best represents the fuzzy set from the fuzzy result obtained by reasoning as the optimal control quantity of the current mirror gain. Commonly used defuzzification methods include the centroid method, the maximum membership method, the weighted average method, etc.

[0070] Through the above steps, adaptive gain control of the current signal to be measured is realized. While dynamically amplifying the signal, the gain configuration of the current mirror can be optimized according to the amplitude characteristics of the signal, overcoming the shortcomings of fixed gain or graded gain schemes and improving the accuracy and reliability of overcurrent detection.

[0071] In summary, this scheme uses chopping modulation to extract the current signal to be measured, combines the multi-stage current mirror structure and adaptive gain control strategy to dynamically amplify the signal, and finally obtains a current detection result with appropriate amplitude and high signal-to-noise ratio, which provides reliable data support for subsequent overcurrent judgment and fault protection. Compared with traditional current detection methods, this scheme has the advantages of high detection sensitivity, wide dynamic range, and strong anti-interference ability, providing a new technical idea for chip-level overcurrent protection.

[0072] In an optional embodiment,

[0073] Based on the pre-built fuzzy rule base, the fuzzy control algorithm is adopted, and the gain of the multi-stage current mirror is adaptively adjusted according to the amplitude of the amplified current signal to be measured, and the amplitude of the amplified current signal to be measured is divided into several fuzzy subsets, and a corresponding gain control strategy is set for each fuzzy subset. The gain control amount of the current signal to be measured is determined by using fuzzy reasoning and defuzzification methods, and dynamic detection of the current signal to be measured is realized, and the current detection results obtained include:

[0074] According to the amplitude range of the current signal to be measured, the amplitude of the current signal to be measured is divided into multiple fuzzy subsets, and a triangular membership function is used to represent each fuzzy subset;

[0075] For each fuzzy subset, a corresponding multi-stage current mirror gain control strategy is set;

[0076] Constructing a fuzzy rule base, wherein the fuzzy rule base is composed of a plurality of fuzzy control rules, and each of the fuzzy control rules uses an If-Then statement to represent the relationship between the fuzzy subset and the gain control strategy;

[0077] Acquire the actual amplitude of the current signal to be measured, and perform fuzzy reasoning on the fuzzy rule base according to the actual amplitude using the Mamdani reasoning method to obtain the fuzzy gain control amount of the multi-stage current mirror, wherein the Mamdani reasoning method includes membership calculation, rule matching and rule synthesis;

[0078] The membership calculation is to calculate the membership of each fuzzy subset according to the actual amplitude of the current signal to be measured;

[0079] The rule matching is to match the membership degree with each fuzzy control rule in the fuzzy rule base and calculate the activation degree of each fuzzy control rule;

[0080] The rule synthesis adopts the maximum-minimum synthesis rule to synthesize the activation degree of each fuzzy control rule and its corresponding gain control strategy to obtain the final fuzzy reasoning result;

[0081] Defuzzification is performed on the fuzzy gain control quantity by using the centroid method to obtain a multi-stage current mirror gain control quantity;

[0082] According to the gain control amount of the multi-stage current mirror, the gain of the multi-stage current mirror is adaptively adjusted to amplify the current signal to be measured, thereby realizing dynamic detection of the current signal to be measured and obtaining a final current detection result.

[0083] For example, according to the amplitude range of the current signal to be measured, it is divided into multiple fuzzy subsets. The division of fuzzy subsets needs to comprehensively consider factors such as the accuracy requirements of current detection, the dynamic range of the signal, and the computational complexity of the system. Usually, the appropriate number of fuzzy subsets and boundary values ​​are determined by combining expert experience and experimental data. A typical division scheme is to divide the amplitude of the current signal to be measured into three fuzzy subsets of "small", "medium", and "large", where "small" corresponds to a low amplitude interval, "medium" corresponds to a medium amplitude interval, and "large" corresponds to a high amplitude interval.

[0084] In order to describe the degree to which the current signal to be measured belongs to each fuzzy subset, it is necessary to define a corresponding membership function for each fuzzy subset. The membership function is a mathematical function that maps the input variable to the interval [0, 1], indicating the degree of membership of the input variable to the fuzzy subset. Commonly used membership functions include triangular function, trapezoidal function, Gaussian function, etc. This scheme selects the triangular membership function. By adjusting the vertex position of the triangular function, the shape of the membership function can be flexibly controlled to better fit the amplitude distribution characteristics of the signal to be measured.

[0085] The fuzzy rule base is the core of fuzzy control, which contains a series of language rules for describing control strategies. The construction of the fuzzy rule base requires the comprehensive use of expert knowledge and control experience to transform qualitative control ideas into quantitative control rules. In this scheme, the fuzzy rule base consists of multiple fuzzy control rules in the form of If-Then, and each rule establishes a mapping relationship between fuzzy subsets and multi-stage current mirror gain control strategies. The antecedent (If part) of the rule describes the fuzzy subset to which the amplitude of the signal to be measured belongs, and the consequent (Then part) gives the corresponding gain control strategy. A typical fuzzy control rule can be expressed as:

[0086] If the amplitude of the signal to be measured is small, then the gain of the multi-stage current mirror is large;

[0087] This rule indicates that when the amplitude of the signal to be measured is in the "small" fuzzy subset, a "large" gain control strategy should be selected, that is, a larger multi-stage current mirror magnification should be set to improve the detection sensitivity. Similarly, a series of fuzzy control rules can be designed according to different amplitude fuzzy subsets to form a complete fuzzy rule base. The rationality and completeness of the fuzzy rule base directly affect the control performance, so it needs to be repeatedly demonstrated and optimized in the design stage.

[0088] Fuzzy reasoning is to make decisions based on the actual amplitude of the current signal to be measured using the fuzzy rule base to obtain the control amount of the multi-stage current mirror gain. This scheme adopts the Mamdani reasoning method, which consists of three steps: membership calculation, rule matching and rule synthesis.

[0089] Among them, the membership degree calculation: according to the actual amplitude of the current signal to be measured, the membership degree of each fuzzy subset is calculated respectively. The membership degree calculation adopts the aforementioned triangular membership function, and by substituting the actual amplitude, a set of membership values ​​representing the degree of membership is obtained.

[0090] Rule matching: Match the membership value with each rule in the fuzzy rule base and calculate the activation of each rule. The activation of a rule indicates the degree to which the signal to be tested satisfies the antecedent conditions of the rule. The minimum value of the membership is usually used as the activation.

[0091] Rule synthesis: Use the maximum-minimum synthesis rule to synthesize the activated fuzzy control rules to obtain the final result of fuzzy reasoning. The basic idea of ​​the maximum-minimum synthesis rule is: first, restrict the membership degree of the output part of each rule, then take the maximum value of the output results of all rules to form a synthesized fuzzy set as the output result of reasoning.

[0092] Through fuzzy reasoning, the fuzzy control quantity representing the multi-level current mirror gain is obtained. This fuzzy control quantity integrates the influence of various fuzzy control rules and embodies the control strategy of adaptive gain adjustment.

[0093] The gain control quantity obtained by fuzzy reasoning is a fuzzy set, which needs to be converted into an accurate control quantity value through defuzzification processing so that it can be actually applied to the multi-stage current mirror circuit. This scheme uses the centroid method for defuzzification. Its basic principle is to solve the centroid abscissa of the fuzzy set membership function curve as the clarified control quantity output. Through the centroid method, a definite value that can represent the overall characteristics of the fuzzy set can be obtained as the gain control quantity of the multi-stage current mirror.

[0094] According to the gain control amount obtained by the defuzzification process, the amplification factor of the multi-stage current mirror is adaptively adjusted. Specifically, by changing the parameter value of the variable resistor or current source in the multi-stage current mirror bias circuit, the gain is continuously adjustable. The gain adjustment process needs to consider factors such as the frequency response, stability, and linearity of the circuit to ensure that good amplification characteristics are maintained over the entire dynamic range.

[0095] After the gain adjustment is completed, the multi-stage current mirror amplifies the input current signal to be measured to obtain a detection result with appropriate amplitude. Due to the use of an adaptive gain control strategy, the amplified signal can maintain a high signal-to-noise ratio and resolution in different amplitude ranges, effectively improving the dynamic performance of overcurrent detection. Finally, the amplified signal is sent to the subsequent circuit for threshold comparison and logical judgment to achieve real-time overcurrent monitoring and fault diagnosis of the target chip.

[0096] In summary, this application proposes an adaptive gain adjustment strategy based on fuzzy control, which realizes the dynamic detection of the current signal to be measured through a series of methods such as fuzzy subset division, membership function selection, fuzzy rule base construction, fuzzy reasoning and defuzzification. This strategy overcomes the shortcomings of traditional fixed gain or graded gain schemes, and can adaptively adjust the amplification factor of the multi-stage current mirror according to the change of signal amplitude, while ensuring the detection sensitivity, significantly expanding the dynamic range of detection. Compared with the existing technology, this scheme has stronger environmental adaptability and higher detection accuracy, and provides new ideas and methods for chip-level overcurrent protection.

[0097] In an optional embodiment,

[0098] According to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip, and at the end of each recovery stage, it is judged whether the current detection result exceeds the preset current threshold value, and if it exceeds, it returns to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within the preset recovery time. The method includes:

[0099] According to the current abnormality threshold, normal working current and preset recovery time of the target chip, the number of stages of staged recovery, the current increase and duration of each stage are determined;

[0100] An adjustable current limiting module is set in the power supply circuit of the target chip, wherein the adjustable current limiting module is composed of a plurality of current limiting units connected in parallel, each current limiting unit controls whether to be connected to the circuit through a switch tube, and a hierarchical limitation of the power supply current is achieved by controlling the conduction state of the switch tube;

[0101] When the power supply current of the target chip is detected to be abnormal, a phased recovery process is started:

[0102] Entering the first recovery stage, by controlling the adjustable current limiting module, the power supply current is gradually increased from the initial state to the current increase of the first stage, and the duration of the first stage is continued, and the change of the power supply current is monitored in real time;

[0103] At the end of the first recovery phase, determine whether the power supply current exceeds the current abnormality threshold. If so, return to the initial state, reduce the recovery amplitude, and restart the recovery. If not, enter the next recovery phase.

[0104] Repeat the steps of entering the recovery phase, gradually increasing the current gain, and determining whether the power supply current exceeds the abnormal current threshold until all recovery phases are completed, and restore the power supply current to the normal operating current. During the entire recovery process, dynamically adjust the recovery speed and amplitude based on the current changes monitored in real time.

[0105] For example, the key to the phased recovery strategy is to reasonably set the number of recovery stages, the current increase and duration of each stage, etc. The selection of these parameters needs to comprehensively consider the following factors:

[0106] Abnormal current threshold of the target chip: The abnormal current threshold is the basis for judging whether the protection mechanism needs to be activated, and is usually determined based on factors such as the chip's process parameters, power consumption characteristics, and reliability requirements. During the recovery process, the power supply current must not exceed this threshold, otherwise it may cause secondary damage to the chip.

[0107] Normal operating current of the target chip: Normal operating current is the target value of the recovery process, which indicates the steady-state current consumption of the chip in a normal functional state. The recovery process needs to gradually restore the power supply current from an abnormal state to a normal operating current within a preset time to ensure the functional availability of the chip.

[0108] Default recovery time: The default recovery time indicates the maximum allowed time from starting the protection mechanism to completing the recovery. This time needs to be determined based on the real-time requirements of the system and the fault recovery time target. It is necessary to ensure the timeliness of recovery while leaving enough margin to avoid new problems caused by overly aggressive recovery strategies.

[0109] Taking the above factors into consideration, a set of optimized recovery parameters can be obtained through simulation analysis and empirical formulas. For example, the current increase in each stage can be set in a geometric progression, that is, the current increase in the next stage is a fixed multiple of the previous stage. This method can quickly increase the current in the early stage of recovery, and gradually reduce the recovery amplitude when approaching the normal working current, which not only speeds up the recovery speed but also avoids drastic fluctuations in current. The duration of each stage can be evenly divided according to the preset recovery time and the number of stages, or a progressive distribution strategy can be adopted, that is, the duration in the early stage of recovery is shorter, and the duration in the later stage is gradually extended, which is consistent with the changing trend of the current increase.

[0110] The adjustable current limit module is the core hardware for realizing phased recovery. Its main function is to limit and dynamically adjust the power supply current of the target chip in stages. A typical adjustable current limit module consists of multiple current limit units in parallel, each of which includes a current limiting device (such as a resistor, MOSFET, etc.) and a control switch. By controlling the conduction state of the switch, the current limit unit can be selected and bypassed, thereby achieving graded adjustment of the total current. The design of the adjustable current limit module needs to consider the following aspects:

[0111] Selection of current limiting unit: The selection of current limiting unit needs to comprehensively consider factors such as on-resistance, power consumption, area, etc. For low current applications, resistors can be used as current limiting devices; for high current applications, devices such as power MOSFET can be used to reduce conduction losses.

[0112] The number of current limiting units and current distribution: The number of current limiting units determines the resolution of current regulation, and is usually selected as a power of 2 (such as 4, 8, 16, etc.). The current distribution of each current limiting unit can be equal or weighted. The equal circuit structure is simple, while the weighted method can optimize the linearity of current regulation.

[0113] Control switch design: The design of the control switch needs to consider factors such as on-resistance, switching speed, and drive power consumption. Commonly used control switches include MOS tubes, transmission gates, etc., which can be selected according to specific application scenarios.

[0114] Current detection and feedback circuit: In order to achieve closed-loop control, it is necessary to integrate current detection and feedback circuits in the adjustable current limiting module. Current detection can be achieved by using shunt resistors or Hall sensors, and the feedback circuit can use a proportional-integral controller composed of an operational amplifier to compare the detected current value with the set value and output a control signal to adjust the conduction state of the current limiting module. By reasonably designing the topology and parameters of the adjustable current limiting module, the power supply current of the target chip can be accurately controlled, providing hardware support for the staged recovery strategy.

[0115] Based on the adjustable current limit module, the phased recovery strategy can be implemented by the following algorithm:

[0116] 1. Initialization: According to the preset recovery parameters, determine the number of recovery stages N and the current increase △ in each stage I n and duration △ t n , and set the current stage variable n to 0, limiting the power supply current of the target chip to the initial value I 0 .

[0117] 2. Enter the recovery phase: increase the current phase variable n by 1, and control the adjustable current limit module to reduce the supply current from the previous phase value to I n-1 Gradually increase to I n = I n-1 +△ I n .

[0118] 3. Monitoring current: duration of the nth stage △ t n The system monitors the changes of the power supply current in real time and compares the current value with the abnormal current threshold. I max Make a comparison.

[0119] 4. Determine whether the limit is exceeded: If the power supply current exceeds the current abnormality threshold in the nth stage, it is determined that an abnormality occurs during the recovery process, and go to step 5; otherwise, go to step 6.

[0120] 5. Exception handling: If an exception occurs during the recovery process, return to the previous recovery stage, decrement the current stage variable n by 1, and adjust the recovery parameters of the subsequent stages according to the actual situation (such as reducing the current increase, extending the duration, etc.), and then re-enter step 2. If it has returned to the initial stage (i.e. n=0), start other exception handling mechanisms (such as power-off protection, alarm, etc.) and end the recovery process.

[0121] 6. Determine whether it is completed: If the current stage variable n is equal to the total stage number N, it means that all recovery stages have been completed and the power supply current has returned to the normal working current, and go to step 7; otherwise, go to step 2 and enter the next recovery stage.

[0122] 7. Recovery completed: Outputs a recovery completed signal and returns the control of the adjustable current limit module to the normal power supply control logic, ending the staged recovery process.

[0123] During the entire recovery process, the algorithm dynamically adjusts the recovery speed and amplitude according to the real-time monitoring of current changes, achieving adaptive recovery of the power supply current. At the same time, by setting up a recovery abnormality judgment and processing mechanism, the safety and controllability of the recovery process are guaranteed.

[0124] In summary, this application proposes a phased recovery strategy for chip-level overcurrent protection. By introducing an adjustable current limiting module and an adaptive recovery algorithm, it achieves precise control and gradual recovery of the target chip power supply current, while meeting functional safety requirements and improving system availability and recovery efficiency. Compared with traditional one-time recovery or fixed-time recovery, this strategy can dynamically adjust the recovery process according to the specific circumstances of the current anomaly, avoiding violent current fluctuations and repeated anomalies, and providing a new solution for chip-level overcurrent protection.

[0125] In an optional embodiment,

[0126] The method further comprises:

[0127] According to the current abnormality characteristics and recovery requirements of the target chip, the entire recovery process is divided into multiple sub-stages, each of which is responsible for the current recovery task within the corresponding recovery target range;

[0128] Select one of the multiple sub-phases as the main phase and the rest as slave phases. The main phase is responsible for coordinating and scheduling the recovery tasks of each slave phase and supervising the execution of the entire recovery process.

[0129] An independent current recovery module is deployed in each slave stage, including an adjustable current limiting unit, a current detection unit and a recovery control unit. Each recovery module autonomously performs current recovery operations according to the recovery tasks and requirements of the sub-stage to which it belongs;

[0130] Establish a communication and synchronization mechanism between the master and slave stages. The master stage is connected to each slave stage through a communication bus or a dedicated link to implement recovery task issuance, progress monitoring and exception handling functions.

[0131] Start the multi-stage collaborative recovery process. The master stage assigns recovery tasks to each slave stage and issues recovery parameters and control instructions. After receiving the recovery parameters and control instructions, the slave stage immediately starts the local recovery operation.

[0132] During the recovery process, the slave stage dynamically adjusts the local recovery strategy based on the real-time monitored current status and recovery progress, and feeds back the recovery progress, current status and other information to the master stage in real time;

[0133] When a slave stage experiences a sudden current change or a recovery failure, the slave stage first starts the local exception handling mechanism to try to recover autonomously. If the recovery fails, it sends an exception report to the master stage to request assistance.

[0134] After receiving the exception report from the slave stage, the master stage starts the exception handling process and takes measures such as reallocating tasks and suspending recovery of some slave stages according to the severity of the exception.

[0135] For example, the primary task of the multi-stage collaborative recovery strategy is to divide the entire recovery process into multiple sub-stages according to the current anomaly characteristics and recovery requirements of the target chip. Each sub-stage is responsible for the current recovery task within the corresponding recovery target range, and through reasonable task allocation and collaborative execution, the global recovery target can be achieved step by step.

[0136] Time and amplitude characteristics of current anomalies: Different types and degrees of current anomalies have different recovery difficulties and required time. It is necessary to reasonably divide the recovery stages according to the time and amplitude characteristics of current anomalies to ensure that the task difficulty and time requirements of each stage match.

[0137] Criticality of chip functional modules: Different functional modules of the chip have different reliance on power supply current, and the current recovery priority of critical modules is higher. It is necessary to reasonably divide the recovery stages according to the criticality of the functional modules, and give priority to ensuring the current recovery of critical modules.

[0138] Real-time and reliability requirements of the recovery process: The real-time and reliability requirements of the recovery process are also important bases for phase division. For scenarios with high real-time requirements, the number of recovery phases needs to be minimized to shorten the recovery time; for scenarios with high reliability requirements, the number of recovery phases needs to be appropriately increased to improve the fault tolerance of recovery.

[0139] Taking all the above factors into consideration, the optimal stage division scheme can be automatically generated by using heuristic algorithms, dynamic programming and other methods. For example, a preliminary division can be made based on the time and amplitude characteristics of the current anomaly, and then fine-tuned based on the criticality and recovery requirements of the chip functional modules. Finally, a stage division scheme that meets all constraints can be obtained through simulation verification and iterative optimization.

[0140] After dividing multiple recovery sub-stages, one needs to be selected as the master stage and the rest as slave stages. The master stage is responsible for coordinating and scheduling the recovery tasks of each slave stage and supervising the execution of the entire recovery process; the slave stage autonomously executes the assigned current recovery tasks according to the scheduling instructions of the master stage.

[0141] Select the stage with the most critical recovery task and the longest time span as the master stage to facilitate the control of the global recovery progress. According to the relevance and dependency of the tasks, assign the related recovery tasks to the same slave stage as much as possible to reduce the communication and synchronization overhead across stages. Evenly distribute the recovery tasks among the slave stages to avoid problems such as uneven load and low recovery efficiency.

[0142] A communication and synchronization mechanism needs to be established between the master and slave stages to implement functions such as the issuance of recovery tasks, progress monitoring, and exception handling. The communication mechanism can be implemented using on-chip buses, dedicated links, and the communication protocol can be designed with reference to existing on-chip communication standards (such as AMBA, CoreConnect, etc.). The synchronization mechanism mainly includes two aspects: one is the synchronization between the master and slave stages, which requires ensuring that the slave stage executes tasks according to the scheduling instructions of the master stage; the other is the synchronization between the slave stages, which requires ensuring that the associated tasks are executed according to the predetermined order and time constraints. The synchronization mechanism can be implemented using global clocks, synchronization signals, message passing, and other methods.

[0143] In each slave stage, an independent current recovery module needs to be deployed to perform the current recovery task of this stage. The current recovery module mainly consists of three parts: an adjustable current limiting unit, a current detection unit, and a recovery control unit.

[0144] Adjustable current limiting unit: The adjustable current limiting unit is responsible for hierarchical limitation and dynamic adjustment of the power supply current of the target chip. The difference is that the adjustable current limiting unit in each recovery stage is only responsible for the current recovery range corresponding to that stage. By reasonably configuring the parameters of the current limiting unit, more refined current regulation can be achieved.

[0145] Current detection unit: The current detection unit is responsible for real-time monitoring of the current status of the power supply in the current stage, and feeding back the detection data to the recovery control unit and the main stage. In addition to the traditional current sampling circuit, an intelligent current anomaly detection algorithm can also be introduced to accurately identify and locate different types of current anomalies (such as instantaneous pulses, slow drift, etc.).

[0146] Recovery control unit: The recovery control unit is the core of the current recovery module. It is responsible for receiving the recovery parameters and control instructions issued by the main stage, and dynamically adjusting the working state of the adjustable current limiting unit according to the real-time data fed back by the current detection unit to achieve the current recovery task of this stage. The design of the recovery control unit needs to comprehensively consider multiple factors such as control algorithm, hardware circuit, interface protocol, etc., and can be implemented using solutions such as FSM and PID controller.

[0147] By deploying independent and configurable current recovery modules in each slave stage, the multi-stage collaborative recovery strategy realizes parallel processing and adaptive adjustment of recovery tasks, avoiding single point failure and performance bottleneck problems in centralized recovery architecture.

[0148] The execution process of the multi-stage collaborative recovery strategy can be summarized as follows:

[0149] Start recovery: When the target chip's power supply current is detected to be abnormal, the multi-stage collaborative recovery process is started. The master stage determines the overall goal and phased tasks of this recovery process based on the type and degree of current anomaly, and generates the initial recovery parameters for each slave stage.

[0150] Task distribution: The master stage distributes the phased recovery tasks and initial parameters to each slave stage through the on-chip bus or dedicated link. After receiving the tasks and parameters, the slave stage configures the local current recovery module and establishes a communication connection with the master stage.

[0151] Parallel recovery: Each slave stage starts the current recovery task in parallel, initializes the adjustable current limit unit according to the parameters issued by the master stage, and adjusts the supply current in real time through the recovery control unit. At the same time, the current detection unit continuously monitors the current state of this stage and feeds the monitoring data back to the recovery control unit.

[0152] Adaptive regulation: The recovery control unit in the slave stage dynamically adjusts the control strategy of the adjustable current limiting unit according to the real-time data fed back by the current detection unit to achieve adaptive optimization of current recovery. When the current in this stage is restored to within the target range, the recovery control unit sends a task completion signal to the master stage.

[0153] Progress monitoring: The master stage monitors the recovery progress and current status of each slave stage in real time, and adjusts the task allocation and coordination strategy of the slave stage in a timely manner according to the achievement of the global recovery goal. When the recovery tasks of all slave stages are completed, the master stage sends a recovery completion signal to the chip power supply control module, ending the entire recovery process.

[0154] Exception handling: During the recovery process, if a slave stage detects an abnormal situation such as a severe current mutation or recovery failure, the slave stage first starts the local exception handling mechanism (such as retry, reset, etc.) to try to recover autonomously. If the local recovery fails, it sends an exception report to the master stage to request assistance. After receiving the exception report, the master stage takes corresponding global exception handling measures according to the severity of the exception, such as suspending the recovery tasks of other slave stages, adjusting the recovery parameters, or directly terminating the recovery process.

[0155] Through the above process, the multi-stage collaborative recovery strategy can flexibly adjust the recovery plan according to the actual situation of the current anomaly, and give full play to the parallel advantages of the distributed architecture, while ensuring the reliability of recovery and minimizing the impact on the normal operation of the chip.

[0156] In summary, this application proposes a multi-stage collaborative recovery strategy for chip-level power supply current anomalies. This strategy is based on the master-slave stage division. By deploying independent current recovery modules in the slave stage and establishing a communication synchronization mechanism between the master and slave stages, distributed parallel processing and global collaborative optimization of recovery tasks are achieved. Compared with centralized recovery strategies, multi-stage collaborative recovery strategies have higher fault tolerance, flexibility and scalability, and can adapt to different types and degrees of current anomaly scenarios, providing stronger guarantees for the power supply safety and reliability of the chip.

[0157] In an optional embodiment,

[0158] If the target chip is overcurrent, adaptively determining multiple protection levels corresponding to the comparison result based on the comparison result of the current detection result and the preset current threshold, and determining corresponding protection strategies based on the multiple protection levels include:

[0159] Compare the current detection result with a preset current threshold to determine whether overcurrent occurs in the target chip;

[0160] If the current detection result exceeds the preset current threshold, it is determined that the target chip has an overcurrent, and according to the proportion of the current detection result exceeding the preset current threshold, the overcurrent fault level of the target chip is adaptively determined, and the overcurrent fault is divided into multiple protection levels;

[0161] Based on the determined multiple protection levels, protection strategies corresponding to the multiple protection levels are selected from a preset multi-level protection strategy library, and the protection strategies include one or more combinations of current limiting protection, function module shutdown protection, and chip power-off protection.

[0162] For example, the core idea of ​​the adaptive multi-level protection strategy is to divide overcurrent faults into multiple levels and take corresponding protection measures for different levels of overcurrent faults. The level of overcurrent faults is mainly determined by the proportion of current detection results exceeding the preset current threshold. The specific implementation process is as follows:

[0163] Setting of current threshold: According to the current carrying capacity of the target chip and the design parameters of the power supply network, a current threshold is pre-set as the basis for overcurrent fault judgment. The selection of current threshold needs to comprehensively consider factors such as the power density, thermal design margin, and process parameters of the chip, in order to avoid misjudgment and leave enough protection margin. Determination of current detection results: The power supply current of the target chip is monitored in real time through the current detection unit, and the detection result is compared with the preset current threshold. Classification of overcurrent fault levels: When an overcurrent fault is detected, the level of the overcurrent fault is adaptively determined based on the proportion of the current detection result exceeding the preset current threshold.

[0164] After dividing multiple overcurrent fault levels, it is necessary to formulate corresponding protection strategies for different levels. The formulation of protection strategies needs to take into account the severity of the fault and the functional integrity of the chip. It is necessary to timely and effectively suppress the damage to the chip caused by overcurrent, and to minimize the impact of protection measures on the normal operation of the chip.

[0165] Common protection strategies include the following:

[0166] Current limiting protection: The chip's power supply current is dynamically adjusted through an adjustable current limiting unit to limit the current within a safe range. This protection strategy is suitable for mild overcurrent faults and guarantees the basic functions of the chip by sacrificing some performance.

[0167] Functional module shutdown protection: selectively shut down the power supply of some non-critical functional modules to reduce the overall power consumption and heat generation of the chip. This protection strategy is suitable for moderate overcurrent faults and ensures the core functions of the chip by sacrificing some functions.

[0168] Chip power-off protection: Directly cut off the power supply of the entire chip, forcing the chip to enter a power-off state. This protection strategy is suitable for severe overcurrent faults and protects the chip from permanent damage by sacrificing its immediate availability.

[0169] In addition to the common protection strategies mentioned above, other protection measures can be designed according to specific application scenarios and requirements, such as frequency reduction protection, backup power supply switching, etc.

[0170] When formulating a hierarchical protection strategy, it is necessary to pre-set a multi-level protection strategy library, which contains the protection strategies corresponding to each overcurrent fault level. The protection strategy library can be organized and stored using data structures such as lookup tables and decision trees to quickly index and match the optimal protection strategy according to the overcurrent fault level.

[0171] In summary, this application proposes an adaptive multi-level protection strategy for chip-level power supply current anomalies. This strategy is based on the classification of overcurrent fault levels, and achieves refined hierarchical processing of overcurrent faults by matching the optimal protection strategy at each fault level. Compared with traditional fixed threshold protection, the adaptive multi-level protection strategy has higher flexibility and adaptability, and can better cope with complex and changeable overcurrent fault scenarios, thereby improving the power supply safety and reliability of the chip.

[0172] In an optional embodiment,

[0173] The method further comprises:

[0174] If there are multiple target chips, each target chip is regarded as a chip node, and an independent multi-level protection module is deployed on each chip node, wherein the multi-level protection module includes one or more functional unit combinations of current detection, threshold comparison, fault level classification, and strategy selection;

[0175] Establishing a communication and synchronization mechanism between the chip nodes, realizing data exchange and state sharing between the chip nodes through on-chip interconnection or inter-chip bus, and maintaining the consistency of protection actions between the chip nodes through a global clock or synchronization protocol;

[0176] When the multi-level protection module of any chip node detects an overcurrent fault, the chip node first triggers the node-level protection measures, and encapsulates the fault information into a fault message in a standard format, and broadcasts it to other chip nodes through the communication mechanism;

[0177] After receiving the fault message, other chip nodes extract the fault information in the fault message and trigger the corresponding linkage protection process according to the coordination strategy. The linkage protection process automatically selects the protection action of cutting off the power supply of the fault node and disconnecting the connection with the fault node based on the fault node location, current size, and duration in the fault information and the preset linkage rules;

[0178] After the faulty node completes the overcurrent protection, it enters the recovery phase and regularly synchronizes the recovery progress to other chip nodes. Other chip nodes release the corresponding linkage protection process based on the recovery progress information to achieve coordinated recovery of multiple target chips.

[0179] For example, in modern high-performance computing systems, a multi-chip collaborative architecture is increasingly being used to improve the processing power and parallelism of the system. However, a power supply anomaly in any chip in a multi-chip system may affect the stability and reliability of the entire system. In order to meet this challenge, this application further proposes a collaborative protection mechanism for a multi-chip system based on an adaptive multi-level protection strategy.

[0180] In the multi-chip collaborative protection mechanism, first of all, it is necessary to deploy an independent multi-level protection module on each chip node. Each multi-level protection module contains functional units such as current detection, threshold comparison, fault level classification, and strategy selection, which are responsible for monitoring and processing the power supply current anomaly of this node. The specific implementation steps are as follows:

[0181] Division of chip nodes: According to the physical topology of the multi-chip system, each chip is divided into an independent node and assigned a unique node identifier. Deployment of multi-level protection modules: A multi-level protection module is integrated on each chip node, which contains functional units such as current detection, threshold comparison, fault level classification, and strategy selection. The multi-level protection modules of different chip nodes can be customized according to their respective current characteristics and protection requirements.

[0182] In order to facilitate communication and data exchange between multi-level protection modules of different chip nodes, it is necessary to define standardized module interface specifications, including fault message format, control command format, status query format, etc. By deploying standardized multi-level protection modules on each chip node, the distributed deployment of overcurrent protection functions in multi-chip systems is achieved, laying the foundation for collaborative protection between chip nodes.

[0183] In order to achieve coordinated protection of multiple chip nodes, it is necessary to establish a communication and synchronization mechanism between chip nodes. The communication mechanism is responsible for exchanging fault information and control commands between chip nodes, and the synchronization mechanism is responsible for maintaining the consistency of different chip nodes when executing protection actions. Communication between chip nodes can be achieved in the following two ways:

[0184] On-Chip Interconnect: For multiple chip nodes integrated in the same chip, on-chip interconnect resources (such as NoC, bus, etc.) can be used to achieve communication between nodes. On-chip interconnects usually have higher bandwidth and lower latency, and are suitable for transmitting smaller fault messages and control commands.

[0185] Inter-Chip Bus: For chip nodes distributed on multiple chips, communication needs to be achieved through an inter-chip bus. Common inter-chip buses include USB, PCI, I²C, etc. Compared with on-chip interconnects, the communication bandwidth of the inter-chip bus is lower and the latency is higher. It is suitable for transmitting large amounts of status information and recovery progress.

[0186] On the basis of the communication mechanism, a synchronization mechanism needs to be established to maintain the consistency of the protection actions of different chip nodes. The synchronization mechanism can be implemented in the following two ways:

[0187] Global clock synchronization: By providing a global synchronization clock to all chip nodes, the protection actions of different nodes are kept consistent in time. The advantages of global clock synchronization are high accuracy and strong real-time performance, but the disadvantages are high requirements for the clock distribution network and easy to be affected by signal integrity issues.

[0188] Synchronization protocol: Maintain the consistency of protection actions by exchanging synchronization messages between chip nodes. Common synchronization protocols include Paxos and Raft. The synchronization mechanism based on the synchronization protocol has good fault tolerance and scalability, but the synchronization process requires a certain amount of time and the real-time performance is relatively poor.

[0189] By establishing a communication and synchronization mechanism, multiple chip nodes can exchange fault information and status data in a timely manner and coordinate their respective protection actions, thereby achieving coordinated protection of the entire system.

[0190] When the multi-level protection module of any chip node detects an overcurrent fault, the multi-chip system will start the coordinated protection process. The execution process of coordinated protection can be divided into three stages: fault handling, linkage protection and coordinated recovery.

[0191] Troubleshooting phase:

[0192] When a chip node (called a fault node) detects an overcurrent fault, its multi-level protection module first triggers node-level protection measures (such as current limiting, shutdown function modules, etc.) to control the impact of the fault on this node. At the same time, the multi-level protection module of the fault node encapsulates the fault information (such as fault type, current size, duration, etc.) into a fault message in a standard format and broadcasts it to other chip nodes through the communication mechanism.

[0193] After receiving the fault message broadcast by the faulty node, other chip nodes extract the fault information and decide whether to trigger the linkage protection according to the preset linkage rules. The purpose of linkage protection is to prevent the abnormal state of the faulty node from affecting other nodes through shared power supply networks, signal lines, etc. Common linkage protection actions include: cutting off the power supply network connected to the faulty node to prevent overcurrent diffusion; closing the I / O interface connected to the faulty node to avoid the propagation of erroneous data; suspending tasks or processes related to the faulty node to reduce the scope of the fault. The triggering conditions and specific actions of the linkage protection can be adaptively selected based on the fault type, faulty node location, current size, duration and other parameters in the fault information, combined with the preset linkage rules.

[0194] After the faulty node completes the node-level overcurrent protection, its multi-level protection module enters the recovery phase and attempts to restore the affected functional modules through reset, reconstruction, and other means. During the recovery process, the faulty node periodically synchronizes the recovery progress to other chip nodes and reports the recovery completion event. Other chip nodes evaluate whether the impact of the faulty node on the system has been eliminated based on the recovery progress information, and decide whether to release the corresponding linkage protection measures. When all chip nodes have completed their respective recovery processes, the entire multi-chip system achieves coordinated recovery from the overcurrent fault and re-enters normal working state.

[0195] In summary, the present application proposes a collaborative protection mechanism for a multi-chip system, which realizes distributed overcurrent fault detection and processing by deploying multi-level protection modules on each chip node and establishing a communication and synchronization mechanism between chip nodes. When an overcurrent fault occurs at any node, the faulty node first takes node-level protection measures and broadcasts the fault information to other nodes; other nodes evaluate the scope of impact based on the fault information and start the corresponding linkage protection process; after the faulty node completes recovery, other nodes release the linkage protection based on the recovery progress, and finally realize the coordinated recovery of the entire system. Compared with traditional centralized protection schemes, the multi-chip collaborative protection mechanism has higher scalability, flexibility and fault tolerance, and can effectively deal with various power supply abnormalities in multi-chip systems, and improve the overall reliability and robustness of the system.

[0196] Figure 2 FIG. 1 is a schematic diagram of a current detection and circuit protection system for a chip according to an embodiment of the present invention. Figure 2 As shown, the system comprises:

[0197] The first unit is used to set a clock source in the target chip, generate a high-frequency clock signal through the clock source, divide and shape the high-frequency clock signal in combination with a frequency divider and a comparator to obtain a chopping signal; use an analog switch to chop and modulate the current signal to be measured of the target chip; use a multi-stage current mirror structure and a fuzzy control algorithm to determine the gain control amount of the current signal to be measured, thereby realizing dynamic detection of the current signal to be measured and obtaining a current detection result;

[0198] The second unit is used to compare the current detection result with a preset current threshold to determine whether the target chip is overcurrent, and if the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result according to the comparison result between the current detection result and the preset current threshold, and determine a corresponding protection strategy based on the multiple protection levels;

[0199] The third unit is used to gradually restore the power supply current of the target chip in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip according to the protection strategy, and judge whether the current detection result exceeds the preset current threshold at the end of each recovery stage. If exceeded, return to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within a preset recovery time, wherein the recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes.

[0200] According to a third aspect of the embodiments of the present invention,

[0201] An electronic device is provided, comprising:

[0202] processor;

[0203] a memory for storing processor-executable instructions;

[0204] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0205] A fourth aspect of the embodiments of the present invention is:

[0206] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0207] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0208] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current detection and circuit protection method for a chip, characterized in that: include: A clock source is set in the target chip, a high-frequency clock signal is generated by the clock source, and the high-frequency clock signal is divided and shaped by combining a frequency divider and a comparator to obtain a chopping signal; an analog switch is used to chop and modulate the current signal to be measured of the target chip; A multi-stage current mirror structure is adopted, and the gain control amount of the current signal to be measured is determined through a fuzzy control algorithm, so as to realize dynamic detection of the current signal to be measured and obtain the current detection result; Compare the current detection result with a preset current threshold to determine whether the target chip is overcurrent; if the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result according to the comparison result between the current detection result and the preset current threshold, and determine corresponding protection strategies based on the multiple protection levels; According to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip. At the end of each recovery stage, it is judged whether the current detection result exceeds the preset current threshold. If it exceeds, it returns to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within the preset recovery time, wherein the recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes; Based on the pre-built fuzzy rule base, the fuzzy control algorithm is adopted, and the gain of the multi-stage current mirror is adaptively adjusted according to the amplitude of the amplified current signal to be measured, and the amplitude of the amplified current signal to be measured is divided into several fuzzy subsets, and a corresponding gain control strategy is set for each fuzzy subset. The gain control amount of the current signal to be measured is determined by using fuzzy reasoning and defuzzification methods, and dynamic detection of the current signal to be measured is realized, and the current detection results obtained include: According to the amplitude range of the current signal to be measured, the amplitude of the current signal to be measured is divided into multiple fuzzy subsets, and a triangular membership function is used to represent each fuzzy subset; For each fuzzy subset, a corresponding multi-stage current mirror gain control strategy is set; Constructing a fuzzy rule base, wherein the fuzzy rule base is composed of a plurality of fuzzy control rules, and each of the fuzzy control rules uses an If-Then statement to represent the relationship between the fuzzy subset and the gain control strategy; Acquire the actual amplitude of the current signal to be measured, and perform fuzzy reasoning on the fuzzy rule base according to the actual amplitude using the Mamdani reasoning method to obtain the fuzzy gain control amount of the multi-stage current mirror, wherein the Mamdani reasoning method includes membership calculation, rule matching and rule synthesis; The membership calculation is to calculate the membership of each fuzzy subset according to the actual amplitude of the current signal to be measured; The rule matching is to match the membership degree with each fuzzy control rule in the fuzzy rule base and calculate the activation degree of each fuzzy control rule; The rule synthesis adopts the maximum-minimum synthesis rule to synthesize the activation degree of each fuzzy control rule and its corresponding gain control strategy to obtain the final fuzzy reasoning result; Defuzzification is performed on the fuzzy gain control quantity by using the centroid method to obtain a multi-stage current mirror gain control quantity; According to the gain control amount of the multi-stage current mirror, the gain of the multi-stage current mirror is adaptively adjusted to amplify the current signal to be measured, thereby realizing dynamic detection of the current signal to be measured and obtaining a final current detection result.

2. The method according to claim 1, characterized in that: A clock source is set in the target chip, a high-frequency clock signal is generated by the clock source, and the high-frequency clock signal is divided and shaped by combining a frequency divider and a comparator to obtain a chopping signal; an analog switch is used to chop and modulate the current signal to be measured of the target chip; A multi-stage current mirror structure is used, and the gain control amount of the current signal to be measured is determined through a fuzzy control algorithm to achieve dynamic detection of the current signal to be measured. The current detection results include: A clock source is used to generate a high-frequency clock signal, and a frequency divider is used to divide the high-frequency clock signal, and a comparator is used to shape the divided high-frequency clock signal to obtain a square wave signal as a chopping signal; an analog switch is used to perform chopping modulation on the current signal to be measured, and the chopping signal is used to control the conduction and shutdown of the analog switch to achieve modulation of the current signal to be measured, and a holding capacitor is connected in parallel to the output end of the analog switch to hold the modulated current signal to be measured; A multi-stage current mirror structure is adopted, an adjustable resistor or an adjustable current source is added to the bias circuit of each stage of the current mirror, and the modulated current signal to be measured is amplified to obtain an amplified current signal to be measured; Based on a pre-constructed fuzzy rule base, a fuzzy control algorithm is adopted, and the gain of the multi-stage current mirror is adaptively adjusted according to the amplitude of the amplified current signal to be measured, and the amplitude of the amplified current signal to be measured is divided into several fuzzy subsets, and a corresponding gain control strategy is set for each fuzzy subset. The gain control amount of the current signal to be measured is determined by using fuzzy reasoning and defuzzification methods, so as to realize dynamic detection of the current signal to be measured and obtain the current detection result.

3. The method according to claim 1, characterized in that According to the protection strategy, the power supply current of the target chip is gradually restored in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip, and at the end of each recovery stage, it is judged whether the current detection result exceeds the preset current threshold value, and if it exceeds, it returns to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within the preset recovery time. The method includes: According to the current abnormality threshold, normal working current and preset recovery time of the target chip, the number of stages of staged recovery, the current increase and duration of each stage are determined; An adjustable current limiting module is set in the power supply circuit of the target chip, wherein the adjustable current limiting module is composed of a plurality of current limiting units connected in parallel, each current limiting unit controls whether to be connected to the circuit through a switch tube, and a hierarchical limitation of the power supply current is achieved by controlling the conduction state of the switch tube; When the power supply current of the target chip is detected to be abnormal, a phased recovery process is started: Entering the first recovery stage, by controlling the adjustable current limiting module, the power supply current is gradually increased from the initial state to the current increase of the first stage, and the duration of the first stage is continued, and the change of the power supply current is monitored in real time; At the end of the first recovery phase, determine whether the power supply current exceeds the current abnormality threshold. If so, return to the initial state, reduce the recovery amplitude, and restart the recovery. If not, enter the next recovery phase. Repeat the steps of entering the recovery phase, gradually increasing the current gain, and determining whether the power supply current exceeds the abnormal current threshold until all recovery phases are completed, and restore the power supply current to the normal operating current. During the entire recovery process, dynamically adjust the recovery speed and amplitude based on the current changes monitored in real time.

4. The method according to claim 3, characterized in that The method further comprises: According to the current anomaly characteristics and recovery requirements of the target chip, the entire recovery process is divided into multiple sub-stages, each of which is responsible for the current recovery task within the corresponding recovery target range; Select one of the multiple sub-phases as the main phase and the rest as slave phases. The main phase is responsible for coordinating and scheduling the recovery tasks of each slave phase and supervising the execution of the entire recovery process. An independent current recovery module is deployed in each slave stage, including an adjustable current limiting unit, a current detection unit and a recovery control unit. Each recovery module autonomously performs current recovery operations according to the recovery tasks and requirements of the sub-stage to which it belongs; Establish a communication and synchronization mechanism between the master and slave stages. The master stage is connected to each slave stage through a communication bus or a dedicated link to implement recovery task issuance, progress monitoring and exception handling functions. Start the multi-stage collaborative recovery process. The master stage assigns recovery tasks to each slave stage and issues recovery parameters and control instructions. After receiving the recovery parameters and control instructions, the slave stage immediately starts the local recovery operation. During the recovery process, the slave stage dynamically adjusts the local recovery strategy based on the real-time monitored current status and recovery progress, and feeds back the recovery progress, current status and other information to the master stage in real time; When a slave stage experiences a sudden current change or a recovery failure, the slave stage first starts the local exception handling mechanism to try to recover autonomously. If the recovery fails, it sends an exception report to the master stage to request assistance. After receiving the exception report from the slave stage, the master stage starts the exception handling process and takes measures such as reallocating tasks and suspending recovery of some slave stages according to the severity of the exception.

5. The method according to claim 1, characterized in that If the target chip is overcurrent, adaptively determining multiple protection levels corresponding to the comparison result based on the comparison result of the current detection result and the preset current threshold, and determining corresponding protection strategies based on the multiple protection levels include: Compare the current detection result with a preset current threshold to determine whether overcurrent occurs in the target chip; If the current detection result exceeds the preset current threshold, it is determined that the target chip has an overcurrent, and according to the proportion of the current detection result exceeding the preset current threshold, the overcurrent fault level of the target chip is adaptively determined, and the overcurrent fault is divided into multiple protection levels; Based on the determined multiple protection levels, protection strategies corresponding to the multiple protection levels are selected from a preset multi-level protection strategy library, and the protection strategies include one or more combinations of current limiting protection, function module shutdown protection, and chip power-off protection.

6. The method according to claim 5, characterized in that The method further comprises: If there are multiple target chips, each target chip is regarded as a chip node, and an independent multi-level protection module is deployed on each chip node, wherein the multi-level protection module includes one or more functional unit combinations of current detection, threshold comparison, fault level classification, and strategy selection; Establishing a communication and synchronization mechanism between the chip nodes, realizing data exchange and state sharing between the chip nodes through on-chip interconnection or inter-chip bus, and maintaining the consistency of protection actions between the chip nodes through a global clock or synchronization protocol; When the multi-level protection module of any chip node detects an overcurrent fault, the chip node first triggers the node-level protection measures, and encapsulates the fault information into a fault message in a standard format, and broadcasts it to other chip nodes through the communication mechanism; After receiving the fault message, other chip nodes extract the fault information in the fault message and trigger the corresponding linkage protection process according to the coordination strategy. The linkage protection process automatically selects the protection action of cutting off the power supply of the fault node and disconnecting the connection with the fault node based on the fault node location, current size, and duration in the fault information and the preset linkage rules; After the faulty node completes the overcurrent protection, it enters the recovery phase and regularly synchronizes the recovery progress to other chip nodes. Other chip nodes release the corresponding linkage protection process based on the recovery progress information to achieve coordinated recovery of multiple target chips.

7. A current detection and circuit protection system for a chip, used to implement the method according to any one of claims 1 to 6, characterized in that: include: The first unit is used to set a clock source in the target chip, generate a high-frequency clock signal through the clock source, divide and shape the high-frequency clock signal in combination with a frequency divider and a comparator to obtain a chopping signal; and use an analog switch to chop and modulate the current signal to be measured of the target chip; A multi-stage current mirror structure is adopted, and the gain control amount of the current signal to be measured is determined through a fuzzy control algorithm, so as to realize dynamic detection of the current signal to be measured and obtain the current detection result; The second unit is used to compare the current detection result with a preset current threshold to determine whether the target chip is overcurrent, and if the target chip is overcurrent, adaptively determine multiple protection levels corresponding to the comparison result according to the comparison result between the current detection result and the preset current threshold, and determine a corresponding protection strategy based on the multiple protection levels; The third unit is used to gradually restore the power supply current of the target chip in stages by controlling the adjustable current limiting module in the power supply circuit of the target chip according to the protection strategy, and judge whether the current detection result exceeds the preset current threshold at the end of each recovery stage. If exceeded, return to the previous recovery stage to continue recovery until the power supply current of the target chip is restored to a normal working state within a preset recovery time, wherein the recovery stage includes fast recovery, medium recovery and slow recovery, and different recovery stages correspond to different current recovery slopes.

8. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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