LDO (Low Dropout Regulator) circuit and method for improving transient response speed of load

Abstract

The invention discloses an LDO circuit and method for improving the transient response speed of a load, the LDO circuit comprises an amplifier, an internal circuit, an input end and an output end, an input voltage # imgabs0 #, a first reference voltage # imgabs1 #, a second reference voltage # imgabs2 # and an output voltage # imgabs3 # are set, the amplifier and the internal circuit are connected to the input end and the output end, the input voltage is connected to the input end, and the output voltage is connected to the output end. The output end of the amplifier is connected with an external load, the first speed increasing module is connected between the amplifiers, and the second speed increasing module is connected between the amplifiers and the internal circuit; when the external load is switched, the amplifier and the first speed increasing module jointly output signals to the internal circuit to control the output voltage so as to deal with voltage undershoot, or the amplifier, the first speed increasing module and the second speed increasing module jointly output signals to the internal circuit to control the output voltage so as to deal with voltage overcharge.

Description

Technical Field

[0001] The present invention relates to the technical field of power management chips, and in particular to an LDO circuit and method for improving load transient response speed. Background Art

[0002] See also Figure 2 , Figure 2 The figure shows a method in the prior art to effectively improve the transient response speed. Figure 2 As shown, by sampling the output load current and feeding back the tail current of the first-stage amplifier, the gate of the second-stage amplifier tube is controlled to improve the transient response speed and the stability of the chip output. It includes: an operational amplifier and an output voltage divider circuit composed of an NMOS tube, a PMOS tube and a resistor, and by sampling the output load current and feeding back the tail current of the first-stage amplifier, the gate of the second-stage amplifier tube is controlled to improve the transient response speed. The source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the power supply voltage VDD, the third NMOS tube MN3, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are connected to the ground terminal GND, the third resistor R3 and the fourth resistor R4 provide a feedback voltage Vfb which is input to the gate of the first NMOS tube MN1, the third NMOS tube MN3 is connected to the reference voltage Vbias, and the voltage output terminal VOUT is formed between the drain of the fifth PMOS tube MP5 and the second resistor R2, wherein at least the first part is formed by the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the first PMOS tube MP1 and the second PMOS tube MP2, which is an operational amplifier circuit; and the third part is formed by the fifth PMOS tube MP5, the third resistor R3 and the fourth resistor R4, which constitutes a second-stage amplification and output voltage divider circuit.

[0003] On the basis of the above scheme, in the first part of the circuit PART1, the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2, and the third NMOS tube MN3 constitute an operational amplifier as the first-stage amplifier of the low-dropout linear regulator loop. Vbg and Vbias are standard voltage sources. The feedback voltages Vfb and Vbg are made equal through the amplifier, and the output voltage with very small error is obtained through the voltage division of the third resistor R3 and the fourth resistor R4 in the third part PART3.

[0004] Generally speaking, when the static power consumption requirement is not high, the first part PART1 and the third part PART3 plus some compensation are sufficient to output a stable output voltage. However, when the static current requirement is relatively high, when the tail current of the first-stage amplifier is relatively small, the gain is small, and the output is output to the gate of the fifth PMOS tube MP5 of the power tube. If there is no large capacitor at the output, the output voltage will jump significantly.

[0005] On the basis of the above scheme, the second part is composed of the fourth NMOS tube MN4, the fifth NMOS tube MN5, the third PMOS tube MP3, the fourth PMOS tube MP4, the first resistor R1, and the second resistor R2, which serves as an output load current sampling circuit, wherein the third PMOS tube MP3 is a sampling tube, the first resistor R1 and the fourth PMOS tube MP4 play a role of auxiliary sampling, the second resistor R2 plays a role of protecting the gate of the fourth PMOS tube MP4 to prevent it from being broken down due to being connected to the PAD, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are current mirrors, responsible for feeding back the sampled current to the operational amplifier, and when the output light load / heavy load suddenly changes, the sampling tube third PMOS tube MP3 samples the output current and feeds it back to the first-stage amplifier through the current mirror fourth NMOS tube MN4 and the fifth NMOS tube MN5.

[0006] Aiming at the shortcomings of traditional low voltage drop linear regulator, such as unstable output when light load and heavy load are switched quickly, and serious output overcharge and undershoot jump, a method for improving transient response speed is proposed. In the circuit, the output load current is sampled and fed back to the tail current of the first-stage amplifier to control the gate of the fifth PMOS tube MP5 of the second-stage amplifier tube, thereby improving the transient response speed and effectively improving the stability of the chip output.

[0007] Pros and cons of previous technologies: 1: The previous technology can indeed improve some of the response speed, but when the heavy load is switched to the light load, the sampling current is extremely small, and the improvement on the output overshoot is limited.

[0008] 2: The operational amplifier is used to improve the sudden change of VOUT only, and the amplifier has only two stages, so the gain is limited and the improvement capability is also limited. Summary of the invention

[0009] In view of the above-mentioned deficiencies in the current power management chip technology field, the present invention provides an LDO circuit and method for improving the load transient response speed, including an amplifier, an internal circuit, an input terminal and an output terminal, and an input voltage , the first reference voltage , the second reference voltage and output voltage The amplifier and the internal circuit are connected to the input end and the output end, the input end is connected to the input voltage, and the output end is connected to the external load. It is characterized in that it also includes a first speed-increasing module connected between the amplifiers and a second speed-increasing module connected between the amplifier and the internal circuit; when the external load is switched, the amplifier and the first speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed-increasing module and the second speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0010] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: An LDO circuit for improving load transient response speed includes an amplifier, an internal circuit, an input terminal and an output terminal, and is provided with an input voltage , the first reference voltage , the second reference voltage and output voltage The amplifier and the internal circuit are connected to the input end and the output end, the input end is connected to the input voltage, and the output end is connected to the external load; it also includes a first speed-increasing module connected between the amplifiers and a second speed-increasing module connected between the amplifier and the internal circuit; when the external load is switched, the amplifier and the first speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed-increasing module and the second speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

[0011] According to one aspect of the present invention, the amplifier is divided into a first-stage amplifier, a second-stage amplifier and a third-stage amplifier, the internal circuit includes a first voltage-dividing sampling resistor, a second voltage-dividing sampling resistor and a second voltage-controlled current source, the first speed-increasing module is connected between the first-stage amplifier and the second-stage amplifier, and the second speed-increasing module is connected to the output end of the second-stage amplifier.

[0012] According to one aspect of the present invention, the first stage amplifier is a five-tube amplifier, which is composed of an input voltage power supply, including a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a current source; the gate of the first NMOS tube is connected to a first reference voltage , the source is connected to the current source and the source of the second NMOS tube, and the drain is connected to the drain of the first PMOS tube; the other end of the current source is grounded; the gate of the second NMOS tube is connected to the feedback voltage , the drain is connected to the drain of the second PMOS tube and outputs a first voltage signal; the gate and drain of the first PMOS tube are interconnected, the gate is connected to the gate of the second PMOS tube, and the source is connected to the input voltage ; The source of the second PMOS tube is connected to the input voltage The five-tube amplifier is based on a first reference voltage The first voltage signal is outputted by the feedback voltage to the first speed increasing module and the second stage amplifier.

[0013] According to one aspect of the present invention, the second stage amplifier includes a third PMOS tube and a first voltage-controlled current source, wherein the gate of the third PMOS tube is connected to the first voltage signal, and the source is connected to the input voltage The drain is connected to the positive end of the output of the first voltage-controlled current source and the third-stage amplifier and the second speed-increasing module, and the negative end of the output of the first voltage-controlled current source is grounded; the third-stage amplifier includes a fourth PMOS tube, the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the source is connected to the input voltage , the drain is connected to the first voltage divider sampling resistor and the output voltage .

[0014] According to one aspect of the present invention, the loop formed by the amplifier, the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor forms a negative feedback loop, the other end of the first voltage-dividing sampling resistor is connected to one end of the second voltage-dividing sampling resistor and outputs a feedback voltage signal; the other end of the second voltage-dividing sampling resistor is grounded; the negative feedback loop makes the first reference voltage consistent with the feedback voltage, and then sets the output voltage through the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor, and the output voltage is: .

[0015] According to one aspect of the present invention, the first speed increasing module is provided with an input voltage power supply, based on the first voltage signal, output a second voltage signal to the first voltage-controlled current source and control its current; the second-stage amplifier is powered by the input voltage Power supply, based on the first voltage signal and the second voltage signal, output driving voltage to the third stage amplifier and the second speed increasing module.

[0016] According to one aspect of the present invention, the third stage amplifier is provided with an input voltage power supply, based on the drive voltage, controls the output voltage The second speed increasing module outputs a third voltage signal to the second voltage controlled current source based on the driving voltage and the second reference voltage, and controls the second voltage controlled current source to output the voltage of discharge.

[0017] A method for improving load transient response speed is implemented based on the above-mentioned LDO circuit, and the method includes the following steps: when the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

[0018] According to one aspect of the present invention, when the first voltage signal increases, the current of the first voltage-controlled current source decreases based on the second voltage signal, and the first speed increasing module accelerates the speed at which the driving voltage rises; when the first voltage signal weakens, the current of the first voltage-controlled current source increases based on the second voltage signal, and the first speed increasing module accelerates the speed at which the driving voltage decreases.

[0019] According to one aspect of the present invention, the output voltage When overcharged, the feedback voltage rises and the first voltage signal drops, the current of the first voltage-controlled current source decreases based on the second voltage signal, the first speed-increasing module accelerates the speed of the driving voltage rise, and quickly adjusts the power tube, and the second speed-increasing module generates a third voltage signal after detecting that the driving voltage is higher than the second reference voltage, and controls the second voltage-controlled current source to increase the output voltage. Discharge, so that the output voltage Reduce; the output voltage During the undershoot, the first voltage signal changes and causes the current of the first voltage-controlled current source to change based on the second voltage signal, and enhances the ability of the third PMOS tube to control the change of the driving voltage, so that the output voltage Increase.

[0020] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1A circuit structure diagram of an LDO circuit for improving load transient response speed according to the present invention; Figure 2 A circuit structure diagram of the prior art of an LDO circuit for improving load transient response speed according to the present invention; Figure 3 This is a load transient simulation effect diagram of an LDO circuit for improving load transient response speed according to the present invention; Figure 4 This is a MOS load simulation effect diagram of an LDO circuit for improving load transient response speed according to the present invention; Figure 5 This is a simulation effect diagram of an LDO circuit for improving load transient response speed according to the present invention without adding the first speed increasing module and the second speed increasing module; Figure 6 This is a simulation effect diagram of a MOS load-pulling LDO circuit for improving load transient response speed according to the present invention without adding a second speed-increasing module; Figure 7 A diagram of a third embodiment of an LDO circuit for improving load transient response speed according to the present invention; Figure 8 This is a diagram of a fourth embodiment of an LDO circuit for improving load transient response speed according to the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Embodiment 1: like Figure 1 As shown, an LDO circuit for improving load transient response speed includes an amplifier, an internal circuit, an input terminal and an output terminal, and is provided with an input voltage , the first reference voltage , the second reference voltage and output voltage , the amplifier and the internal circuit are connected to the input end and the output end, the input end is connected to the input voltage, and the output end is connected to the external load. It also includes a first speed-increasing module connected between the amplifiers and a second speed-increasing module connected between the amplifier and the internal circuit; when the external load is switched, the amplifier and the first speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed-increasing module and the second speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

[0025] The amplifier is divided into a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. The internal circuit includes a first voltage-dividing sampling resistor, a second voltage-dividing sampling resistor and a second voltage-controlled current source. The first speed-increasing module is connected between the first-stage amplifier and the second-stage amplifier, and the second speed-increasing module is connected to the output end of the second-stage amplifier. The first-stage amplifier is a five-tube amplifier. The five-tube amplifier is composed of an input voltage power supply, including a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a current source; the gate of the first NMOS tube is connected to a first reference voltage , the source is connected to the current source and the source of the second NMOS tube, and the drain is connected to the drain of the first PMOS tube; the other end of the current source is grounded; the gate of the second NMOS tube is connected to the feedback voltage , the drain is connected to the drain of the second PMOS tube and outputs a first voltage signal; the gate and drain of the first PMOS tube are interconnected, the gate is connected to the gate of the second PMOS tube, and the source is connected to the input voltage ; The source of the second PMOS tube is connected to the input voltage The five-tube amplifier is based on a first reference voltage The first voltage signal is output to the first speed increasing module and the second stage amplifier by the feedback voltage. The second stage amplifier includes a third PMOS tube and a first voltage controlled current source. The gate of the third PMOS tube is connected to the first voltage signal, and the source is connected to the input voltage The drain is connected to the positive end of the output of the first voltage-controlled current source and the third-stage amplifier and the second speed-increasing module, and the negative end of the output of the first voltage-controlled current source is grounded; the third-stage amplifier includes a fourth PMOS tube, the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the source is connected to the input voltage , the drain is connected to the first voltage divider sampling resistor and the output voltage The loop formed by the amplifier, the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor forms a negative feedback loop, the other end of the first voltage-dividing sampling resistor is connected to one end of the second voltage-dividing sampling resistor and outputs a feedback voltage signal; the other end of the second voltage-dividing sampling resistor is grounded; the negative feedback loop makes the first reference voltage consistent with the feedback voltage, and then sets the output voltage through the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor, and the output voltage is: The first speed increasing module is composed of an input voltage power supply, based on the first voltage signal, output a second voltage signal to the first voltage-controlled current source and control its current; the second-stage amplifier is powered by the input voltage The third stage amplifier is powered by an input voltage and outputs a driving voltage to a second speed increasing module based on the first voltage signal and the second voltage signal. power supply, based on the drive voltage, controls the output voltage The second speed increasing module outputs a third voltage signal to the second voltage controlled current source based on the driving voltage and the second reference voltage, and controls the second voltage controlled current source to output the voltage of discharge.

[0026] In this embodiment, the specific structures of the first speed increasing module and the second speed increasing module can be replaced with the structures of the third embodiment or the fourth embodiment, so that the new embodiment can obtain the same functions and effects.

[0027] When the first voltage signal increases, the current of the first voltage-controlled current source decreases based on the second voltage signal, and the first speed-increasing module accelerates the speed at which the driving voltage rises; when the first voltage signal decreases, the current of the first voltage-controlled current source increases based on the second voltage signal, and the first speed-increasing module accelerates the speed at which the driving voltage drops. When overcharged, the feedback voltage rises and the first voltage signal drops, the current of the first voltage-controlled current source decreases based on the second voltage signal, the first speed-increasing module accelerates the speed of the driving voltage rise, and quickly adjusts the power tube, and the second speed-increasing module generates a third voltage signal after detecting that the driving voltage is higher than the second reference voltage, and controls the second voltage-controlled current source to increase the output voltage. Discharge, so that the output voltage Reduce; the output voltage During the undershoot, the first voltage signal changes and causes the current of the first voltage-controlled current source to change based on the second voltage signal, and enhances the ability of the third PMOS tube to control the change of the driving voltage, so that the output voltage Increase.

[0028] like Figure 3 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.768V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is only 44.12mV.

[0029] like Figure 4 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.884mA, and the first overcharge duration is 92.74uS. The difference between overcharge and undershoot is 273.9mV.

[0030] like Figure 5 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.537V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is 275mV.

[0031] like Figure 6 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.885mA, the first overcharge duration is 37.08mS, and the overcharge duration is very long.

[0032] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0033] Embodiment 2: like Figure 1 As shown, an LDO circuit for improving load transient response speed, the circuit includes: a five-tube amplifier, a second-stage amplifier, a third-stage amplifier, a first voltage-dividing sampling resistor , the second voltage-dividing sampling resistor and a second voltage controlled current source , and the input voltage , the first reference voltage , the second reference voltage , ground signal GND and output voltage , the five-tube amplifier, the second-stage amplifier and the third-stage amplifier are connected in sequence, and The third stage amplifier is connected and generates a feedback voltage The first speed increasing module is connected between the five-tube amplifier and the second-stage amplifier, and the second speed increasing module is connected to the output end of the second-stage amplifier. The five-tube amplifier outputs a driving voltage through the first speed increasing module and the second-stage amplifier. , the driving voltage The output voltage is then controlled by the third stage amplifier The second speed increasing module controls the output voltage through the second voltage controlled current source. The five-tube amplifier is powered by an input voltage Power supply, including the first PMOS tube , the second PMOS tube , the first NMOS tube , the second NMOS tube and current source ; The gate of the , source access and The source and drain are connected The drain of The other end is grounded; The gate is connected to the feedback voltage, and the drain is connected to The drain of the device outputs a first voltage signal ; The gate-drain interconnection, the gate access The gate and source are connected to the input voltage ; The source input voltage The five-tube amplifier is based on a first reference voltage and feedback voltage Output to the first speed increasing module and the second stage amplifier. The second stage amplifier includes a third PMOS tube and a first voltage controlled current source , Gate access , source connected to input voltage , drain access The positive end of the output is connected to the third stage amplifier and the second speed increasing module. The negative end of the output terminal is grounded; the third stage amplifier includes a fourth PMOS tube , The gate is connected to the The drain and source are connected to the input voltage , drain connected With output voltage The amplifier, and The loop formed constitutes a negative feedback loop. The other end of the connection One end of the feedback voltage signal , The other end of the negative feedback loop makes the first reference voltage Consistent with feedback voltage , and then through and Setting the Output Voltage , the output voltage for: The first speed increasing module is composed of input voltage Power supply, based on , output to The second stage amplifier is controlled by the input voltage Power supply, based on and , output drive voltage to the third-stage amplifier and the second speed-up module; the third-stage amplifier is input by the voltage power supply, based on the drive voltage , control the output voltage The second speed increasing module is based on the driving voltage and the second reference voltage , output the third voltage signal To the second voltage controlled current source , and control For output voltage of discharge.

[0034] When the output voltage is When the external load on the inverter switches between light load and heavy load, the output voltage Overcharge and undershoot will occur, and the three-stage op amp will be used to adjust the output voltage. The power tube is adjusted to adjust the changes state, thereby controlling the output voltage The first speed-up module is based on , output voltage ,control The current, thus speeding up The speed of change can improve overcharge and undershoot. When enhanced, The current is based on If it decreases, it will speed up The speed of rise; When weakened, The current is based on And increase, speed up The speed of the drop is faster than that of the output voltage. The second speed-up module is based on and , output voltage ,control The output voltage is then controlled When When the overcharge occurs when the heavy load switches to the light load, the negative feedback causes the driving voltage signal becomes high, when the second speed increasing module detects Higher than When the second speed increasing module is based on Respond to produce , and control right To discharge, Reduce and improve overcharge changes. When the load switches from light load to heavy load, The operational amplifier and the first speed-up module jointly Pull it up and stabilize it during the adjustment process; when the load switches from heavy load to light load, Overcharge is regulated by the op amp, the first speed-up module and the second speed-up module. to a stable voltage.

[0035] like Figure 3 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.768V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is only 44.12mV.

[0036] like Figure 4 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.884mA, and the first overcharge duration is 92.74uS. The difference between overcharge and undershoot is 273.9mV.

[0037] like Figure 5 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.537V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is 275mV.

[0038] like Figure 6 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.885mA, the first overcharge duration is 37.08mS, and the overcharge duration is very long.

[0039] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0040] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0041] Embodiment three: like Figure 7 As shown, an LDO circuit for improving load transient response speed, the circuit includes: a five-tube amplifier, a second-stage amplifier, a third-stage amplifier, a first voltage-dividing sampling resistor , the second voltage-dividing sampling resistor and a second voltage controlled current source , and the input voltage , the first reference voltage , the second reference voltage , ground signal GND and output voltage , the five-tube amplifier, the second-stage amplifier and the third-stage amplifier are connected in sequence, and The third stage amplifier is connected and generates a feedback voltage The first speed increasing module is connected between the five-tube amplifier and the second-stage amplifier, and the second speed increasing module is connected to the output end of the second-stage amplifier. The five-tube amplifier outputs a driving voltage through the first speed increasing module and the second-stage amplifier. , the driving voltage The output voltage is then controlled by the third stage amplifier The second speed increasing module controls the output voltage through the second voltage controlled current source. The five-tube amplifier is powered by an input voltage Power supply, including the first PMOS tube , the second PMOS tube , the first NMOS tube , the second NMOS tube and current source ; The gate of the , source access and The source and drain are connected The drain of The other end is grounded; The gate is connected to the feedback voltage, and the drain is connected to The drain of the device outputs a first voltage signal ; The gate-drain interconnection, the gate access The gate and source are connected to the input voltage ; The source input voltage The five-tube amplifier is based on a first reference voltage and feedback voltage Output to the first speed increasing module and the second stage amplifier. The second stage amplifier includes a third PMOS tube and a first voltage controlled current source In this embodiment, The sixth NMOS tube . Gate access , source connected to input voltage , drain access The drain and the third stage amplifier and the second speed increasing module, The negative end of the output is grounded. The gate of the third-stage amplifier includes a fourth PMOS transistor , The gate is connected to the The drain and source are connected to the input voltage , drain connected With output voltage The amplifier, and The loop formed constitutes a negative feedback loop. The other end of the connection One end of the feedback voltage signal , The other end of the negative feedback loop makes the first reference voltage Consistent with feedback voltage , and then through and Setting the Output Voltage , the output voltage for: .

[0042] In this embodiment, the first speed increasing module includes a fifth PMOS transistor , the third NMOS tube , the fourth NMOS tube , the fifth NMOS tube and current source . The gate and drain are interconnected, the source is grounded, and the gate is The gate and drain of The drain; The source is grounded and the gate is The drain of The source of The drain terminal , and outputs a second voltage signal to The gate of The other end is connected to the input voltage ; The gate connection Drain, and access , source connected to input voltage , the drain outputs the fourth voltage signal Parallel The drain and The first speed-up module is composed of an input voltage powered by, based on , output control Output internal voltage signal , and thus control The amount of current flowing.

[0043] The second stage amplifier is powered by the input voltage Power supply, based on and , output drive voltage to the third-stage amplifier and the second speed-up module; the third-stage amplifier is input by the voltage power supply, based on the drive voltage , control the output voltage .

[0044] The second speed increasing module is based on the driving voltage and the second reference voltage , output the third voltage signal To the second voltage controlled current source , and control For output voltage In this embodiment The internal part is the seventh NMOS tube , The gate is connected to the second speed-up module, the source is grounded, and the drain is output The second speed increasing module includes a seventh PMOS tube , the eighth PMOS tube and current source , . Source access The drain is connected to the drive voltage , gate access The gate and drain of And output a third voltage signal to The gate of The other end is grounded; The gate-drain interconnection , the source is connected to the second reference voltage The second speed increasing module is based on the driving voltage and the second reference voltage Compare and output a third voltage signal To the second voltage controlled current source In , and control For output voltage of discharge.

[0045] When the output voltage is When the external load on the inverter switches between light load and heavy load, the output voltage Overcharge and undershoot will occur, and the three-stage op amp will be used to adjust the output voltage. The power tube is adjusted to adjust the changes state, thereby controlling the output voltage The three-stage amplifier has a arrive ,pass , undergoes a reverse change process of the voltage signal; and the first speed increasing module to ,from arrive , pass , , , and the voltage signal undergoes three reverse changes. based on Output ,and based on Output , these two behaviors reinforce each other of changes, which accelerates The speed of change. When the overcharge occurs when the heavy load switches to the light load, the negative feedback causes the driving voltage signal becomes high, when the second speed increasing module detects Higher than hour, If the ability is enhanced, The voltage increases when Voltage higher than When the on-state voltage Conductivity, Discharge to improve overcharge. When the load switches from light load to heavy load, The operational amplifier and the first speed-up module jointly Pull it up and stabilize it during the adjustment process; when the load switches from heavy load to light load, Overcharge is regulated by the op amp, the first speed-up module and the second speed-up module. to a stable voltage.

[0046] like Figure 3 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.768V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is only 44.12mV.

[0047] like Figure 4 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.884mA, and the first overcharge duration is 92.74uS. The difference between overcharge and undershoot is 273.9mV.

[0048] like Figure 5 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.537V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is 275mV.

[0049] like Figure 6 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.885mA, the first overcharge duration is 37.08mS, and the overcharge duration is very long.

[0050] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0051] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0052] Embodiment 4: like Figure 8 As shown, an LDO circuit for improving load transient response speed, the circuit includes: a five-tube amplifier, a second-stage amplifier, a third-stage amplifier, a first voltage-dividing sampling resistor , the second voltage-dividing sampling resistor and a second voltage controlled current source , and the input voltage , the first reference voltage , the second reference voltage , ground signal GND and output voltage , the five-tube amplifier, the second-stage amplifier and the third-stage amplifier are connected in sequence, and The third stage amplifier is connected and generates a feedback voltage The first speed increasing module is connected between the five-tube amplifier and the second-stage amplifier, and the second speed increasing module is connected to the output end of the second-stage amplifier. The five-tube amplifier outputs a driving voltage through the first speed increasing module and the second-stage amplifier. , the driving voltage The output voltage is then controlled by the third stage amplifier The second speed increasing module controls the output voltage through the second voltage controlled current source. The five-tube amplifier is powered by an input voltage Power supply, including the first PMOS tube , the second PMOS tube , the first NMOS tube , the second NMOS tube and current source ; The gate of the , source access and The source and drain are connected The drain of The other end is grounded; The gate is connected to the feedback voltage, and the drain is connected to The drain of the device outputs a first voltage signal ; The gate-drain interconnection, the gate access The gate and source are connected to the input voltage ; The source input voltage The five-tube amplifier is based on a first reference voltage and feedback voltage Output to the first speed increasing module and the second stage amplifier. The second stage amplifier includes a third PMOS tube and a first voltage controlled current source In this embodiment, The sixth NMOS tube . Gate access , source connected to input voltage , drain access The drain and the third stage amplifier and the second speed increasing module, The negative end of the output is grounded. The gate of the third-stage amplifier includes a fourth PMOS transistor , The gate is connected to the The drain and source are connected to the input voltage , drain connected With output voltage The amplifier, and The loop formed constitutes a negative feedback loop. The other end of the connection One end of the feedback voltage signal , The other end of the negative feedback loop makes the first reference voltage Consistent with feedback voltage , and then through and Setting the Output Voltage , the output voltage for: .

[0053] In this embodiment, the first speed increasing module includes a fifth PMOS transistor , the sixth PMOS tube ,resistance and current source , . The source terminal The drain of the device is connected to the first voltage signal , gate connection The gate and drain of And output the second voltage signal to The gate of The gate-drain interconnection , source connected ; The other end is connected to the input voltage , The other end of the first speed increasing module is connected to the ground. powered by, based on , output internal voltage signal , and thus control The amount of current flowing.

[0054] The second stage amplifier is powered by the input voltage Power supply, based on and , output drive voltage to the third-stage amplifier and the second speed-up module; the third-stage amplifier is input by the voltage power supply, based on the drive voltage , control the output voltage .

[0055] The second speed increasing module is based on the driving voltage and the second reference voltage , output the third voltage signal To the second voltage controlled current source , and control The discharge of the output voltage. The internal part is the seventh NMOS tube , The gate is connected to the second speed-up module, the source is grounded, and the drain is output The second speed increasing module includes a seventh PMOS tube , the eighth PMOS tube and current source , . Source access The drain is connected to the drive voltage , gate access The gate and drain of And output a third voltage signal to The gate of The other end is grounded; The gate-drain interconnection , the source is connected to the second reference voltage The second speed increasing module is based on the driving voltage and the second reference voltage Compare and output a third voltage signal To the second voltage controlled current source In , and control For output voltage of discharge.

[0056] When the output voltage is When the external load on the inverter switches between light load and heavy load, the output voltage Overcharge and undershoot will occur, and the three-stage op amp will be used to adjust the output voltage. The power tube is adjusted to adjust the changes state, thereby controlling the output voltage The three-stage amplifier has a arrive ,pass , undergoes a reverse change process of the voltage signal; and the first speed increasing module to ,from arrive , pass , , and the voltage signal undergoes a reverse change process. Then based on Output ,and based on Output , these two behaviors reinforce each other of changes, which accelerates The speed of change. When the overcharge occurs when the heavy load switches to the light load, the negative feedback causes the driving voltage signal becomes high, when the second speed increasing module detects Higher than hour, If the ability is enhanced, The voltage increases when Voltage higher than When the on-state voltage Conductivity, Discharge to improve overcharge. When the load switches from light load to heavy load, The operational amplifier and the first speed-up module jointly Pull it up and stabilize it during the adjustment process; when the load switches from heavy load to light load, Overcharge is regulated by the op amp, the first speed-up module and the second speed-up module. to a stable voltage.

[0057] like Figure 4 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.884mA, and the first overcharge duration is 92.74uS. The difference between overcharge and undershoot is 273.9mV.

[0058] like Figure 5 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.537V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is 275mV.

[0059] like Figure 6 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.885mA, the first overcharge duration is 37.08mS, and the overcharge duration is very long.

[0060] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0061] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0062] Embodiment five: like Figure 1 As shown, a method for improving the load transient response speed is provided. This embodiment is based on the LDO circuit of the second embodiment. The specific method steps of this embodiment are as follows: S1: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with the voltage undershoot.

[0063] S2: When the external load is switched, the amplifier, the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

[0064] A new embodiment of the LDO circuit structure can be obtained by replacing and changing part of the structure of the LDO circuit in this embodiment. The new embodiment has the same function and effect.

[0065] For example, in the third embodiment, the first speed increasing module and the second speed increasing module are expanded. , The first speed increasing module includes a fifth PMOS tube , the third NMOS tube , the fourth NMOS tube , the fifth NMOS tube and current source . The gate and drain are interconnected, the source is grounded, and the gate is The gate and drain of The drain; The source is grounded and the gate is The drain of The source of The drain terminal , and outputs a second voltage signal to The gate of The other end is connected to the input voltage ; The gate connection Drain, and access , source connected to input voltage , the drain outputs the fourth voltage signal Parallel The drain and The first speed-up module is composed of an input voltage powered by, based on , output control Output internal voltage signal , and thus control The second-stage amplifier is controlled by the input voltage Power supply, based on and , output drive voltage to the third-stage amplifier and the second speed-up module; the third-stage amplifier is input by the voltage power supply, based on the drive voltage , control the output voltage The second speed increasing module is based on the driving voltage and the second reference voltage , output the third voltage signal To the second voltage controlled current source , and control For output voltage In this embodiment The internal part is the seventh NMOS tube , The gate is connected to the second speed-up module, the source is grounded, and the drain is output The second speed increasing module includes a seventh PMOS tube , the eighth PMOS tube and current source , . Source access The drain is connected to the drive voltage , gate access The gate and drain of And output a third voltage signal to The gate of The other end is grounded; The gate-drain interconnection , the source is connected to the second reference voltage The second speed increasing module is based on the driving voltage and the second reference voltage Compare and output a third voltage signal To the second voltage controlled current source In , and control For output voltage When the output voltage is When the external load on the inverter switches between light load and heavy load, the output voltage Overcharge and undershoot will occur, and the three-stage op amp will be used to adjust the output voltage. The power tube is adjusted to adjust the changes state, thereby controlling the output voltage The three-stage amplifier has a arrive ,pass , undergoes a reverse change process of the voltage signal; and the first speed increasing module to ,from arrive , pass , , , and the voltage signal undergoes three reverse changes. based on Output ,and based on Output , these two behaviors reinforce each other of changes, which accelerates The speed of change. When the overcharge occurs when the heavy load switches to the light load, the negative feedback causes the driving voltage signal becomes high, when the second speed increasing module detects Higher than hour, If the ability is enhanced, The voltage increases when Voltage higher than When the on-state voltage Conductivity, Discharge to improve overcharge. When the load switches from light load to heavy load, The operational amplifier and the first speed-up module jointly Pull it up and stabilize it during the adjustment process; when the load switches from heavy load to light load, Overcharge is regulated by the op amp, the first speed-up module and the second speed-up module. to a stable voltage.

[0066] For example, in the fourth embodiment, the first speed increasing module and the second speed increasing module are expanded. , The first speed increasing module includes a fifth PMOS tube , the sixth PMOS tube ,resistance and current source , . The source terminal The drain of the device is connected to the first voltage signal , gate connection The gate and drain of And output the second voltage signal to The gate of The gate-drain interconnection , source connected ; The other end is connected to the input voltage , and The other end of the first speed increasing module is connected to the ground. powered by, based on , output internal voltage signal , and thus control The second-stage amplifier is controlled by the input voltage Power supply, based on and , output drive voltage to the third-stage amplifier and the second speed-up module; the third-stage amplifier is input by the voltage power supply, based on the drive voltage , control the output voltage .

[0067] The second speed increasing module is based on the driving voltage and the second reference voltage , output the third voltage signal To the second voltage controlled current source , and control For output voltage In this embodiment The internal part is the seventh NMOS tube , The gate is connected to the second speed-up module, the source is grounded, and the drain is output The second speed increasing module includes a seventh PMOS tube , the eighth PMOS tube and current source , . Source access The drain is connected to the drive voltage , gate access The gate and drain of And output a third voltage signal to The gate of The other end is grounded; The gate-drain interconnection , the source is connected to the second reference voltage The second speed increasing module is based on the driving voltage and the second reference voltage Compare and output a third voltage signal To the second voltage controlled current source In , and control For output voltage When the output voltage is When the external load on the inverter switches between light load and heavy load, the output voltage Overcharge and undershoot will occur, and the three-stage op amp will be used to adjust the output voltage. The power tube is adjusted to adjust the changes state, thereby controlling the output voltage The three-stage amplifier has a arrive ,pass , undergoes a reverse change process of the voltage signal; and the first speed increasing module to ,from arrive , pass , , and the voltage signal undergoes a reverse change process. Then based on Output ,and based on Output , these two behaviors reinforce each other of changes, which accelerates The speed of change. When the overcharge occurs when the heavy load switches to the light load, the negative feedback causes the driving voltage signal becomes high, when the second speed increasing module detects Higher than hour, If the ability is enhanced, The voltage increases when Voltage higher than When the on-state voltage Conductivity, Discharge to improve overcharge. When the load switches from light load to heavy load, The operational amplifier and the first speed-up module jointly Pull it up and stabilize it during the adjustment process; when the load switches from heavy load to light load, Overcharge is regulated by the op amp, the first speed-up module and the second speed-up module. to a stable voltage.

[0068] like Figure 4 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.884mA, and the first overcharge duration is 92.74uS. The difference between overcharge and undershoot is 273.9mV.

[0069] like Figure 5 Shown are: The external load current is switched between 1mA and 300mA at a speed of 10us. When switching from a light load of 1mA to 300mA, The minimum undershoot value is 2.537V; when When switching from 300mA to 1mA, The maximum overcharge value is 2.812mA, and the first overcharge duration is 20.54uS. The difference between overcharge and undershoot is 275mV.

[0070] like Figure 6 As shown: i(rout) is the externally added load current, which switches rapidly between no-load and 300mA at a speed of 100nS. When switching from light load to no load to 300mA, The minimum undershoot value is 2.611V; when When switching from 300mA to no-load, The maximum overcharge value is 2.885mA, the first overcharge duration is 37.08mS, and the overcharge duration is very long.

[0071] Advantages of the implementation of the present invention: When the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge, thereby improving transient response capability.

[0072] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. An LDO circuit for improving load transient response speed, comprising an amplifier, an internal circuit, an input terminal and an output terminal, and an input voltage , the first reference voltage , the second reference voltage and output voltage The amplifier and the internal circuit are connected to the input and output ends, the input end is connected to the input voltage, and the output end is connected to the external load, characterized in that: It also includes a first speed-increasing module connected between the amplifiers and a second speed-increasing module connected between the amplifier and the internal circuit; when the external load is switched, the amplifier and the first speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed-increasing module and the second speed-increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

2. The LDO circuit for improving load transient response speed according to claim 1, characterized in that: The amplifier is divided into a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. The internal circuit includes a first voltage-dividing sampling resistor, a second voltage-dividing sampling resistor and a second voltage-controlled current source. The first speed-increasing module is connected between the first-stage amplifier and the second-stage amplifier, and the second speed-increasing module is connected to the output end of the second-stage amplifier.

3. The LDO circuit for improving load transient response speed according to claim 2, characterized in that: The first stage amplifier is a five-tube amplifier, which is composed of an input voltage power supply, including a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a current source; the gate of the first NMOS tube is connected to a first reference voltage , the source is connected to the current source and the source of the second NMOS tube, and the drain is connected to the drain of the first PMOS tube; the other end of the current source is grounded; the gate of the second NMOS tube is connected to the feedback voltage , the drain is connected to the drain of the second PMOS tube and outputs a first voltage signal; the gate and drain of the first PMOS tube are interconnected, the gate is connected to the gate of the second PMOS tube, and the source is connected to the input voltage ; The source of the second PMOS tube is connected to the input voltage ; The five-tube amplifier is based on a first reference voltage The first voltage signal is outputted by the feedback voltage to the first speed increasing module and the second stage amplifier.

4. The LDO circuit for improving load transient response speed according to claim 3, characterized in that: The second stage amplifier includes a third PMOS tube and a first voltage-controlled current source, wherein the gate of the third PMOS tube is connected to the first voltage signal, and the source is connected to the input voltage The drain is connected to the positive end of the output of the first voltage-controlled current source and the third-stage amplifier and the second speed-increasing module, and the negative end of the output of the first voltage-controlled current source is grounded; the third-stage amplifier includes a fourth PMOS tube, the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the source is connected to the input voltage , the drain is connected to the first voltage divider sampling resistor and the output voltage .

5. The LDO circuit for improving load transient response speed according to claim 4, characterized in that: The loop formed by the amplifier, the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor forms a negative feedback loop, the other end of the first voltage-dividing sampling resistor is connected to one end of the second voltage-dividing sampling resistor and outputs a feedback voltage signal; the other end of the second voltage-dividing sampling resistor is grounded; the negative feedback loop makes the first reference voltage consistent with the feedback voltage, and then sets the output voltage through the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor, and the output voltage is: .

6. The LDO circuit for improving load transient response speed according to claim 4, characterized in that: The first speed increasing module is input voltage power supply, based on the first voltage signal, output a second voltage signal to the first voltage-controlled current source and control its current; the second-stage amplifier is powered by the input voltage Power supply, based on the first voltage signal and the second voltage signal, output driving voltage to the third stage amplifier and the second speed increasing module.

7. The LDO circuit for improving load transient response speed according to claim 6, characterized in that: The third stage amplifier is composed of an input voltage power supply, based on the drive voltage, controls the output voltage ; The second speed increasing module outputs a third voltage signal to the second voltage controlled current source based on the driving voltage and the second reference voltage, and controls the second voltage controlled current source to output the voltage of discharge.

8. A method for improving load transient response speed, implemented based on the LDO circuit according to any one of claims 1 to 7, characterized in that: The method includes the following steps: when the external load is switched, the amplifier and the first speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage undershoot, or the amplifier and the first speed increasing module and the second speed increasing module jointly output a signal to the internal circuit to control the output voltage to cope with voltage overcharge.

9. The method for improving load transient response speed according to claim 8, characterized in that: The method of controlling the output voltage to cope with voltage undershoot by jointly outputting a signal to the internal circuit through the amplifier and the first speed increasing module includes: the amplifier includes a first voltage controlled current source, the amplifier outputs a first voltage signal and a driving voltage, the first speed increasing module outputs a second voltage signal based on the first voltage signal, when the first voltage signal increases, the current of the first voltage controlled current source decreases based on the second voltage signal, and the first speed increasing module accelerates the speed at which the driving voltage rises; when the first voltage signal weakens, the current of the first voltage controlled current source increases based on the second voltage signal, and the first speed increasing module accelerates the speed at which the driving voltage decreases.

10. The method for improving load transient response speed according to claim 8, characterized in that: The method of controlling the output voltage to cope with voltage overcharge by jointly outputting a signal to an internal circuit by the amplifier, a first speed increasing module, and a second speed increasing module includes: the amplifier includes a first voltage controlled current source and a second voltage controlled current source, the amplifier outputs a first voltage signal and a driving voltage, the amplifier generates a feedback voltage internally, the first speed increasing module outputs a second voltage signal based on the first voltage signal, and the output voltage When overcharged, the feedback voltage rises and the first voltage signal drops, the current of the first voltage-controlled current source decreases based on the second voltage signal, the first speed-increasing module accelerates the speed of the driving voltage rising, and the second speed-increasing module generates a third voltage signal after detecting that the driving voltage is higher than the second reference voltage, and controls the second voltage-controlled current source to increase the output voltage. Discharge, so that the output voltage Reduce; the output voltage During the undershoot, the first voltage signal changes and causes the current of the first voltage-controlled current source to change based on the second voltage signal, so that the output voltage Increase.

Images