Display panel, manufacturing method thereof and display device

Abstract

The invention is applicable to the technical field of display equipment, and provides a display panel, a manufacturing method thereof and a display device.The display panel comprises a driving circuit layer, a first metal layer and a plurality of pixel groups, the driving circuit layer comprises a plurality of pixel circuits, the first metal layer is arranged on one side of the driving circuit layer, and the pixel groups are arranged on the other side of the driving circuit layer; the pixel group is arranged on the side, away from the driving circuit layer, of the first metal layer, the pixel group comprises a plurality of sub-pixels, the first metal layer comprises a plurality of signal line groups, and each signal line group comprises a first reference signal line, a second reference signal line and a third reference signal line which are arranged at intervals; the first reference signal line, the second reference signal line and the third reference signal line are arranged along a first direction parallel to the surface of the driving circuit layer. According to the display panel, the phenomenon of uneven low-gray-scale display of the display panel can be improved, and the display brightness uniformity of the display panel is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of display devices, and in particular, relates to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Diode) display panels have been widely used due to their advantages such as lighter weight, higher brightness, lower power consumption, faster response and higher definition.

[0003] In the OLED display panel of the related art, there are problems such as poor display brightness uniformity and poor display effect. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a display panel and a manufacturing method thereof, and a display device to solve the problems of poor display brightness uniformity and poor display effect existing in the current OLED display panel.

[0005] A first aspect of an embodiment of the present application provides a display panel, comprising: a driving circuit layer, a first metal layer and a plurality of pixel groups arranged in an array, wherein the first metal layer is arranged on one side of the driving circuit layer, each of the pixel groups is arranged on a side of the first metal layer away from the driving circuit layer, each of the pixel groups comprises a plurality of sub-pixels, the first metal layer comprises a plurality of signal line groups arranged corresponding to each of the pixel groups, each of the signal line groups comprises a first reference signal line, a second reference signal line and a third reference signal line arranged at intervals from each other, and the first reference signal line, the second reference signal line and the third reference signal line are all arranged along a first direction parallel to a surface of the driving circuit layer.

[0006] The above-mentioned display panel, by setting signal line groups corresponding to pixel groups in the first metal layer, each signal line group includes a first reference signal line, a second reference signal line and a third reference signal line that are spaced from each other and set along a first direction parallel to the surface of the driving circuit layer. In this way, the wiring space inside the display panel is optimized, and the array arrangement design of the first reference signal line, the second reference signal line and the third reference signal line corresponding to the pixel group can be realized, which can improve the low grayscale display unevenness of the display panel, improve the display brightness uniformity of the display panel, and thereby enhance its display effect.

[0007] In one embodiment, each of the signal line groups includes a plurality of the third reference signal lines. This design can mainly increase the wiring density of the third reference signal lines, and further enhance the improvement effect on display brightness uniformity.

[0008] In one embodiment, the second reference signal line is located on one side of the first reference signal line in a second direction, the second direction is parallel to the surface of the driving circuit layer and intersects with the first direction; at least one of the third reference signal lines is located between the first reference signal line and the second reference signal line; and / or at least one of the third reference signal lines is located on one side of the second reference signal line in the second direction. By reasonably setting the positions of the first reference signal line, the second reference signal line and the third reference signal line, it is beneficial to optimize the wiring space in the first metal layer and improve the wiring density.

[0009] In one embodiment, each of the signal line groups further includes a first voltage signal line and a first fan-out signal line, wherein the first voltage signal line and the first fan-out signal line are both arranged along the first direction, and the first voltage signal line and the first fan-out signal line are both located between the first reference signal line and the second reference signal line; and at least one third reference signal line is located between the first voltage signal line and the first fan-out signal line. By arranging at least one third reference signal line between the first voltage signal line and the first fan-out signal line, the relative wiring positions between the first voltage signal line, the first fan-out signal line and the third reference signal line can be optimized, thereby improving the wiring density.

[0010] In one embodiment, each of the signal line groups further includes a second voltage signal line and a second fan-out signal line, the second voltage signal line and the second fan-out signal line are both arranged along the first direction, and the second voltage signal line and the second fan-out signal line are both located on one side of the second reference signal line in the second direction; at least one third reference signal line is located between the second voltage signal line and the second fan-out signal line. By arranging at least one third reference signal line between the second voltage signal line and the second fan-out signal line, the relative wiring positions between the second voltage signal line, the second fan-out signal line and the third reference signal line can be optimized, thereby improving the wiring density.

[0011] In one embodiment, the first metal layer includes a plurality of data line groups corresponding to the pixel groups; each of the data line groups includes a first data line and a second data line spaced apart from each other, the first data line and the second data line are spaced along the first direction, and the first data line and the second data line are located on both sides of the first reference signal line in the second direction, the second direction is parallel to the surface of the driving circuit layer and intersects with the first direction; each of the data line groups includes a third data line and a fourth data line spaced apart from each other, the third data line and the fourth data line are spaced along the first direction, and the third data line and the fourth data line are located on both sides of the second reference signal line in the second direction. By arranging the first data line and the second data line on both sides of the first reference signal line in the second direction, the relative wiring positions between the first data line, the second data line and the first reference signal line can be optimized, and the wiring density can be improved; by arranging the third data line and the fourth data line on both sides of the second reference signal line in the second direction, the relative wiring positions between the third data line, the fourth data line and the second reference signal line can be optimized, and the wiring density can be improved.

[0012] In one embodiment, the display panel also includes a plurality of pixel circuits corresponding to each of the pixel groups, each of the pixel circuits includes a driving transistor, a first initialization transistor, a second initialization transistor and a third initialization transistor; the first reference signal line is electrically connected to the first initialization transistor, and the first initialization transistor is used to initialize the driving transistor; the second reference signal line is electrically connected to the second initialization transistor, and the second initialization transistor is used to initialize the sub-pixel; the third reference signal line is electrically connected to the third initialization transistor, and the third initialization transistor is used to initialize the driving transistor.

[0013] In one embodiment, the first reference signal line, the second reference signal line and the third reference signal line are all in a grid shape. By setting the first reference signal line, the second reference signal line and the third reference signal line in a grid shape, their respective resistances can be made smaller, and accordingly, the voltage drop when they transmit the power signal is reduced, so that the voltage difference of the power signal received by the sub-pixels at different positions is reduced, thereby improving the display uniformity of the display panel and improving the picture display quality.

[0014] The second aspect of the embodiments of the present application provides a method for manufacturing a display panel as described in the first aspect, comprising: forming a first metal layer on one side of a driving circuit layer; patterning the first metal layer to form a plurality of signal line groups, each of the signal line groups comprising a first reference signal line, a second reference signal line and a third reference signal line spaced apart from each other, the first reference signal line, the second reference signal line and the third reference signal line being arranged along a first direction parallel to a surface of the driving circuit layer; forming a plurality of pixel groups on a side of the first metal layer away from the driving circuit layer, each of the pixel groups comprising a plurality of sub-pixels, and each of the signal line groups being arranged corresponding to each of the pixel groups.

[0015] The display panel manufactured using the above-mentioned manufacturing method can optimize the wiring space inside the display panel, realize the array arrangement design of the first reference signal line, the second reference signal line and the third reference signal line corresponding to the pixel group, improve the low grayscale display unevenness of the display panel, improve the display brightness uniformity of the display panel, and thus enhance its display effect.

[0016] A third aspect of the embodiments of the present application provides a display device, comprising the display panel as described in the first aspect.

[0017] It can be understood that the beneficial effects of the third aspect can be found in the relevant descriptions of the first and second aspects, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a simplified structural schematic diagram of a display panel in the related art;

[0020] Figure 2 is a schematic diagram of a top view structure of a reference signal line in a display panel in the related art;

[0021] Figure 3 is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present application;

[0022] Figure 4 is a simplified structural diagram of a pixel group and a signal line group in a display panel provided by an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of the structure of a pixel group in a display panel provided in an embodiment of the present application;

[0024] Figure 6 is a simplified structural diagram of a pixel group in a display panel provided in an embodiment of the present application;

[0025] Figure 7 is a schematic diagram of a top view of the structure of a display panel provided in an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of a top view structure of a signal line group in a display panel provided in an embodiment of the present application;

[0027] Fig. 9 is a schematic diagram of a top view structure of an M0 metal layer in a display panel provided in an embodiment of the present application;

[0028] Fig.10 is a schematic diagram of a top view structure of a gate layer in a display panel provided in an embodiment of the present application;

[0029] Fig.11 is a schematic diagram of a top view structure of the M1 metal layer in the display panel provided in an embodiment of the present application;

[0030] Fig.12 is a schematic diagram of a top view structure of an M2 metal layer in a display panel provided in an embodiment of the present application;

[0031] Fig.13 is a schematic diagram of a top view structure of a first pattern layer in a display panel provided in an embodiment of the present application;

[0032] Fig.14 is a schematic diagram of a top view of the structure of a second pattern layer in a display panel provided in an embodiment of the present application;

[0033] Fig.15 is a schematic diagram of a top view of the structure of a first insulating layer in a display panel provided in an embodiment of the present application;

[0034] Fig.16 is a schematic diagram of a top view structure of an M3 metal layer in a display panel provided in an embodiment of the present application;

[0035] Fig.17 is a schematic diagram of a top view structure of a first flat layer in a display panel provided in an embodiment of the present application;

[0036] Fig.18 is a schematic diagram of a top view of the structure of a second flat layer in a display panel provided in an embodiment of the present application;

[0037] Fig.19 is a schematic diagram of a top view structure of a first electrode in a display panel provided in an embodiment of the present application;

[0038] Fig. 20is a schematic diagram of a top view structure of a pixel definition layer in a display panel provided in an embodiment of the present application;

[0039] Fig.21 is a schematic structural diagram of a pixel circuit in a display panel provided in an embodiment of the present application;

[0040] Fig. 22 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0041] Fig.23 It is a schematic diagram of the overall structure of the display device provided in an embodiment of the present application.

[0042] Figure Number:

[0043] 10. Display device;

[0044] 100. Display panel;

[0045] 110, driving circuit layer, 111, pixel circuit, 1111, driving transistor, 1112, first initialization transistor, 1113, second initialization transistor, 1114, third initialization transistor, 112, M0 metal layer, 113, gate layer, 114, M1 metal layer; 115, M2 metal layer, 116, first pattern layer, 117, second pattern layer, 118, first insulating layer, 119, M3 metal layer;

[0046] 120, a first metal layer, 121, a signal line group, 1211, a first reference signal line, 1212, a second reference signal line, 1213, a third reference signal line, 1214, a first voltage signal line, 1215, a first fan-out signal line, 1216, a second voltage signal line, 1217, a second fan-out signal line, 122, a data line group, 1221, a first data line, 1222, a second data line, 1223, a third data line, 1224, a fourth data line;

[0047] 130, pixel group, 131, sub-pixel, 1311, first electrode;

[0048] 140, first flat layer;

[0049] 150, second flat layer;

[0050] 160, pixel definition layer;

[0051] y, first direction, x, second direction. DETAILED DESCRIPTION

[0052] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0053] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0054] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0055] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0056] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. "Multiple" means two or more.

[0058] like Figure 1 to Figure 2As shown, the display panel 1 in the related art includes a plurality of pixel groups 11 arranged in an array and a reference signal line group 12 arranged in each pixel group 11, each pixel group 11 includes a plurality of sub-pixels, wherein Figure 1 As shown in the first pixel group 11 from left to right, the reference signal line group 12 includes a first reference signal line 13 (Vref1) and a second reference signal line 14 (Vref2) which are arranged in sequence from left to right. In the second pixel group 11, the reference signal line group 12 includes two third reference signal lines 15 (Vref3) which are arranged in sequence. In the third pixel group 11, the reference signal line group 12 includes a second reference signal line 14 (Vref2) and a first reference signal line 13 (Vref1) which are arranged in sequence from left to right.

[0059] It can be seen that in order to realize the three-grid design of the reference signal line, two adjacent pixel groups 11 need to cooperate, which is realized by the alternating arrangement of the first reference signal line 13 (Vref1), the second reference signal line 14 (Vref2) and the third reference signal line 15 (Vref3). The three pixel groups 11 jointly realize the three-grid design of the two groups of reference signal lines. In this way, the three-grid design of the reference signal line cannot be one-to-one corresponding to the arrangement of the pixel groups, and the improvement of the low grayscale display unevenness of the display panel is also very limited.

[0060] To at least partially address the above issues, see Figures 3 to 7 An embodiment of the present application provides a display panel 100 , which includes a driving circuit layer 110 , a first metal layer 120 and a pixel group 130 .

[0061] The driving circuit layer 110 can support and carry other film layers in the display panel 100. For example, the driving circuit layer 110 can be made of materials such as polyimide (PI). In the embodiment of the present application, the pixel group 130 is arranged on the side of the first metal layer 120 away from the driving circuit layer 110. Each pixel group 130 includes a plurality of sub-pixels 131, and the driving circuit layer 110 includes a pixel circuit 111.

[0062] In some embodiments, the number of pixel groups 130 can be multiple, and each pixel group 130 can be arranged in an array according to actual needs. The number of pixel circuits 111 in the driving circuit layer 110 can also be multiple. It should be noted that one pixel circuit 111 can be set corresponding to one sub-pixel 131 in the pixel group 130, or multiple pixel circuits 111 can be set corresponding to one sub-pixel 131 in the pixel group 130, or one pixel circuit 111 can be set corresponding to multiple sub-pixels 131 in the pixel group 130. There is no limitation here. Under the drive of the pixel circuit 111, different sub-pixels 131 located in the display area of ​​the display panel 100 can be excited to emit light of different colors, so that the display panel 100 can achieve a colorful display effect.

[0063] In some embodiments, the structure of a portion of the pixel group 130 in the display panel 100 is shown as follows: Figure 5 and Figure 6 As shown, the multiple sub-pixels 131 in each pixel group 130 are roughly arranged in two rows and four columns. Specifically, one red sub-pixel 131 (R), one blue sub-pixel 131 (B) and two green sub-pixels 131 (G) are roughly arranged in the first row, and one blue sub-pixel 131 (B), one red sub-pixel 131 (R) and two green sub-pixels 131 (G) are roughly arranged in the second row. The sub-pixels 131 in the first row and the second row are aligned with each other in the column direction so that the red sub-pixel 131 (R), the blue sub-pixel 131 (B) and the green sub-pixel 131 (G) can surround each other as much as possible.

[0064] Specifically, if Figure 3 As shown, in some embodiments, the driving circuit layer 110 also includes an M0 metal layer 112, a gate layer 113, an M1 metal layer 114, an M2 metal layer 115, a first pattern layer 116, a second pattern layer 117, a first insulating layer 118, an M3 metal layer 119 and an interlayer insulating layer arranged between two adjacent metal layers, which are stacked in sequence.

[0065] The top view of the arrangement of the circuits in the display panel 100 can be found in Figure 7 The top view of the signal line group 121 in the display panel 100 can be found in Figure 8 The top view structure of the M0 metal layer 112 in the display panel 100 can be found in Fig. 9 The top view of the gate layer 113 in the display panel 100 can be found in Fig.10 The top view structure of the M1 metal layer 114 in the display panel 100 can be found in Fig.11 The top view structure of the M2 metal layer 115 in the display panel 100 can be found in Fig.12The top view of the structure of the first pattern layer 116 in the display panel 100 can be found in Fig.13 The top view of the second pattern layer 117 in the display panel 100 can be found in Fig.14 The top view of the structure of the first insulating layer 118 in the display panel 100 can be found in Fig.15 The top view structure of the M3 metal layer 119 in the display panel 100 can be found in Fig.16 .

[0066] Please also read Figure 3 and Figure 4 The display panel may also include a first metal layer 120 stacked in sequence on the driving circuit layer 110, a pixel group 130, a first flat layer 140 arranged between the driving circuit layer 110 and the first metal layer 120, a second flat layer 150 arranged between the first metal layer 120 and the pixel group 130, and a pixel definition layer 160 arranged on the second flat layer 150, the pixel definition layer 160 defines a pixel opening, and the sub-pixel 131 includes a first electrode 1311 and a light-emitting material arranged in the pixel opening.

[0067] The top view of the first flat layer 140 in the display panel 100 can be found in Fig.17 The top view of the second flat layer 150 in the display panel 100 can be seen in Fig.18 The top view structure of the first electrode 1311 in the display panel 100 can be seen in Fig.19 The top view of the pixel definition layer 160 in the display panel 100 can be found in Fig. 20 .

[0068] The first metal layer 120 is disposed on one side of the driving circuit layer 110, wherein the first metal layer 120 may include a plurality of different types of signal lines to be electrically connected to the driving circuit in the display panel, so as to transmit various different signals, for example, the gate signal line is used to transmit the scanning signal Gate to the driving circuit, the data signal line is used to transmit the data signal Data to the driving circuit, and the voltage signal line is used to provide the working voltage for the light emitting device. Figure 4 As shown, the first metal layer 120 includes a plurality of signal line groups 121 arranged corresponding to each pixel group 130, and each signal line group 121 includes a first reference signal line 1211 (Vref1), a second reference signal line 1212 (Vref2) and a third reference signal line 1213 (Vref3) arranged at intervals from each other, and the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3) are all arranged along a first direction y parallel to the surface of the driving circuit layer 110.

[0069] The display panel 100 of the embodiment of the present application is provided with a signal line group 121 corresponding to the pixel group 130 in the first metal layer 120, and each signal line group 121 includes a first reference signal line 1211 (Vref1), a second reference signal line 1212 (Vref2) and a third reference signal line 1213 (Vref3) which are spaced apart from each other and arranged along a first direction y parallel to the surface of the driving circuit layer 110. In this way, the wiring space inside the display panel 100 is optimized, and the array arrangement design of the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3) corresponding to the pixel group 130 can be realized, which can improve the low grayscale display unevenness of the display panel 100, improve the display brightness uniformity of the display panel 100, and thereby enhance its display effect.

[0070] As described above, each signal line group 121 includes at least one first reference signal line 1211 (Vref1), at least one second reference signal line 1212 (Vref2) and at least one third reference signal line 1213 (Vref3). In some embodiments, optionally, each signal line group 121 includes multiple third reference signal lines 1213 (Vref3). Such a design can mainly increase the wiring density of the third reference signal line 1213 (Vref3) and further enhance the improvement effect on the uniformity of display brightness. In this embodiment, the number of the first reference signal line 1211 (Vref1) and the second reference signal line 1212 (Vref2) in each signal line group 121 can be one or more.

[0071] On the basis of the above embodiment, optionally, the second reference signal line 1212 (Vref2) is located at one side of the first reference signal line 1211 (Vref1) in the second direction x, and the second direction x is parallel to the surface of the driving circuit layer 110 and intersects with the first direction y; at least one third reference signal line 1213 (Vref3) is located between the first reference signal line 1211 (Vref1) and the second reference signal line 1212 (Vref2), or at least one third reference signal line 1213 (Vref3) is located at one side of the second reference signal line 1212 (Vref2) in the second direction x. When the signal line group 121 includes a plurality of third reference signal lines 1213 (Vref3), at least one third reference signal line 1213 (Vref3) is located between the first reference signal line 1211 (Vref1) and the second reference signal line 1212 (Vref2), and at least another third reference signal line 1213 (Vref3) is located at one side of the second reference signal line 1212 (Vref2) in the second direction x.

[0072] By properly setting the positions of the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3), it is beneficial to optimize the wiring space in the first metal layer 120 and improve the wiring density.

[0073] The specific number and location of the plurality of third reference signal lines 1213 (Vref3) are not limited. Figure 7 In some embodiments, optionally, each signal line group 121 further includes a first voltage signal line 1214 (VDD) and a first fan-out signal line 1215 (fiaa), and the first voltage signal line 1214 (VDD) and the first fan-out signal line 1215 (fiaa) are both arranged along the first direction y, and the first voltage signal line 1214 (VDD) and the first fan-out signal line 1215 (fiaa) are both located between the first reference signal line 1211 (Vref1) and the second reference signal line 1212 (Vref2); at least one third reference signal line 1213 (Vref3) is located between the first voltage signal line 1214 (VDD) and the first fan-out signal line 1215 (fiaa). Such an arrangement can optimize the relative wiring positions between the first voltage signal line 1214 (VDD), the first fan-out signal line 1215 (fiaa) and the third reference signal line 1213 (Vref3), and improve the wiring density.

[0074] Please continue reading Figure 7 In some embodiments, optionally, each signal line group 121 further includes a second voltage signal line 1216 (VDD) and a second fan-out signal line 1217 (fiaa), the second voltage signal line 1216 (VDD) and the second fan-out signal line 1217 (fiaa) are both arranged along the first direction y, and the second voltage signal line 1216 (VDD) and the second fan-out signal line 1217 (fiaa) are both located on one side of the second reference signal line 1212 (Vref2) in the second direction x; at least one third reference signal line 1213 (Vref3) is located between the second voltage signal line 1216 (VDD) and the second fan-out signal line 1217 (fiaa). Similarly, such an arrangement can optimize the relative wiring positions between the second voltage signal line 1216 (VDD), the second fan-out signal line 1217 (fiaa) and the third reference signal line 1213 (Vref3), and improve the wiring density.

[0075] like Figure 7As shown, in some embodiments, optionally, the first metal layer 120 includes a plurality of data line groups 122 corresponding to each pixel group 130, and each data line group 122 may include a first data line 1221 (Data) and a second data line 1222 (Data) spaced apart from each other, the first data line 1221 (Data) and the second data line 1222 (Data) are both arranged along the first direction y, and the first data line 1221 (Data) and the second data line 1222 (Data) are respectively located on both sides of the first reference signal line 1211 (Vref1) in the second direction x, and the second direction x is parallel to the surface of the driving circuit layer 110 and intersects with the first direction y. In this way, the relative wiring positions between the first data line 1221 (Data), the second data line 1222 (Data) and the first reference signal line 1211 (Vref1) can be optimized, and the wiring density can be improved.

[0076] Each data line group 122 may further include a third data line 1223 (Data) and a fourth data line 1224 (Data) spaced apart from each other, the third data line 1223 (Data) and the fourth data line 1224 (Data) are both arranged along the first direction y, and the third data line 1223 (Data) and the fourth data line 1224 (Data) are respectively located on both sides of the second reference signal line 1212 (Vref2) in the second direction x. In this way, the relative wiring positions between the third data line 1223 (Data), the fourth data line 1224 (Data) and the second reference signal line 1212 (Vref2) can be optimized, and the wiring density can be improved.

[0077] See also Fig.21 In some embodiments, optionally, the display panel 100 further includes a plurality of pixel circuits 111 corresponding to each pixel group 130, each pixel circuit 111 including a driving transistor 1111, a first initialization transistor 1112, a second initialization transistor 1113 and a third initialization transistor 1114; a first reference signal line 1211 (Vref1) is electrically connected to the first initialization transistor 1112, the first initialization transistor 1112 is used to initialize the driving transistor 1111, specifically, to initialize the gate of the driving transistor 1111 and discharge its capacitance; a second reference signal line 1212 (Vref2) is electrically connected to the second initialization transistor 1113, the second initialization transistor 1113 is used to initialize the sub-pixel 131, specifically, to initialize the first electrode 1311 of the sub-pixel 131; a third reference signal line 1213 (Vref3) is electrically connected to the third initialization transistor 1114, the third initialization transistor 1114 is used to initialize the driving transistor 1111.

[0078] In some embodiments, optionally, the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2), and the third reference signal line 1213 (Vref3) are all in a grid shape. By setting the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2), and the third reference signal line 1213 (Vref3) in a grid shape, their respective resistances can be made smaller, and accordingly, by reducing the voltage drop when they transmit the power signal, the voltage difference of the power signal received by the sub-pixels 131 at different positions is reduced, thereby improving the display uniformity of the display panel 100 and improving the picture display quality.

[0079] Based on the same invention concept, please combine Figures 3 to 7 Also see Fig. 22 The present application also provides a method for manufacturing the display panel 100 as in any one of the above embodiments, the manufacturing method comprising the following steps:

[0080] S102 , forming a first metal layer 120 on one side of the driving circuit layer 110 .

[0081] S104, patterning the first metal layer 120 to form a plurality of signal line groups 121, each signal line group 121 comprising a first reference signal line 1211 (Vref1), a second reference signal line 1212 (Vref2) and a third reference signal line 1213 (Vref3) spaced apart from each other, the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3) being arranged along a first direction y parallel to the surface of the driving circuit layer 110.

[0082] S106 , forming a plurality of pixel groups 130 on a side of the first metal layer 120 away from the driving circuit layer 110 , each pixel group 130 includes a plurality of sub-pixels 131 , and each signal line group 121 is disposed corresponding to each pixel group 130 .

[0083] The display panel 100 manufactured using the above-mentioned manufacturing method can optimize the wiring space inside the display panel 100, and can realize the array arrangement design of the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3) corresponding to the pixel group 130, which can improve the low grayscale display unevenness of the display panel 100, improve the display brightness uniformity of the display panel 100, and thereby enhance its display effect.

[0084] See also Fig.23The embodiment of the present application further provides a display device 10, which includes a display panel 100 as in any one of the above embodiments.

[0085] The display panel 100 disclosed in the embodiment of the present application is applied to the display device 10 to provide the function of displaying a picture. The display device 10 can be any product or component with a display function, including but not limited to a mobile phone, a tablet computer, a laptop computer, an e-reader, a wearable device, a remote control, a television, a desktop computer, a vehicle-mounted device, etc. Since the display panel 100 in any of the above embodiments is adopted, the wiring space inside the display panel 100 can be optimized, and the array arrangement design of the first reference signal line 1211 (Vref1), the second reference signal line 1212 (Vref2) and the third reference signal line 1213 (Vref3) corresponding to the pixel group 130 can be realized, which can improve the uneven display phenomenon of low grayscale of the display panel 100, improve the uniformity of the display brightness of the display panel 100, and thus improve its display effect.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A driving circuit layer, a first metal layer and a plurality of pixel groups, the driving circuit layer comprising a plurality of pixel circuits, the first metal layer being arranged on one side of the driving circuit layer, the pixel group being arranged on a side of the first metal layer away from the driving circuit layer, the pixel group comprising a plurality of sub-pixels, the first metal layer comprising a plurality of signal line groups, each of the signal line groups comprising a first reference signal line, a second reference signal line and a third reference signal line which are arranged in the same layer and spaced apart from each other, the first reference signal line, the second reference signal line and the third reference signal line being connected to the pixel circuits respectively, and the first reference signal line, the second reference signal line and the third reference signal line being arranged along a first direction parallel to a surface of the driving circuit layer.

2. The display panel according to claim 1, wherein: Each of the signal line groups includes a plurality of the third reference signal lines.

3. The display panel according to claim 2, wherein: The second reference signal line is located at one side of the first reference signal line in a second direction, and the second direction is parallel to the surface of the driving circuit layer and intersects with the first direction; At least one of the third reference signal lines is located between the first reference signal line and the second reference signal line; and / or At least one of the third reference signal lines is located at one side of the second reference signal line in the second direction.

4. The display panel according to claim 3, wherein: Each of the signal line groups further includes a first voltage signal line and a first fan-out signal line, wherein the first voltage signal line and the first fan-out signal line are both arranged along the first direction, and the first voltage signal line and the first fan-out signal line are both located between the first reference signal line and the second reference signal line; At least one of the third reference signal lines is located between the first voltage signal line and the first fan-out signal line.

5. The display panel according to claim 3, wherein: Each of the signal line groups further includes a second voltage signal line and a second fan-out signal line, the second voltage signal line and the second fan-out signal line are both arranged along the first direction, and the second voltage signal line and the second fan-out signal line are both located on one side of the second reference signal line in the second direction; At least one of the third reference signal lines is located between the second voltage signal line and the second fan-out signal line.

6. The display panel according to claim 1, wherein: The first metal layer further includes a plurality of data line groups arranged corresponding to the pixel groups; Each of the data line groups comprises a first data line and a second data line spaced apart from each other, the first data line and the second data line are both arranged along the first direction, and the first data line and the second data line are respectively located on both sides of the first reference signal line in the second direction, and the second direction is parallel to the surface of the driving circuit layer and intersects with the first direction; Each of the data line groups includes a third data line and a fourth data line spaced apart from each other, the third data line and the fourth data line are arranged along the first direction, and the third data line and the fourth data line are respectively located on both sides of the second reference signal line in the second direction.

7. The display panel according to claim 1, wherein: Each of the pixel circuits comprises a driving transistor, a first initialization transistor, a second initialization transistor and a third initialization transistor; The first reference signal line is electrically connected to the first initialization transistor, and the first initialization transistor is used to initialize the driving transistor; The second reference signal line is electrically connected to the second initialization transistor, and the second initialization transistor is used to initialize the sub-pixel; The third reference signal line is electrically connected to the third initialization transistor, and the third initialization transistor is used to initialize the driving transistor.

8. The display panel according to any one of claims 1 to 7, characterized in that: The first reference signal line, the second reference signal line and the third reference signal line are all in a grid shape.

9. A method for manufacturing a display panel, characterized in that: include: forming a first metal layer on one side of the driving circuit layer; Patterning the first metal layer to form a plurality of signal line groups, each of the signal line groups comprising a first reference signal line, a second reference signal line and a third reference signal line spaced apart from each other, the first reference signal line, the second reference signal line and the third reference signal line being arranged along a first direction parallel to a surface of the driving circuit layer; A plurality of pixel groups are formed on a side of the first metal layer away from the driving circuit layer, each of the pixel groups includes a plurality of sub-pixels, and each of the signal line groups is arranged corresponding to each of the pixel groups.

10. A display device, characterized in that: A display panel according to any one of claims 1 to 8.

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