Erasing durability improving method of memory-computing integrated flash memory

Abstract

The invention relates to the field of flash memories, in particular to a method for improving erasing durability of a memory-computing integrated flash memory. According to the method, firstly, a high threshold voltage mode is adopted when programming and erasing operations of the flash memory are carried out, the high threshold voltage mode carries out programming and erasing in a high voltage mode when the threshold voltage of a single device ranges from 6.5 V to 7V, the erasing durability of the flash memory is effectively enhanced, and the flash memory is more excellent in an environment with a small storage window requirement. And secondly, the device degradation caused by the erasing pulse is reduced by adopting an electric field assisted relaxation pulse mode, and the device degradation process caused by hot hole injection can be effectively slowed down by introducing the electric field assisted relaxation pulse, so that the service life of the flash memory is prolonged, and the reliability of the flash memory is improved. According to the method, high-threshold voltage programming and erasing and electric field assisted relaxation pulse are comprehensively utilized, and an innovative solution is provided for performance improvement of the flash under a specific application scene.

Description

Technical Field

[0001] The present invention relates to the field of flash memory, and in particular to a method for improving the erasing and writing durability of a storage-computing integrated flash memory. Background Art

[0002] Storage-computing integration is an innovative architecture that integrates storage and computing functions. It aims to solve the performance bottleneck and energy consumption problems caused by the frequent transmission of data between computing nodes and storage nodes in traditional computing models. The core idea of ​​this architecture is to integrate storage and computing resources in the same processing unit to reduce the need for data transmission, improve computing efficiency, and reduce the overall energy consumption of the system.

[0003] The storage-computing integrated architecture is of great significance for modern big data applications, artificial intelligence, deep learning and other computing-intensive tasks. By integrating storage and computing, the storage-computing integrated architecture is expected to provide a more efficient solution when processing massive data and complex computing tasks. Therefore, the research and optimization of the storage-computing integrated architecture has attracted much attention in the current computing field to promote the development of computing models and performance improvement. Flash memory is expected to realize the storage-computing integrated architecture with its excellent reliability. However, the erase and write durability of existing flash memory is usually around 10 5 This greatly limits the number of times the storage-computing integration updates weights, thereby limiting the application of flash memory in the storage-computing integration field. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for improving the erase and write durability of a storage-computing integrated flash memory, thereby effectively improving the durability of the flash memory by reducing the storage window.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a method for improving the erase and write durability of a storage-computing integrated flash memory, the method comprising: When programming and erasing the flash memory, a high threshold voltage mode is used. The high threshold voltage mode performs programming and erasing in a high voltage mode when the threshold voltage of a single device is 6.5V to 7V. Since the device is less damaged during erasing, the flash memory can be repeatedly erased and written. Therefore, the high voltage mode erasing is expected to effectively enhance the erasing and writing durability of the flash memory, making it perform better in an environment with a small storage window requirement. The electric field assisted relaxation pulse is used to reduce the device degradation caused by the erase pulse, that is, the electric field assisted relaxation pulse is introduced in the opposite direction of the erase voltage, thereby reducing the defect generation during the erase process; by introducing the electric field assisted relaxation pulse in the opposite direction of the erase voltage, the defect generation during the erase process can be reduced, thereby effectively slowing down the device degradation process caused by hot hole injection and improving the service life and reliability of the flash memory. This method combines high threshold voltage programming and erasing with electric field assisted relaxation pulses (EAR), providing an innovative solution for improving the performance of flash memory in specific application scenarios.

[0006] Furthermore, the electric field assisted relaxation pulse is to apply a positive voltage pulse of duration T1 to the device gate after the hot hole injection erase pulse during the erase process, and T1 is between 8 ns and 12 ns; by applying the electric field assisted relaxation pulse, some holes will be trapped in the tunneling layer oxide during the erase cycle, thereby increasing the potential barrier of the tunneling layer, which reduces the efficiency of hole injection and may cause additional defects. Therefore, by the proposed scheme of adding electric field assisted relaxation pulses, the holes in the tunneling oxide defects are released, and the above-mentioned damage can be suppressed to a certain extent.

[0007] Furthermore, the amplitude of the electric field-assisted relaxation pulse was 0.5 V and the duration was 10 ns.

[0008] Furthermore, a high threshold voltage mode is achieved through charge injection.

[0009] Furthermore, when the external drain voltage is constant, the charge injection amount is changed by changing the gate voltage, the positive and negative polarity and the duration, so that the threshold voltage of the flash memory transistor moves.

[0010] Furthermore, the erase and write durability of this method is increased to 10 10 .

[0011] Beneficial effects of the present invention: The present invention adopts a high threshold voltage mode when programming and erasing devices, that is, programming and erasing are performed in a high voltage mode with a single device threshold voltage of about 7V. This is expected to effectively enhance the erase and write durability of the flash memory, making it perform better in an environment with a small storage window requirement.

[0012] Secondly, in order to combat the device degradation problem caused by hot hole injection, the present invention adopts an innovative electric field assisted relaxation pulse (EAR) method to reduce the device degradation caused by the erase pulse. By introducing the electric field assisted relaxation pulse, the device degradation process caused by hot hole injection can be effectively slowed down, thereby improving the service life and reliability of the flash memory. The uniqueness of this method lies in the comprehensive use of high threshold voltage programming and erasure and electric field assisted relaxation pulses, which provides an innovative solution for improving the performance of flash memory in specific application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of threshold voltage mode optimization in the present invention, a is a schematic diagram of a low threshold voltage mode, b is a schematic diagram of a high threshold voltage mode; Figure 2 A schematic diagram of an electric field-assisted relaxation pulse in the present invention; Figure 3 1 is a statistical diagram of the effect of the low threshold voltage mode, a is an IV curve diagram under the low threshold voltage mode, b is a schematic diagram of the change of the subthreshold swing with the number of erase and write times under the low threshold voltage mode, and c is a schematic diagram of the change of the off-state current with the number of erase and write times under the low threshold voltage mode; Figure 4 1 is a statistical diagram of the effect of the high threshold voltage mode, a is an IV curve diagram under the high threshold voltage mode, b is a schematic diagram of the change of the subthreshold swing with the number of erase and write times under the high threshold voltage mode, and c is a schematic diagram of the change of the off-state current with the number of erase and write times under the high threshold voltage mode; Figure 5 Figure 1 is a statistical diagram of the effect after adding electric field assisted relaxation pulses, a is the IV curve after adding electric field assisted relaxation pulses, b is a schematic diagram of the change of subthreshold swing with the number of erase and write times after adding electric field assisted relaxation pulses, c is a schematic diagram of the change of off-state current with the number of erase and write times after adding electric field assisted relaxation pulses, and d is a schematic diagram of the change of on-state current with the number of erase and write times after adding electric field assisted relaxation pulses. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0015] Example 1 The present embodiment discloses a method for improving the erase and write durability of a storage-computing integrated flash memory. Since the storage-computing integrated has much lower requirements for the storage window than ordinary storage applications, the demand for the storage window is relatively small. Therefore, in this specific scenario, the durability of the flash memory can be effectively improved by reducing the storage window. This method first adopts a high threshold voltage mode when programming and erasing the device, that is, programming and erasing in a high voltage mode when the threshold voltage of a single device is 6.5V to 7V. Due to the small damage to the device during erasure, the flash memory can be erased and written repeatedly, so the high voltage mode erasing is expected to effectively enhance the erase and write durability of the flash memory, making it perform better in an environment with a small storage window requirement.

[0016] Secondly, in order to combat the device degradation caused by hot hole injection, this method uses electric field assisted relaxation pulses to reduce the device degradation caused by erase pulses. By introducing an electric field assisted relaxation pulse that is opposite to the erase voltage, defect generation during the erase process can be reduced, thereby effectively slowing down the device degradation process caused by hot hole injection and improving the life and reliability of the flash memory. The uniqueness of this solution lies in the comprehensive use of high threshold voltage programming and erasing and electric field assisted relaxation pulses (EAR), which provides an innovative solution for improving the performance of flash memory in specific application scenarios.

[0017] The hot hole injection is an erasing scheme for flash memory, which applies a negative bias to the gate to attract hot holes generated by a high electric field to be injected into the insulating layer, resulting in a redistribution of charges in the insulating layer, thereby erasing the flash memory cell.

[0018] The electric field assisted relaxation pulse (EAR) refers to a short (about 10ns) positive voltage pulse applied to the device gate after the hot hole injection erase pulse during the erase process. By applying the electric field assisted relaxation pulse, some holes will be trapped in the tunneling layer oxide during the erase cycle, thereby increasing the potential barrier of the tunneling layer, which reduces the efficiency of hole injection and may cause additional defects. Therefore, by the proposed scheme of adding electric field assisted relaxation pulses, the holes in the tunneling oxide defects are released, and the above-mentioned damage can be suppressed to a certain extent.

[0019] This embodiment is implemented on a 55nm NOR array flash memory and the improvement effect is tested. By changing the charge injection, the transfer characteristic curve of the transistor, as well as the threshold voltage, transconductance, subthreshold swing, etc. are obtained.

[0020] Figure 1 The present invention provides a specific operation mode for extending the erase and write endurance of the flash memory by optimizing the threshold voltage mode. The threshold voltage mode optimization means that the threshold voltage of the flash memory has two operation modes, namely Figure 1 The high threshold voltage mode and low threshold voltage mode shown in 1a and 1b are programmed in different threshold voltage ranges. The experimental results show that the flash memory has better durability in the high threshold voltage mode. Figure 2 The present invention provides a specific operation mode of extending the erase and write durability of the flash memory through the electric field relaxation mode. The electric field relaxation mode refers to adding an additional EAR pulse. After the flash memory is erased, an EAR pulse with the amplitude and duration shown in the figure is added on the basis of the original erase pulse, thereby improving the durability of the flash memory. Figure 2 The amplitude of the EAR pulse is 0.5V and the duration is 10ns.

[0021] The principle of charge injection to adjust the threshold voltage is as follows Figure 3 ,4 As shown in the figure, as the injected charge increases, the number of electrons captured by the gate oxide layer increases, and the threshold voltage increases. By applying a certain drain voltage, the charge injection amount is changed by changing the gate voltage, the positive and negative polarity, and the duration, so that the transistor threshold voltage moves. Figure 3 , 4 By comparison, it can be seen that the high threshold voltage mode achieves 10 10 durability and has a lower off-state current I off .

[0022] Figure 5 The transfer characteristic curves under different gate voltages are given. When a positive gate voltage is applied, the transfer characteristic curve of the transistor shifts to the right, and the threshold voltage also moves accordingly. When a reverse gate voltage is applied, the transfer characteristic curve of the transistor and the threshold voltage shift to the left. The positive and negative and magnitude of the applied gate voltage can effectively change the threshold voltage, and the process is reversible. When a positive gate voltage is applied, the transfer characteristic curve moves, and when a negative gate voltage is applied, the transfer characteristic curve moves in the opposite direction. According to Figure 5 It can be seen that the high threshold voltage mode with the addition of EAR pulse achieves 10 10 durability and has a lower off-state current I off , on-state current I on rise.

[0023] Figure 3 , 4 In 5, HHI represents hot hole injection, CHEI represents channel hot electron injection, and V g represents the applied gate bias, V d represents the applied drain bias, What is described above are only the basic principles and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A method for improving the erase and write durability of a storage-computing integrated flash memory, characterized in that: The method includes: When performing programming and erasing operations on the flash memory, a high threshold voltage mode is used. The high threshold voltage mode performs programming and erasing in a high voltage mode when the threshold voltage of a single device is 6.5V to 7V; An electric field-assisted relaxation pulse is used to reduce device degradation caused by the erase pulse, that is, an electric field-assisted relaxation pulse opposite to the erase voltage is introduced to reduce defect generation during the erase process.

2. The method for improving the erase and write durability of the storage-computation integrated flash memory according to claim 1, characterized in that: The electric field assisted relaxation pulse is a positive voltage pulse with a duration of T1 applied to the device gate after the hot hole injection erase pulse during the erase process. T1 is between 8 ns and 12 ns.

3. The method for improving the erase and write durability of the storage-computation integrated flash memory according to claim 1 or 2, characterized in that: The electric field-assisted relaxation pulse had an amplitude of 0.5 V and a duration of 10 ns.

4. The method for improving the erase and write durability of the storage-computation integrated flash memory according to claim 1, characterized in that: High threshold voltage mode is achieved by charge injection.

5. The method for improving the erase and write durability of the storage-computation integrated flash memory according to claim 4, characterized in that: When the external drain voltage is constant, the charge injection amount is changed by changing the gate voltage, positive and negative polarity, and duration, causing the threshold voltage of the flash memory transistor to move.

6. The method for improving the erase and write durability of the storage-computation integrated flash memory according to claim 1, characterized in that: The erase and write durability of this method is increased to 10 10 .

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