Assembly comprising word line having first metal-containing material at least partially surrounding second metal-containing material and having crystallinity different from crystallinity of second metal-containing material

Abstract

The present disclosure relates to an assembly comprising a word line having a first metal-containing material at least partially surrounding a second metal-containing material and having a crystallinity different from the crystallinity of the second metal-containing material. Some embodiments include a memory array having a vertical stack of alternating insulation levels and word line levels. A channel material extends vertically along the stack. The word line level includes a conductive region having a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a crystallinity different from a crystallinity of the second metal-containing material. In some embodiments, the first metal-containing material is substantially amorphous and the second metal-containing material has a mean grain size in a range from greater than or equal to about 5 nm to less than or equal to about 200 nm.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application of the invention patent application with an application date of March 3, 2020, application number 202080028697.7, and invention name "An assembly comprising a word line having a first metal-containing material that at least partially surrounds a second metal-containing material and has a crystallinity different from that of the second metal-containing material."

[0003] Related patent data

[0004] This patent claims priority to U.S. patent application No. 16 / 383,862, filed on April 15, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0005] The present invention relates to an assembly (eg, a NAND memory architecture) including a word line having a first metal-containing material that at least partially surrounds a second metal-containing material and has a crystallinity that is different from the crystallinity of the second metal-containing material. Background Art

[0006] Memory provides data storage for electronic systems. Flash memory is a type of memory and is used extensively in modern computers and devices. For example, a modern personal computer may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives instead of traditional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0007] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0008] Before describing NAND in detail, it may be helpful to more generally describe the relationship of the memory array within the integrated arrangement. FIG. 1 shows a block diagram of a prior art device 1000 that includes a memory array 1002 of a plurality of memory cells 1003 arranged in rows and columns along with access lines 1004 (e.g., word lines that conduct signals WL0 to WLm) and first data lines 1006 (e.g., bit lines that conduct signals BL0 to BLn). The access lines 1004 and the first data lines 1006 may be used to transfer information into and out of the memory cells 1003. The row decoder 1007 and the column decoder 1008 decode the address signals A0 to AX on the address lines 1009 to determine which of the memory cells 1003 are to be accessed. The sense amplifier circuit 1015 is used to determine the value of the information read from the memory cell 1003. The I / O circuit 1017 transfers information values ​​between the memory array 1002 and the input / output (I / O) lines 1005. The signals DQ0 to DQN on the I / O line 1005 may represent the value of information to be read from or written to the memory cell 1003. Other devices may communicate with the device 1000 through the I / O line 1005, the address line 1009, or the control line 1020. The memory control unit 1018 is used to control the memory operation to be performed on the memory cell 1003, and uses the signal on the control line 1020. The device 1000 may receive supply voltage signals Vcc and Vss on the first supply line 1030 and the second supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input / output (I / O) circuit 1017. The selection circuit 1040 may respond to the signals CSEL1 to CSELn via the I / O circuit 1017 to select the signals on the first data line 1006 and the second data line 1013 that may represent the value of information to be read from or programmed into the memory cell 1003. Column decoder 1008 may selectively activate CSEL1 through CSELn signals based on A0 through AX address signals on address lines 1009. Selection circuit 1040 may select signals on first and second data lines 1006 and 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0009] The memory array 1002 of FIG. 1 may be a NAND memory array, and FIG. 2 shows a block diagram of a three-dimensional NAND memory device 200 that may be used for the memory array 1002 of FIG. 1 . The device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one above the other, wherein each charge storage device corresponds to, for example, one of thirty-two rows (tiers) (e.g., Tier0-Tier31). The charge storage devices of the corresponding strings may share a common channel region, such as a common channel region formed in a corresponding semiconductor material (e.g., polysilicon) column, around which the charge storage device string is formed. In a second direction (XX'), each first group (e.g., sixteen first groups) of the multiple strings may include, for example, eight strings that share multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines", also referred to as word lines WL). Each of the access lines may couple the charge storage devices within a layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same level) may be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group of the plurality of strings (e.g., eight second groups) may include sixteen strings coupled by corresponding data lines of the eight data lines. The size of the memory block may include 1024 pages and a total of approximately 16MB (e.g., 16WL×32 rows×2 bits=1024 pages / block, block size=1024 pages×16KB / page=16MB). The number of strings, rows, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in FIG. 2 .

[0010] 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to FIG. The memory block 300 of the plurality of strings may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as I , Piece Column j and tile columns K, where each subset (e.g., tile column) includes a "partial block" of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGD of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or cut off the SGD of the strings of the corresponding partial block (e.g., tile column) independently of the SGD of the strings of the other partial blocks. A global source-side select gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding sub-SGS driver in a plurality of sub-SGS drivers 322, 324, 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., tile column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or cut off the SGS of the strings of the corresponding partial block (e.g., tile column) independently of the SGS of the strings of the other partial blocks. The global access line (e.g., global CG line) 350 may couple the charge storage devices of the corresponding rows of each string in the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding sub-string driver in a plurality of sub-string drivers 312, 314, and 316. Each of the substring drivers may simultaneously couple or disconnect the charge storage devices corresponding to the corresponding partial blocks and / or rows independently of the charge storage devices of other partial blocks and / or other rows. The charge storage devices corresponding to the corresponding subsets (e.g., partial blocks) and corresponding rows may include charge storage devices of a "partial row" (e.g., a single "tile"). The strings corresponding to the corresponding subsets (e.g., partial blocks) may be coupled to corresponding sub-sources of the sub-sources 372, 374, and 376 (e.g., "tile sources"), each of which is coupled to a corresponding power source.

[0011] Alternatively, refer to Figure 4 A schematic diagram of a NAND memory device 200 is depicted.

[0012] The memory array 200 includes word lines 2021 to 202 N , and bit lines 2281 to 228 M .

[0013] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string includes charge storage transistors 2081 to 208 NThe charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0014] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series in a source-to-drain manner between a source selection device (e.g., a source side selection gate SGS) 210 and a drain selection device (e.g., a drain side selection gate SGD) 212. Each source selection device 210 is located at the intersection of the string 206 and the source selection line 214, and each drain selection device 212 is located at the intersection of the string 206 and the drain selection line 215. The selection devices 210 and 212 can be any suitable access devices, and are used Figure 4 The boxes in the figure are generally described.

[0015] The source of each source select device 210 is connected to the common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select devices 210 are connected to the source select line 214.

[0016] The drain of each drain select device 212 is connected to a bit line (i.e., digit line) 228 at a drain contact. For example, the drain of drain select device 2121 is connected to bit line 2281. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain select device 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N of the drain.

[0017] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are commonly coupled to a given word line 202.

[0018] A three-dimensional NAND architecture may have multiple vertically stacked word lines. Each of the word lines may include a conductive liner surrounding a metal-containing core material. The conductive liner may have any of a number of purposes; and may, for example, improve adhesion of the core material, provide desired work function properties, etc. An ongoing goal is to increase the number of stacked memory cells within a three-dimensional NAND, and a corresponding goal is to increase the number of vertically stacked word lines within a NAND memory array.

[0019] One problem that can be encountered during NAND architecture fabrication is that the wafer including the NAND components can bow; this can complicate fabrication and may even damage the wafer. This problem becomes increasingly severe as the number of vertically stacked word lines increases.

[0020] Improved designs are needed to alleviate the above problems. Summary of the invention

[0021] In one aspect, the present disclosure provides a memory cell comprising: a conductive gate comprising only two metal-containing materials; the two metal-containing materials comprising a first metal-containing material that completely encapsulates a core second metal-containing material; the crystallinity of the first metal-containing material and the core second metal-containing material are different from each other, wherein the core second metal-containing material has a larger average grain size than the first metal-containing material; the first metal-containing material comprises one or more of the following compositions: metal carbide, metal oxide, metal silicide, metal nitride and metal germanide; and a charge blocking region adjacent to the conductive gate; a charge storage region adjacent to the charge blocking region; and wherein the compositions of the first metal-containing material and the core second metal-containing material are the same as each other.

[0022] On the other hand, the present disclosure provides a memory cell comprising: a conductive gate; the conductive gate comprises a first metal-containing material that substantially encapsulates a second metal-containing material; the first metal-containing material comprises a gradient interface with the second metal-containing material; the gradient interface comprises one of the following configurations: as the thickness of the second metal-containing material increases from the first metal-containing material, the percentage of the first metal-containing material decreases and the percentage of the second metal-containing material increases, wherein most of the central portion of the second metal-containing material comprises only the second metal-containing material; or as the thickness of the second metal-containing material increases from the first metal-containing material, the percentage of the first metal-containing material decreases and the percentage of the second metal-containing material increases until reaching a peak at the center of the second metal-containing material; the crystallinity of the first metal-containing material and the second metal-containing material are different from each other, wherein the second metal-containing material has a larger average grain size than the first metal-containing material; and a charge blocking region adjacent to the conductive gate; and a charge storage region adjacent to the charge blocking region.

[0023] On the other hand, the present disclosure provides a memory cell comprising: a conductive gate; the conductive gate comprises a first metal-containing material that substantially encapsulates a second metal-containing material; the first metal-containing material comprises a non-discrete material boundary with the second metal-containing material; the non-discrete material boundary comprises one of the following configurations: as the thickness of the second metal-containing material increases from the first metal-containing material, the percentage of the first metal-containing material decreases and the percentage of the second metal-containing material increases, wherein most of the central portion of the second metal-containing material comprises only the second metal-containing material; or as the thickness of the second metal-containing material increases from the first metal-containing material, the percentage of the first metal-containing material decreases and the percentage of the second metal-containing material increases until reaching a peak at the center of the second metal-containing material; the crystallinity of the first metal-containing material and the second metal-containing material are different from each other, wherein the second metal-containing material has a larger mean grain size than the first metal-containing material; and a charge blocking region adjacent to the conductive gate; and a charge storage region adjacent to the charge blocking region. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 shows a block diagram of a prior art memory device having a memory array of memory cells.

[0025] 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0026] FIG. 3 illustrates a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 along the XX′ direction.

[0027] Figure 4 is a schematic diagram of a prior art NAND memory array.

[0028] Figure 5 is a schematic cross-sectional side view of a region of an integrated assembly including an example memory array.

[0029] Figure 5A It is along Figure 5 Schematic top view of line 5A-5A. Figure 5 Along Figure 5A Line 5-5.

[0030] Figure 6 yes Figure 5 A schematic cross-sectional enlarged view of a region labeled “6” of an example memory array.

[0031] Figure 7-9 is a diagram illustrating the relationship between the components of an instance assembly and the instance depth.

[0032] Fig.10 is a schematic cross-sectional side view of a region of an integrated assembly including an example memory array.

[0033] Fig.11 yes Fig.10 A schematic cross-sectional enlarged view of a region labeled “11” of an example memory array.

[0034] Fig. 12A and 12B This is to describe the bow configuration ( Fig. 12A ) and unbowed configurations ( Fig. 12B ) is a schematic cross-sectional side view of a semiconductor wafer. DETAILED DESCRIPTION

[0035] Some embodiments include a NAND memory array having a conductive word line containing a first metal-containing material and a second metal-containing material. The first metal-containing material may substantially encapsulate the second metal-containing material, or may at least partially surround the second metal-containing material; and may include a crystallinity that is less than the crystallinity of the second metal-containing material. In some embodiments, the first metal-containing material may be substantially amorphous, and the second metal-containing material may include a median grain size in a range from at least about 5 nanometers (nm) to less than or equal to about 200 nm; wherein the term "about 5 nm" means 5 nm within a reasonable tolerance of manufacturing and measurement, and the term "about 200 nm" means 200 nm within a reasonable tolerance of manufacturing and measurement. The first metal-containing material and the second metal-containing material may be the same composition as one another, or may include different compositions relative to one another. In some embodiments, the first metal-containing material may be a metal nitride (e.g., tungsten nitride, titanium nitride, etc.), and the second metal-containing material may consist primarily of a metal (e.g., tungsten, titanium, etc.). The first metal-containing material may be formed very thin, and in some embodiments, may have a thickness of less than or equal to about 100 angstroms. The first metal-containing material may be continuous or discontinuous.

[0036] Utilizing a thin first metal-containing material having a relatively low crystallinity compared to a second metal-containing material can enable the formation of a NAND memory array without the wafer bow issues described above in the Background section. Figure 5 -12 describes example embodiments and advantages.

[0037] refer to Figure 5 and 5A The construction 10 , which is also referred to as an integrated assembly or as an integrated structure, includes a stack 14 of alternating first and second levels 16 , 18 .

[0038] First level 16 includes insulating material 20, and second level 18 includes conductive region 22. Levels 16 and 18 may have any suitable thickness. Level 16 may have a thickness different from the thickness of level 18, or may have the same thickness as level 18. In some embodiments, levels 16 and 18 may have a thickness in a range from about 5 nm to about 50 nm. In some embodiments, conductive region 22 may have a thickness T in a range from about 5 nm to about 50 nm.

[0039] Insulating material 20 may include any suitable composition or combination of compositions; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide.

[0040] Insulating material 24 extends around conductive region 22. Insulating material 24 may correspond to a dielectric barrier material; and may include any suitable composition. In some embodiments, dielectric barrier material 24 may include a high-k material (e.g., one or more of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, etc.); wherein the term "high-k" means a dielectric constant greater than the dielectric constant of silicon dioxide. Although insulating material 24 is shown as a single homogenous material, in other embodiments, the insulating material may include two or more discrete compositions. Insulating material 24 has horizontally extending segments 21, and has vertically extending segments 23.

[0041] Conductive region 22 includes conductive word lines. In some embodiments, conductive level 18 may be referred to as a word line level (memory cell level) of a NAND configuration. A NAND configuration may include a string of memory cells (a so-called NAND string), where the number of memory cells in the string is determined by the number of memory cell layers 18. A NAND string may include any suitable number of memory cell layers. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0042] Levels 16 may be referred to as insulating levels that alternate with wordline levels 18 within stack 14. Such insulating levels 16 may be considered to include insulating material 20, and to include horizontally extending segments 21 of insulating material 24.

[0043] Structure 28 extends through stack 14. Structure 28 may be referred to as a channel material structure because it includes channel material 30. Channel material 30 includes a semiconductor material; and may include any suitable composition or combination of compositions. For example, channel material 30 may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Groups III and V of the periodic table (wherein Groups III and V are old nomenclature, now referred to as Groups 13 and 15).

[0044] Between the channel material 30 and the vertically stacked levels 16 / 18 are tunneling material (sometimes referred to as gate dielectric material) 32, charge storage material 34, and charge blocking material 36. The tunneling material, charge storage material, and charge blocking material may include any suitable composition or combination of compositions.

[0045] In some embodiments, tunneling material 32 may include, for example, one or more of silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, and the like.

[0046] In some embodiments, charge storage material 34 may include a charge trapping material such as silicon nitride, silicon oxynitride, conductive nanodots, etc. In alternative embodiments, charge storage material 34 may be configured to include a floating gate material (eg, polysilicon).

[0047] In some embodiments, the charge blocking material 36 may include one or more of silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, and the like.

[0048] In the illustrated embodiment, channel material 30 is configured as annular rings within each of structures 28. Insulating material 38 fills such annular rings. Insulating material 38 may include any suitable composition or combination of compositions, such as silicon dioxide. The illustrated structures 28 may be considered to include a hollow channel configuration because insulating material 38 is disposed within a "void" in the annular channel configuration. In other embodiments (not shown), channel material may be configured as a solid pillar configuration.

[0049] Channel material structure 28 may be considered to include all of materials 30 , 32 , 34 , 36 , and 38 combined. Figure 5A The top view of illustrative embodiment shows that the channel material structures 28 may be arranged in a hexagonal pattern.

[0050] Slots (trench) 40 extend through stack 14, and such slots are filled with insulating material 42. Insulating material 42 may comprise any suitable composition, and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0051] In some embodiments, stack 14 may be viewed as a vertically extending stack, and structure 28 may be viewed as a vertically extending channel material structure through stack 14 .

[0052] Stack 14 is above supporting base 12. Base 12 may include semiconductor material; and and may, for example, include, consist primarily of, or consist of single crystal silicon. Base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconductor material, including but not limited to integral semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

[0053] A gap is shown between substrate 12 and stack 14 to diagrammatically indicate that there may be one or more additional materials, components, etc. disposed between substrate 12 and stack 14. Such additional components may include, for example, conductive source lines, select gates, etc.

[0054] The word line level 18 includes conductive gates 44 (only some of which are labeled) adjacent to the channel material structures 28. The conductive gates 44, together with the vertically extending regions 23 of the dielectric barrier material 24 and the regions of the channel material structures 28, form memory cells 46. Such memory cells are incorporated into a three-dimensional NAND memory array 48 similar to the NAND memory arrays described above with reference to FIGS. 1-4. The memory cells 46 are all substantially identical to each other (where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement).

[0055] In operation, the charge storage material 34 can be configured to store information in the memory cell 46. The value of the information stored in an individual memory cell (the term "value" means one or more bits) can be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the electrical memory cell. The amount of charge within an individual charge storage region can be controlled (e.g., increased or decreased) based at least in part on the value of a voltage applied to an associated gate 44, and / or based at least in part on the value of a voltage applied to an associated channel material 30.

[0056] Tunneling material 32 forms a tunneling region of memory cell 46. Such a tunneling region may be configured to allow for the desired migration (e.g., transport) of charge (e.g., electrons) between charge storage material 34 and channel material 30. The tunneling region may be configured (i.e., engineered) to achieve selected criteria such as, but not limited to, equivalent oxide thickness (EOT). EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region in terms of a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability issues.

[0057] Charge blocking material 36 is adjacent to charge storage material 34 and may provide a mechanism to block charge from flowing from charge storage material 34 to an associated gate 44. Dielectric barrier material 24 is disposed between charge blocking material 36 and an associated gate 44 and may serve to inhibit reverse tunneling of charge carriers from gate 44 toward charge storage material 34. In some embodiments, dielectric barrier material 24 may be viewed as forming a dielectric barrier region within memory cell 46.

[0058] exist Figure 5 In the illustrated embodiment, the conductive region 22 includes a pair of metal-containing materials 50 and 52. The metal-containing material 50 may be referred to as a first metal-containing material, and the metal-containing material 52 may be referred to as a second metal-containing material. A dashed line 51 is provided to illustrate the approximate boundary between the first metal-containing material 50 and the second metal-containing material 52.

[0059] The first metal-containing material 50 and the second metal-containing material 52 extend along all word line levels and are included within the conductive gate 44 .

[0060] Figure 6 Show Figure 5 FIG. 5 is an enlarged view of region “ 6 ” of FIG. 5 to better illustrate first metal-containing material 50 and second metal-containing material 52 in one of conductive regions 22 .

[0061] The first metal-containing material 50 surrounds Figure 651. In some embodiments, the second metal-containing material 52 may be considered to include an outer perimeter that substantially corresponds to the illustrated orientation of the dashed line 51. The first metal-containing material 50 is adjacent to such outer perimeter of the second metal-containing material 52. As shown, the first metal-containing material 50 may completely surround the outer perimeter 51 of the second metal-containing material 52. In some embodiments, the first metal-containing material 50 may at least partially surround the second metal-containing material 52. The term "at least partially surround" includes configurations in which the first metal-containing material 50 completely surrounds the second metal-containing material 52, as well as configurations in which there may be some areas of the periphery 51 of the second metal-containing material 52 that do not overlap with the first metal-containing material 50. In some embodiments, the first metal-containing material 50 may be considered to enclose or at least substantially enclose the second metal-containing material 52 of the conductive region 22. The term "substantially encloses" is used to indicate that the first metal-containing material 50 extends around at least about 90% of the area of ​​the outer boundary 51 of the second metal-containing material 52.

[0062] The crystallinity of the first metal-containing material 50 and the second metal-containing material 52 is different from each other, and the second metal-containing material has a mean (average) grain size greater than that of the first metal-containing material. In some embodiments, the second metal-containing material 52 may have a mean grain size in a range from greater than or equal to about 5 nm to less than or equal to about 200 nm, while the first metal-containing material 50 has a mean grain size less than or equal to about 10 nm (the mean grain size may be determined by any suitable method). In some embodiments, the first metal-containing material 50 may be substantially amorphous (the term "substantially amorphous" means amorphous within reasonable tolerances of manufacturing and measurement); and may, for example, consist primarily of, or consist of, amorphous material.

[0063] In some embodiments, the first metal-containing material 50 may be continuous (or at least substantially continuous, the term "substantially continuous" meaning continuous within reasonable tolerances of manufacturing and measurement), and in other embodiments, may be discontinuous. If the first metal-containing material 50 is continuous, then such material is located along the Figure 6 The cross-sections described may have a width from about To date In some embodiments, the conductive region 22 is arranged along the Figure 6 The cross-section of may have an overall thickness (total thickness) T in the range from about 5 nm to about 50 nm. The thickness T1 of the first metal-containing material 50 may be in the range from about 5% of the total thickness T to about 25% of the total thickness T.

[0064] Dashed line 51 may be considered to represent the interface between first metal-containing material 50 and second metal-containing material 52. Such an interface may be an abrupt boundary where low crystallinity material 50 meets high crystallinity material 52 (the terms "low crystallinity" and "high crystallinity" are used to indicate that material 50 has a lower crystallinity than material 52), or may be gradient. For example, Figure 7-9 The diagram illustrates that the boundary 51 is a sudden change boundary ( Figure 7 ) and has a gradient ( Figure 8 and 9 ) of the present invention. Figure 7 The mutation boundary can be called the mutation interface.

[0065] Figure 6 The first metal-containing material 50 and the second metal-containing material 52 may include the same composition as one another, or may include different compositions relative to one another.

[0066] In some embodiments, the first metal-containing material 50 includes one or more metals in combination with one or more of nitrogen, carbon, silicon, germanium, and oxygen. Thus, the first metal-containing material 50 may include one or more of various metal silicides, metal nitrides, metal carbides, metal oxides, and metal germanides. In some embodiments, the metal within the first metal-containing material 50 may include one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, and aluminum. In some specific examples, the first metal-containing material 50 may include one or more metal nitrides; and may, for example, include one or both of tungsten nitride and titanium nitride, consist essentially of one or both of tungsten nitride and titanium nitride, or consist of one or both of tungsten nitride and titanium nitride.

[0067] In some embodiments, the second metal-containing material 52 may include one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, aluminum, copper, platinum, and palladium. In some embodiments, the second metal-containing material 52 may have the same composition as the first metal-containing material 50, and may include one or more of various metal silicides, metal nitrides, metal carbides, metal oxides, and metal germanides. In other embodiments, the second metal-containing material 52 may consist essentially of or consist of one or more metals selected from the group consisting of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, aluminum, copper, platinum, and palladium. In some embodiments, the metal within the first metal-containing material 50 may be referred to as a first metal, and the metal within the second metal-containing material 52 may be referred to as a second metal.

[0068] Fig.10 The integrated assembly 10 is shown in a configuration in which the first metal-containing material 50 and the second metal-containing material 52 include different compositions relative to each other. Fig.11 Show Fig.10 1 is an enlarged view of region “ 11 ” of FIG. 1 and shows that boundary 51 corresponds to the interface between first metal-containing material 50 and second metal-containing material 52 . Fig.10 and 11 The first metal-containing material 50 and the second metal-containing material 52 may include the same composition as described above. In some embodiments, the first metal-containing material 50 may include, consist essentially of, or consist of one or both of tungsten nitride and titanium nitride; and the second metal-containing material 52 may include, consist essentially of, or consist of tungsten.

[0069] Figure 5-11 The configuration can alleviate or prevent the wafer bow problem described above in the background technology section. Fig. 12A and 12B Shows the bow configuration ( Fig. 12A ) and unbowed configurations ( Fig. 12B ) in chip 60. Fig. 12A The bowed configuration may result from problematic stresses imposed by the conductive material in conventional word lines used in NAND configurations. Fig. 12A The dotted line 61 is provided in the figure to help the reader observe the bow configuration of the wafer 60 illustrated. Figure 5-11 The word line configuration is achieved Fig. 12B . Specifically, the thin, low-crystallinity first metal-containing material 50 can form an adherent template that supports the second metal-containing material 52. Because there are few, if any, grain boundaries along the surface of the template material 50, the second material 52 has relatively fewer nucleation sites than in a configuration in which the template material 50 has a greater crystallinity; this can cause the second material 52 to have larger crystalline grains than would be achieved with a template material 50 having a higher crystallinity. The larger crystalline grains of the second material 52, together with the thin, low-crystallinity nature of the first material 50, can enable the conductive word line region 22 to be formed with less problematic stress than would be achieved with a conventional word line configuration. This can cause the problematic wafer bowing problem of conventional configurations to be mitigated, or even to no longer occur. The mechanisms discussed above for mitigating problematic stress are provided to assist the reader in understanding the embodiments described herein, and do not limit any aspect of any invention described herein unless, to the extent (if at all), the mechanisms are expressly recited in the appended claims.

[0070] The assemblies and structures discussed above may be used within integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0071] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0072] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide language variation to simplify the premise basis within the following claims, rather than to indicate any significant chemical or electrical differences.

[0073] The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the following claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0074] Unless otherwise specified, the cross-sectional views of the accompanying drawings only show features within the plane of the cross-section and do not show material behind the plane of the cross-section in order to simplify the drawing.

[0075] When a structure is referred to as being "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may also be intervening structures. Conversely, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0076] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to an upper surface of the base.

[0077] Some embodiments include a memory cell. The memory cell includes a conductive gate having a first metal-containing material substantially encapsulating a second metal-containing material. The first and second metal-containing materials have different crystallinity from each other, the second metal-containing material having a mean grain size greater than a mean grain size of the first metal-containing material. A charge blocking region is adjacent to the conductive gate. A charge storage region is adjacent to the charge blocking region. A tunneling material is adjacent to the charge storage region. A channel material is adjacent to the tunneling material. The tunneling material is between the channel material and the charge storage region.

[0078] Some embodiments include an assembly having a vertical stack of alternating insulating levels and wordline levels. The wordline levels include a conductive region. The conductive region has a first metal-containing material adjacent to an outer periphery of a second metal-containing material. The first and second metal-containing materials are different in crystallinity and composition from each other. The second metal-containing material has a mean grain size greater than a mean grain size of the first metal-containing material. A charge storage region is adjacent to the conductive region. A charge blocking region is between the charge storage region and the conductive region.

[0079] Some embodiments include a memory array having a vertical stack of alternating insulating levels and word line levels. A channel material extends vertically along the stack. The word line level includes a conductive region having a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size in a range from greater than or equal to about 5 nm to less than or equal to about 200 nm. A charge storage region is adjacent to the word line level. A charge blocking region is between the charge storage region and the conductive region.

[0080] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory cell, comprising: A conductive gate comprising only two metal-containing materials; the two metal-containing materials comprising a first metal-containing material completely encapsulating a core second metal-containing material; the first metal-containing material and the core second metal-containing material have different crystallinity from each other, wherein the core second metal-containing material has a larger mean grain size than the first metal-containing material; the first metal-containing material comprises one or more of the following compositions: metal carbide, metal oxide, metal silicide, metal nitride and metal germanide; and a charge blocking region adjacent to the conductive gate; a charge storage region adjacent to the charge blocking region; and The first metal-containing material and the core second metal-containing material have the same composition.

2. The memory cell of claim 1, wherein the metal within the first metal-containing material comprises one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, and aluminum.

3. The memory cell of claim 1 wherein the metal within the core second metal-containing material comprises one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, aluminum, copper, platinum, and palladium.

4. The memory cell of claim 1 wherein the metal within the first metal-containing material comprises one or more of tantalum, ruthenium, and aluminum.

5. The memory cell of claim 1 wherein the metal within the core second metal-containing material comprises one or more of tantalum, ruthenium, and aluminum.

6. A memory cell comprising: Conductive grid; The conductive gate comprises a first metal-containing material substantially encapsulating a second metal-containing material; the first metal-containing material comprises a gradient interface with the second metal-containing material; the gradient interface comprises one of the following configurations: As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases, wherein a majority central portion of the second metalliferous material comprises only the second metalliferous material; or As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases until reaching a peak at the center of the second metalliferous material; the first metalliferous material and the second metalliferous material have different crystallinity from each other, wherein the second metalliferous material has a larger mean grain size than the first metalliferous material; as well as a charge blocking region adjacent to the conductive gate; as well as A charge storage region is adjacent to the charge blocking region.

7. The memory cell of claim 6, wherein the first metal-containing material comprises one or more of the following compositions: a metal carbide, a metal oxide, and a metal germanide.

8. The memory cell of claim 6, wherein the metal within the first metal-containing material comprises one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, and aluminum.

9. The memory cell of claim 6, wherein the metal within the second metal-containing material comprises one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, aluminum, copper, platinum, and palladium.

10. The memory cell of claim 6 wherein a metal within the first metal-containing material comprises one or more of tantalum, ruthenium, and aluminum.

11. The memory cell of claim 6 wherein the metal within the second metal-containing material comprises one or more of tantalum, ruthenium, and aluminum.

12. The memory cell of claim 6, wherein the first metal-containing material and the second metal-containing material have the same composition as one another.

13. The memory cell of claim 6, wherein the first metal-containing material and the second metal-containing material have compositions that are different from each other.

14. A memory cell comprising: Conductive grid; The conductive gate comprises a first metal-containing material substantially encapsulating a second metal-containing material; the first metal-containing material comprises a non-discrete material boundary with the second metal-containing material; the non-discrete material boundary comprises one of the following configurations: As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases, wherein a majority central portion of the second metalliferous material comprises only the second metalliferous material; or As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases until reaching a peak at the center of the second metalliferous material; the first metalliferous material and the second metalliferous material have different crystallinity from each other, wherein the second metalliferous material has a larger mean grain size than the first metalliferous material; as well as a charge blocking region adjacent to the conductive gate; as well as A charge storage region is adjacent to the charge blocking region.

15. The memory cell of claim 14 wherein the metal within the first metal-containing material comprises one or more of tantalum, ruthenium, and aluminum.

16. The memory cell of claim 14, wherein at least one of the metals within the second metal-containing material comprises tantalum, ruthenium, and aluminum.

17. The memory cell of claim 14, wherein the second metal-containing material comprises one or more of the following compositions: a metal silicide, a metal nitride, a metal carbide, a metal oxide, and a metal germanide.

18. The memory cell of claim 14, wherein the first metal-containing material comprises one or more of the following compositions: a metal carbide, a metal oxide, and a metal germanide.

19. The memory cell of claim 14 wherein the metal within the first metal-containing material comprises one or more of tungsten, tantalum, titanium, ruthenium, molybdenum, cobalt, nickel, and aluminum.

20. The memory cell of claim 14, wherein the first metal-containing material and the second metal-containing material have the same composition as one another.

21. The memory cell of claim 14, wherein the first metal-containing material and the second metal-containing material have compositions that are different from each other.

22. The memory cell of claim 1 wherein a total thickness of the conductive gate comprises a range from about 5 nm to about 50 nm.

23. The memory cell of claim 22, wherein the first metal-containing material comprises a thickness ranging from about 5% of the total thickness to about 25% of the total thickness.

24. The memory cell of claim 1 wherein a mean grain size of the core second metal-containing material comprises a range from greater than or equal to approximately 5 nm to less than or equal to approximately 200 nm.

25. The memory cell of claim 1 wherein the first metal-containing material comprises a mean grain size less than or equal to approximately 10 nm.

26. The memory cell of claim 6 wherein a total thickness of the conductive gate comprises a range from about 5 nm to about 50 nm.

27. The memory cell of claim 6 wherein a mean grain size of the second metal-containing material comprises a range from greater than or equal to approximately 5 nm to less than or equal to approximately 200 nm.

28. The memory cell of claim 6 wherein the first metal-containing material comprises a mean grain size less than or equal to approximately 10 nm.

29. The memory cell of claim 14 wherein a total thickness of the conductive gate comprises a range from about 5 nm to about 50 nm.

30. The memory cell of claim 14 wherein a mean grain size of the second metal-containing material comprises a range from greater than or equal to approximately 5 nm to less than or equal to approximately 200 nm.

31. The memory cell of claim 14 wherein the first metal-containing material comprises a mean grain size less than or equal to approximately 10 nm.

32. The memory cell of claim 1, wherein the first metal-containing material comprises a gradient interface with the second metal-containing material; the gradient interface comprising one of the following configurations: As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases, wherein a majority central portion of the second metalliferous material comprises only the second metalliferous material; or As the thickness of the second metalliferous material increases from the first metalliferous material, the percentage of the first metalliferous material decreases and the percentage of the second metalliferous material increases until reaching a peak at the center of the second metalliferous material.

33. The memory cell of claim 6 wherein the first metal-containing material and the second metal-containing material are the only two materials that form the conductive gate.

34. The memory cell of claim 33 wherein the first metal-containing material completely encapsulates the second metal-containing material.

35. The memory cell of claim 14 wherein the first metal-containing material and the second metal-containing material are the only two materials that form the conductive gate.

36. The memory cell of claim 35 wherein the first metal-containing material completely encapsulates the second metal-containing material.

Images