Silicon carbide power device JTE terminal structure and preparation method thereof

Abstract

The invention provides a silicon carbide power device JTE terminal structure and a preparation method thereof. A P-JTE region of the silicon carbide power device JTE terminal structure is arranged in an N-epitaxial layer in a step shape, and the left side of the P-JTE region is in contact with the right side surface of a P + region. According to the invention, the step-type multi-region JTE structure with unconventional charge gradient change is constructed, so that the surface JTE concentration is greatly reduced, and the JTE charges are enabled to present gradient change inside. The structure can effectively reduce the peak electric field on the surface of the device while ensuring a wide dose injection window, avoid extra electric leakage on the surface, reduce the risk of advanced breakdown on the surface of the device, and improve the reverse voltage withstanding reliability of the device. In addition, the required JTE structure can be realized by combining conventional injection and trajectory injection, the tedious steps of multiple epitaxy and injection in a conventional manufacturing method are avoided, and the process cost and period are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a JTE terminal structure of a silicon carbide power device and a preparation method thereof. Background Art

[0002] As energy and environmental issues are becoming more and more concerned by people, society has higher demands on the efficiency of power electronic systems and the performance of power semiconductor devices. To date, silicon-based power devices have been widely used in many fields. However, as silicon power devices are approaching maturity and the material properties of silicon materials themselves are limited, their device performance can no longer meet the growing demand for high-power applications. Compared with traditional silicon-based semiconductor materials, silicon carbide (SiC) materials are particularly suitable for the preparation of high-voltage and high-power power electronic devices due to their excellent properties such as large bandgap, strong critical breakdown electric field, and high thermal conductivity.

[0003] When preparing high-voltage SiC power devices, the junction terminal extension (JTE) terminal structure is often used to extend the main junction depletion region to alleviate the electric field concentration at the edge of the main junction, thereby improving and stabilizing the breakdown voltage. Compared with the field-limiting ring (FLRs) terminal, the JTE terminal has the advantages of simple preparation and high design size tolerance, and is widely used in the preparation of high-voltage, especially ultra-high-voltage SiC power devices. Generally, the single-concentration doped JTE (i.e., single-zone JTE) has a narrow doping dose window corresponding to a high breakdown voltage, which makes the device breakdown voltage extremely sensitive to the interference of the SiC / SiO2 interface charge. Therefore, designers often adopt the concept of multi-zone effect to construct a multi-zone JTE with a lateral charge gradient change to greatly increase the merit dose window and solve the problem of breakdown voltage transmutation caused by interface charge. However, since most JTE terminals are "surface-type terminals", that is, the depletion region terminates on the surface of the SiC material, the presence of a high surface electric field often leads to the degradation of the device breakdown characteristics and the poor withstand voltage stability of the device.

[0004] Therefore, it is urgent to conduct design optimization research on the JTE structure of silicon carbide power devices to ensure the stability of the reverse blocking characteristics of the device. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a JTE terminal structure of a silicon carbide power device and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a silicon carbide power device JTE terminal structure comprising: a substrate 1, an N-epitaxial layer 2, a P-JTE region 3, a P+ region 4, a passivation layer 5, an anode 6 and a cathode 7;

[0007] Among them, the N-epitaxial layer 2 is arranged on the substrate 1, the P+ region 4 is arranged on one side of the N-epitaxial layer 2, the anode 6 is arranged on the P+ region 4, the passivation layer 5 is arranged on the N-epitaxial layer 2, the anode 6 is arranged on the P+ region 4, the P-JTE region 3 is arranged in a step shape inside the N-epitaxial layer 2, and the left side is in contact with the right side surface of the P+ region 4, the right side is not in contact with the inner surface of the N-epitaxial layer 2, the upper surface is in contact with the lower surface of the passivation layer 5, and the cathode 7 is arranged on the reverse side of the substrate 1.

[0008] In a second aspect, the present invention provides a method for preparing a JTE terminal structure of a silicon carbide power device, comprising:

[0009] S100, obtaining a substrate 1, and growing an N-epitaxial layer 2 on the substrate 1;

[0010] S200, depositing and covering a silicon dioxide layer on the N-epitaxial layer 2, spin-coating a photoresist on the silicon dioxide layer, and then etching away the silicon dioxide at one end, and performing ion implantation from top to bottom into the N-epitaxial layer 2 in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2;

[0011] S300, regrowing silicon dioxide on the etched end to re-form a silicon dioxide layer, and spin-coating photoresist on both sides of the silicon dioxide layer, etching from top to bottom in the middle area until reaching the upper surface of the N-epitaxial layer 2, and performing multiple ion implantations with different energies from the upper surface to the N-epitaxial layer 2 from top to bottom to form a P-JTE region 3 with multiple steps;

[0012] Wherein, the injection junction depth of the P-JTE region 3 is greater than the injection junction depth of the P+ region 4;

[0013] S400, etching away the silicon dioxide layer, and forming a passivation layer 5 on the N-epitaxial layer 2, so that the passivation layer 5 covers a part of the P+ region 4 and the upper surface of the N-epitaxial layer 2;

[0014] S500 , covering the P+ region 4 with an anode metal to form an anode 6 , and covering the reverse side of the substrate 1 with a cathode metal to form a cathode 7 .

[0015] Beneficial effects:

[0016] 1. The present invention introduces the electric field concentration point into the N-epitaxial layer, effectively reducing the surface peak electric field in the terminal area of ​​the device, reducing the surface leakage of the device induced by the strong electric field under high reverse bias voltage, reducing the risk of premature breakdown of the device, and improving the reverse withstand voltage reliability of the device.

[0017] 2. The inverted JTE terminal structure adopted in the present invention can broaden the figure of merit dose window, enhance process robustness, and improve the stability of the reverse withstand voltage of the device.

[0018] 3. From the perspective of process manufacturing, the present invention can realize the required JTE structure by combining conventional implantation and ballistic implantation, avoiding the tedious steps of multiple epitaxy and implantation in conventional manufacturing methods, and reducing process costs and cycles.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of a JTE terminal structure of a silicon carbide power device provided by the present invention;

[0021] Figure 2a-2i It is a schematic diagram of the process of preparing the JTE terminal structure of a silicon carbide power device by adopting the first ion implantation method provided by the present invention;

[0022] Figure 2j-2l It is a schematic diagram of the process of preparing the JTE terminal structure of a silicon carbide power device by adopting the second ion implantation method provided by the present invention;

[0023] Figure 3 It is the AI ​​ion implantation concentration-implantation depth curve;

[0024] Figure 4 is a schematic diagram of surface electric field intensity-position;

[0025] Figure 5 This is a schematic diagram of breakdown voltage-JTE dose. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0027] refer to Figure 1 As shown, the present invention provides a silicon carbide power device JTE terminal structure including: a substrate 1, an N-epitaxial layer 2, a P-JTE region 3, a P+ region 4, a passivation layer 5, an anode 6 and a cathode 7;

[0028] Among them, the N-epitaxial layer 2 is arranged on the substrate 1, the P+ region 4 is arranged on one side of the N-epitaxial layer 2, the anode 6 is arranged on the P+ region 4, the passivation layer 5 is arranged on the N-epitaxial layer 2, the anode 6 is arranged on the P+ region 4, the P-JTE region 3 is arranged in a step shape inside the N-epitaxial layer 2, and the left side is in contact with the right side surface of the P+ region 4, the right side is not in contact with the inner surface of the N-epitaxial layer 2, the upper surface is in contact with the lower surface of the passivation layer 5, and the cathode 7 is arranged on the reverse side of the substrate 1.

[0029] The substrate 1 is a silicon carbide substrate, the doping type is N-type, and the doping element is nitrogen or phosphorus; the concentration of the N-epitaxial layer 2 is 5×10 13 cm-3 ~2×10 16 cm -3 , thickness 5 to 200 μm, doped with nitrogen or phosphorus. The number of steps in the P-JTE region 3 is n, and the value range of n is 2 to 10. The depth d1 of the first step JTE is in the range of 0.4 to 1.5 μm; the depth variation Δdi of the adjacent steps from the second step to the nth step is in the range of 0.1 to 0.6 μm. In each step of the P-JTE region 3, the doping concentration of JTE is 1×10 16 cm -3 ~1×10 18 cm -3 , the doping element is aluminum.

[0030] It is worth noting that the depth variation of adjacent steps can be a constant equal variation or a variable unequal variation.

[0031] Combination Figure 2a to Figure 2l The present invention provides a method for preparing a JTE terminal structure of a silicon carbide power device, comprising:

[0032] S100, obtaining a substrate 1, and growing an N-epitaxial layer 2 on the substrate 1;

[0033] S200, depositing and covering a silicon dioxide layer 103 on the N-epitaxial layer 2, and spin-coating a photoresist 104 on the silicon dioxide layer 103, then etching away the silicon dioxide at one end, and performing ion implantation from top to bottom into the N-epitaxial layer 2 in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2;

[0034] The present invention introduces an electric field concentration point into the N-epitaxial layer, effectively reducing the surface peak electric field in the device terminal region, reducing the surface leakage of the device induced by the strong electric field under high reverse bias voltage, reducing the risk of premature breakdown of the device, and improving the reverse withstand voltage reliability of the device.

[0035] S300, regrowing silicon dioxide on the etched end to re-form a silicon dioxide layer, and spin-coating photoresist on both sides of the silicon dioxide layer, etching from top to bottom in the middle area until reaching the upper surface of the N-epitaxial layer 2, and performing multiple ion implantations with different energies from the upper surface to the N-epitaxial layer 2 from top to bottom to form a P-JTE region 3 with multiple steps;

[0036] The P-JTE region 3 of the present invention is an inverted JTE terminal structure. The inverted JTE terminal structure can broaden the figure of merit dose window, enhance process robustness, and improve the reverse withstand voltage stability of the device. The dose range under the 3300V withstand voltage target reaches 1.4×10 13 cm -2 , which is 7 times that of single-zone JTE and 0.4×10 higher than the traditional three-stage JTE structure.13 cm -2 At the same time, a breakdown voltage closer to the ideal planar junction is obtained, and the maximum breakdown efficiency reaches 99%. It can be seen that the inverted JTE can better accommodate the breakdown voltage and process tolerance, and this structure is suitable for devices of any voltage level.

[0037] S400, etching away the silicon dioxide layer, and forming a passivation layer 5 on the N-epitaxial layer 2, so that the passivation layer 5 covers a part of the P+ region 4 and the upper surface of the N-epitaxial layer 2;

[0038] S500 , covering the P+ region 4 with an anode metal to form an anode 6 , and covering the reverse side of the substrate 1 with a cathode metal to form a cathode 7 .

[0039] The present invention combines ballistic ion implantation with conventional ion implantation to construct a stepped multi-zone JTE structure with an unconventional charge gradient change, which greatly reduces the surface JTE concentration and makes the JTE charge present a gradient change inside. This structure can effectively reduce the peak electric field on the device surface while ensuring a wide dose injection window, avoid additional leakage at the surface, reduce the risk of premature breakdown of the device on the surface, and improve the reverse withstand voltage reliability of the device. And from the perspective of process manufacturing, the present invention combines conventional implantation and ballistic implantation to achieve the desired JTE structure, avoiding the cumbersome steps of multiple epitaxy and implantation in conventional manufacturing methods, and reducing process costs and cycles.

[0040] In an optional implementation manner of the present invention, S200 includes:

[0041] S210, depositing a covering silicon dioxide layer 103 on the N-epitaxial layer 2, such as Figure 2a As shown;

[0042] S220, spin-coating the photoresist 104 on the silicon dioxide layer 103, such as Figure 2b As shown, the silicon dioxide at one end is etched away to form a first ion implantation mask layer as shown in FIG. Figure 2c As shown;

[0043] S230, Al ions are injected into the N-epitaxial layer 2 from top to bottom in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2, such as Figure 2d As shown; wherein the Al ion implantation energy is 10keV~800keV;

[0044] S240, cleaning out the first ion implantation mask layer.

[0045] In an optional implementation manner of the present invention, S300 includes:

[0046] S310, regrow silicon dioxide on the etched end to re-form the silicon dioxide layer 103;

[0047] S320, spin-coating photoresist 106 on both sides of the re-formed silicon dioxide layer 103, such as Figure 2e As shown, a second ion implantation mask layer is formed by photolithography and dry etching to open a hole and then etching from top to bottom in the middle area until the upper surface of the N-epitaxial layer 2 is reached, as shown in FIG. Figure 2f As shown, two ion implantation methods are used to perform multiple ion implantations with different energies from top to bottom into the N-epitaxial layer 2 in the middle etched area, thereby forming a P-JTE region 3 in the N-epitaxial layer 2 in which the JTE charge in the step changes from top to bottom or a P-JTE region 3 in which the JTE charge in the step changes from left to right.

[0048] In an optional embodiment of the present invention, the first ion implantation method in S320 includes:

[0049] S321a, Al ion implantation is performed on JTE 1 to 3 at an implantation angle of -4° and an energy of 500keV to 800keV to form the bottommost terminal region 107, such as Figure 2g As shown; cleaning and removing the second ion implantation mask layer;

[0050] S322a, prepare a third ion implantation mask layer on the surface of the N-epitaxial layer 2, and implant Al ions into the JTE 1-2 at an implantation angle of -4° and an energy of 300keV-500keV to form an intermediate layer terminal region 108, as shown in FIG. Figure 2h As shown;

[0051] S323a, cleaning and removing the third ion implantation mask layer, preparing a fourth ion implantation mask layer on the surface of the N-epitaxial layer 2, and implanting Al ions into the JTE 1 at an implantation tilt angle of -4°, an energy of 100keV to 300keV and an implantation tilt angle of 0°, an energy of 10keV to 100keV, respectively, to finally form the uppermost terminal region, such as Figure 2i As shown;

[0052] It is worth noting that an injection angle of -4° is ballistic injection, and an injection angle of 0° is conventional injection.

[0053] S324a, cleaning and removing the fourth ion implantation mask layer, and activating the implanted ions by high temperature annealing to form a P-JTE region 3 in the N-epitaxial layer 2, where the JTE charge in the step changes from top to bottom;

[0054] Among them, the bottom terminal region, the middle terminal region and the top terminal region form a P-JTE region 3 in which the JTE charge in the step changes from top to bottom.

[0055] In an optional embodiment of the present invention, the second ion implantation method in S320 includes:

[0056] S321b, four ion implantations are performed on the JTE 1 region using high, medium and low energies of 500keV to 800keV, 300keV to 500keV, 100keV to 300keV and 10keV to 100keV to form the leftmost terminal region 111, such as Figure 2j As shown; cleaning and removing the second ion implantation mask layer;

[0057] S322b, prepare a third ion implantation mask layer on the surface of the N-epitaxial layer 2, and then perform two ion implantations on the JTE 2 using medium and high energies of 500keV to 800keV and 300keV to 500keV to form an intermediate terminal region, such as Figure 2k As shown; cleaning and removing the third ion implantation mask layer;

[0058] S323b, prepare a fourth ion implantation mask layer on the surface of the N-epitaxial layer 2, and finally perform an ion implantation on the JTE 3 with a high energy of 500keV to 800keV to form the rightmost terminal region, such as Figure 2l As shown;

[0059] S324b, cleaning and removing the fourth ion implantation mask layer, and activating the implanted ions by high temperature annealing to form a P-JTE region 3 in the N-epitaxial layer 2, where the JTE charge in the step changes from left to right;

[0060] Among them, the leftmost terminal region, the middle terminal region and the rightmost terminal region form a P-JTE region 3 in which the JTE charge in the step changes from left to right.

[0061] It is worth noting that although the two ion implantation methods are different, the JTE charge on the steps in the formed P-JTE region 3 is the highest on the leftmost side from left to right, and is also the highest on the bottom layer from bottom to top, which makes the P-JTE region 3 of the present invention different from the existing structure and presents a structure with inverted JTE charge.

[0062] In an optional implementation manner of the present invention, S500 includes:

[0063] S510, depositing Ti, Ni or Al metal on the P+ region 4 by magnetron sputtering or electron beam evaporation to form an anode 6, and then performing rapid thermal annealing (RTA) to form an ohmic contact;

[0064] S520, depositing Ni metal on the reverse side of the substrate 1 by magnetron sputtering or electron beam evaporation to form a cathode 7, and then performing rapid thermal annealing (RTA) to form an ohmic contact.

[0065] The present invention provides a JTE terminal structure of a silicon carbide power device and a preparation method thereof. The JTE terminal structure of a silicon carbide power device includes: a substrate, an N-epitaxial layer, a P-JTE region, a P+ region, a passivation layer, an anode and a cathode; the P-JTE region is arranged in a step shape inside the N-epitaxial layer, and the left side contacts the right surface of the P+ region. The present invention greatly reduces the surface JTE concentration and makes the JTE charge present a gradient change inside by constructing a step-type multi-region JTE structure with an unconventional charge gradient change. The structure can effectively reduce the peak electric field on the surface of the device while ensuring a wide dose injection window, avoid additional leakage at the surface, reduce the risk of premature breakdown of the device on the surface, and improve the reverse withstand voltage reliability of the device. In addition, the present invention combines conventional injection and ballistic injection to achieve the desired JTE structure, avoiding the cumbersome steps of multiple epitaxy and injection in conventional manufacturing methods, and reducing process costs and cycles.

[0066] The advantages of the structure of the present invention are illustrated below through experimental results.

[0067] refer to Figure 3 , Figure 3 The doping concentration of JTE1 is 7.5×10 16 cm -3 , the doping concentration of JTE2 is 7.2×10 16 cm -3 , the doping concentration of JTE3 is 4.5×10 16 cm -3 AI ion implantation concentration-implantation depth curve. Figure 3 The vertical axis is the AI ​​ion implantation concentration, and the horizontal axis is the implantation depth. Figure 3 It can be seen that the structure of the present invention achieves a JTE structure opposite to the traditional three-order JTE through 4 groups of Al ion implantation with different energies / doses / tilt angles. At a maximum implantation energy of 700 keV, the Gaussian peak concentration position (i.e., the step edge) is 0.8 μm, and d1, d2, and d3 are 0.8, 0.4, and 0.2 microns, respectively.

[0068] refer to Figure 4 , Figure 4 is a schematic diagram of surface electric field strength and position. Figure 4 The horizontal axis is the electric field position, and the vertical axis is the surface electric field strength. Figure 4 From the surface electric field strength-position in the figure, it can be seen that compared with the traditional three-order JTE, the inverted JTE structure reduces the maximum surface peak electric field strength by 24%. The low surface electric field can avoid additional leakage at the surface, reduce the risk of hard breakdown of the device on the surface, and improve the breakdown application reliability of the device.

[0069] refer to Figure 5 , Figure 5This is a schematic diagram of breakdown voltage and JTE dose. Figure 5 The horizontal axis is the JTE dose, and the vertical axis is the breakdown voltage. Figure 5 It can be seen that the merit dose window of single-zone JTE is only about 0.2×10 13 cm -2 The proposed inverted JTE terminal structure can broaden the figure of merit dose window, and the dose range under the 3300V withstand voltage target reaches 1.4×10 13 cm -2 , which is 7 times that of single-zone JTE and 0.4×10 higher than the traditional three-stage JTE structure. 13 cm -2 It can be seen that the proposed inverted JTE structure is an effective termination technology that is compatible with breakdown voltage and process tolerance.

[0070] It is worth noting that the terms "first" and "second" in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0071] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0072] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A JTE terminal structure of a silicon carbide power device, characterized in that: include: Substrate (1), N-epitaxial layer (2), P-JTE region (3), P+ region (4), passivation layer (5), anode (6) and cathode (7); The N-epitaxial layer (2) is arranged on the substrate (1), the P+ region (4) is arranged on one side of the N-epitaxial layer (2), the anode (6) is arranged on the P+ region (4), the passivation layer (5) is arranged on the N-epitaxial layer (2), the anode (6) is arranged on the P+ region (4), the P-JTE region (3) is arranged in a step shape inside the N-epitaxial layer (2), and the left side is in contact with the right side surface of the P+ region (4), the right side is not in contact with the inner surface of the N-epitaxial layer (2), and the upper surface is in contact with the lower surface of the passivation layer (5), and the cathode (7) is arranged on the reverse side of the substrate (1).

2. The silicon carbide power device JTE terminal structure according to claim 1, characterized in that: The substrate (1) is a silicon carbide substrate, the doping type is N-type, and the doping element is nitrogen or phosphorus; the concentration of the N-epitaxial layer (2) is 5×10 13 cm -3 ~2×10 16 cm -3 , thickness 5 to 200um, and the doping elements are nitrogen or phosphorus.

3. The silicon carbide power device JTE terminal structure according to claim 1, characterized in that: The number of steps in the P-JTE region (3) is n, and the value range of n is 2 to 10. The depth d1 of the first step JTE is in the range of 0.4 to 1.5 μm. The depth variation Δdi of adjacent steps from the second step to the nth step is in the range of 0.1 to 0.6 μm.

4. The silicon carbide power device JTE terminal structure according to claim 1, characterized in that: In each step of the P-JTE region (3), the doping concentration of JTE is 1×10 16 cm -3 ~1×10 18 cm -3 , the doping element is aluminum.

5. A method for preparing a JTE terminal structure of a silicon carbide power device, characterized in that: include: S100, obtaining a substrate (1), and growing an N-epitaxial layer (2) on the substrate (1); S200, depositing a covering silicon dioxide layer on the N-epitaxial layer (2), spin-coating a photoresist on the silicon dioxide layer and then etching away the silicon dioxide at one end, and performing ion implantation from top to bottom into the N-epitaxial layer (2) in the etched area to form a P+ region (4) at one end of the N-epitaxial layer (2); S300, regrowing silicon dioxide on the etched end to re-form a silicon dioxide layer, spin-coating photoresist on both sides of the silicon dioxide layer, etching from top to bottom in the middle area until reaching the upper surface of the N-epitaxial layer (2), and performing multiple ion implantations with different energies from top to bottom into the N-epitaxial layer (2) from the upper surface to form a P-JTE region (3) with multiple steps; The injection junction depth of the P-JTE region (3) is greater than the injection junction depth of the P+ region (4); S400, etching away the silicon dioxide layer, and forming a passivation layer (5) on the N-epitaxial layer (2), so that the passivation layer (5) covers a part of the P+ region (4) and the upper surface of the N-epitaxial layer (2); S500, covering the P+ region (4) with an anode metal to form an anode (6) and covering the reverse side of the substrate (1) with a cathode metal to form a cathode (7).

6. The method for preparing the JTE terminal structure of a silicon carbide power device according to claim 5, characterized in that: S200 includes: S210, depositing a covering silicon dioxide layer on the N-epitaxial layer (2); S220, spin-coating a photoresist on the silicon dioxide layer and then etching away the silicon dioxide at one end to form a first ion implantation mask layer; S230, implanting Al ions into the N-epitaxial layer (2) from top to bottom in the etched area to form a P+ region (4) at one end of the N-epitaxial layer (2); wherein the Al ion implantation energy is 10 keV to 800 keV; S240, cleaning out the first ion implantation mask layer.

7. The method for preparing the JTE terminal structure of a silicon carbide power device according to claim 5, characterized in that: S300 includes: S310, regrowing silicon dioxide on the etched end to re-form a silicon dioxide layer S320, spin-coating photoresist on both sides of the newly formed silicon dioxide layer, then etching from top to bottom in the middle area until reaching the upper surface of the N-epitaxial layer (2) to form a second ion implantation mask layer; using two ion implantation methods to perform multiple ion implantations with different energies from top to bottom into the N-epitaxial layer (2) in the middle etched area, thereby forming a P-JTE region (3) in the N-epitaxial layer (2) in which the JTE charge in the step changes from top to bottom.

8. The method for preparing the JTE terminal structure of a silicon carbide power device according to claim 7, characterized in that: The first ion implantation method in S320 includes: S321a, performing Al ion implantation on JTE 1 to 3 at an implantation tilt angle of -4° and an energy of 500keV to 800keV to form a bottom terminal region; cleaning and removing the second ion implantation mask layer; S322a, preparing a third ion implantation mask layer on the surface of the N-epitaxial layer (2), and implanting Al ions into JTE 1-2 at an implantation tilt angle of -4° and an energy of 300keV-500keV to form an intermediate layer terminal region; S323a, cleaning and removing the third ion implantation mask layer, preparing a fourth ion implantation mask layer on the surface of the N-epitaxial layer (2), and implanting Al ions into JTE 1 at an implantation tilt angle of -4° and an energy of 100keV to 300keV and an implantation tilt angle of 0° and an energy of 10keV to 100keV, respectively, to finally form an uppermost terminal region; S324a, cleaning and removing the fourth ion implantation mask layer, and activating the implanted ions by high temperature annealing to form a P-JTE region (3) in the N-epitaxial layer (2) where the ion energy in the step changes from top to bottom; The bottommost terminal region, the middle terminal region and the topmost terminal region form a P-JTE region (3) in which the JTE charge in the step changes from top to bottom.

9. The method for preparing the JTE terminal structure of a silicon carbide power device according to claim 7, characterized in that: The second ion implantation method in S320 includes: S321b, four ion implantations are performed on the JTE 1 region using high, medium and low energies of 500keV to 800keV, 300keV to 500keV, 100keV to 300keV and 10keV to 100keV respectively to form a leftmost terminal region; the second ion implantation mask layer is cleaned and removed; S322b, preparing a third ion implantation mask layer on the surface of the N-epitaxial layer (2), and then performing two ion implantations on the JTE 2 using medium and high energies of 500keV to 800keV and 300keV to 500keV to form an intermediate terminal region; cleaning and removing the third ion implantation mask layer; S323b, preparing a fourth ion implantation mask layer on the surface of the N-epitaxial layer (2), and finally performing an ion implantation on JTE 3 with a high energy of 500keV to 800keV to form a rightmost terminal region; S324b, cleaning and removing the fourth ion implantation mask layer, and activating the implanted ions by high temperature annealing to form a P-JTE region (3) in the N-epitaxial layer (2) where JTE charges in the steps change from left to right; The leftmost terminal region, the middle terminal region and the rightmost terminal region form a P-JTE region (3) in which the JTE charge in the step changes from left to right.

10. The method for preparing a JTE terminal structure of a silicon carbide power device according to claim 5, characterized in that: S500 includes: S510, depositing Ti, Ni or Al metal on the P+ region (4) by magnetron sputtering or electron beam evaporation to form an anode (6), and then performing rapid thermal annealing (RTA) to form an ohmic contact; S520, depositing Ni metal on the reverse side of the substrate (1) by magnetron sputtering or electron beam evaporation to form a cathode (7), and then performing rapid thermal annealing (RTA) to form an ohmic contact.

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