SSD chiplet communication system and method

Abstract

The invention provides a communication system based on SSD (Solid State Disk) chiplet, which is applied to communication among core particles, and each core particle comprises a controller, a register and a memory, the core particle is a main body for sending and receiving data; the controller is responsible for sending the data of the core particles for sending the information to the ucie port, and the controller is responsible for receiving the data sent by the core particles at the opposite end from the ucie port. According to the invention, two transmission modes between the chips are defined, only a small amount of information and batch data are transmitted, and the transmission can be freely controlled through the controller, so that the transmission setting is simplified, and the transmission of different data volumes between the chips can be met.

Description

Technical Field

[0001] The present invention belongs to the field of solid-state hard disk storage, and more specifically relates to a chiplet communication method and a communication system for an SSD solid-state hard disk. Background Art

[0002] Traditional SOC design uses photolithography to make multiple modules responsible for different types of tasks on the same wafer, and then uses advanced processes for manufacturing. However, such a highly integrated approach will lead to a decrease in chip yield and an increase in the complexity and cost of chip design. If a large SOC is decomposed into multiple small chips according to different functions, and each small chip is manufactured according to a suitable manufacturing process, a similar modular design can be achieved. It is not necessary for all small chips to use advanced processes, which can reduce the complexity and cost of chip design. This patent uses chiplet technology to decompose large SOC designs into small chips, and uses ucie phy to design how the small chips should communicate.

[0003] Chiplet generally communicates with each other according to UCIE, but the current communication protocol is difficult to meet the different length requirements of data transmission between chips. Summary of the invention

[0004] The object of the present invention is to provide an SSD chiplet communication system and method that can realize two transmission modes: transmitting a small amount of information and transmitting batch data.

[0005] According to one aspect of the present invention, there is provided a communication system of an SSD chiplet, which is applied to communication between chiplets, wherein the chiplet includes a controller, a register, and a memory;

[0006] The core particle is the subject of sending and receiving data;

[0007] The controller is responsible for sending the data of the chiplet that sends information to the ucie port, and the controller is responsible for receiving the data sent by the chiplet at the opposite end from the ucie port.

[0008] In some embodiments, when the core particle is the subject of sending data, it is a sending core particle, and when the core particle is the subject of receiving data, it is a receiving core particle.

[0009] According to another aspect of the present invention, a communication method of a communication system based on an SSD chiplet is provided, wherein transmitting a small amount of information includes:

[0010] Send information: The sending chip initializes the clock and ucie port, sets the transmission mode to transmit information only, writes the information to be transmitted in the register of the sending chip, and then enables the start transmission to be transmitted to the receiving chip through the ucie port;

[0011] Receive information: The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit has received data, checks the transmission mode, checks whether the information has been transmitted to the register of the receiving chip, and extracts the information from the register if the transmission is complete.

[0012] According to another aspect of the present invention, a communication method of a communication system based on an SSD chiplet is provided, wherein a large amount of information is transmitted, including:

[0013] Send information: The sending chip initializes the clock and ucie port, sets the transmission mode to batch data transmission, writes the information to be transmitted in the register and memory of the sending chip, and sets the data length according to the amount of data to be transmitted, and then enables the start transmission to be transmitted to the receiving chip through the ucie port;

[0014] Receive information: The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit has received data, checks the transmission mode, if the transmission mode is batch data, checks whether the information has been transmitted to the memory of the receiving chip, if the transmission is completed, extracts the transmitted data length from the register of the receiving chip, and fetches the data of the corresponding length from the memory.

[0015] In some implementations, after the receiving core particle extracts the data, it clears the data valid bit.

[0016] In some embodiments, if the data valid bit indicates that no data has been received, the data valid bit continues to be checked until the data valid bit indicates that data has been received.

[0017] The beneficial effects are as follows: the present invention defines a transmission mode between two chips, which transmits only a small amount of information and a batch of data, and can be freely controlled by a controller, which simplifies the transmission setting and can also meet the transmission of different data amounts between core chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a communication system of an SSD chiplet according to an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of sending data of a communication method of an SSD chiplet according to an embodiment of the present invention;

[0020] Figure 3A schematic diagram of receiving data in a communication method of an SSD chiplet according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] Figure 1-Figure 3 The schematic diagram takes the communication between the first chip0 and the second chip1 as an example, where the first chip0 is a sending chip that sends data information and the second chip1 is a receiving chip that receives data information. In practical applications, the communication method can be applied to communication between various chiplets, and is not limited to communication between chiplets in SSDs.

[0023] Figure 1 The figure schematically shows a communication system of an SSD chiplet. Figure 1 As shown, the first chip chip0 includes a first controller 11, a first memory 12, a first register 13 and a ucie port. The second chip chip1 includes a second controller 21, a second memory 22, a second register 23 and a ucie port. The data transmission between the first chip chip0 and the second chip chip1 is handled by the ucie port. The first chip chip0 is the main body for sending and receiving data. The first controller 11 is responsible for sending the data of the first chip chip0 to the ucie port or receiving the data sent by the second chip chip1 from the ucie port. The second chip chip1 is the main body for sending and receiving data. The second controller 21 is responsible for sending the data of the second chip chip1 to the ucie port or receiving the data sent by the first chip chip0 from the ucie port.

[0024] The present invention has two transmission modes, one is to transmit only a small amount of information, and the other is to transmit a large amount of data. When transmitting a small amount of information: the first controller 11 of the first chip0 writes the data to be transmitted into the first register 13, and then transmits it to the second chip1 communicating with it through the ucie port; the second chip1 obtains the valid flag of the transmission data from the second controller 21, and then obtains data from the corresponding position according to the valid flag. When transmitting a large amount of data: the controller 11 of the first chip0 writes the data to be transmitted into the first register 13 and the first memory 12 of the first chip0, and the first controller 11 of the first chip0 sends the data to the second chip1 through the ucie port according to the set transmission mode, and the second chip1 obtains the valid flag of the transmission data from the controller 21, and then obtains data from the corresponding position according to the valid flag.

[0025] Ways to transmit small amounts of information such as Figure 2 The sending chip Chip0 initializes the clock and ucie port, sets the sending mode to transmit information only, writes the information to be transmitted to the corresponding register, and then enables the start transmission to transmit to the receiving chip chip1 through the ucie port. The way to receive a small amount of information is as follows Figure 3 As shown. The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit indicates that no data has been received, then continue to check the data valid bit, if the data valid bit indicates that data has been received, then check whether the transmission mode is a small amount of information or a large amount of data, if a small amount of information is received, then check whether the information has been transmitted to the register corresponding to the current chip, if the transmission has been completed, extract the information in the corresponding register, and then clear the data valid bit. Specifically, take the example that the first chip chip0 transmits a small amount of information to the second chip chip1, and the second chip chip1 receives a small amount of information. The first controller 11 of the first chip chip0 initializes the clock and ucie port, the first controller 11 of the first chip chip0 sets the sending mode to transmit information only, and writes the information to be transmitted to the first register 13 of the first chip chip0, and then enables the start of transmission to be transmitted to the second chip chip1 through the ucie port. The second chip chip1 initializes the clock and ucie port, and the second controller 21 of the second chip chip1 checks whether the data valid bit has received data. If the data valid bit indicates that no data has been received, the data valid bit continues to be checked. If the data valid bit indicates that data has been received, the transmission mode continues to be checked to see whether a small amount of information or a large amount of data has been received. If a small amount of information is received, the receiving mode is set to only transmit information, and it is checked whether the information to be transmitted has been transmitted to the second second register 23 of the second chip chip1. If the transmission has been completed, the information is extracted from the second register 23 of the second chip chip1, and then the data valid bit is cleared.

[0026] The method of transmitting a large amount of information is shown in the attached figure Figure 2 The sending chip initializes the clock and ucie port, sets the transmission mode to transmit batch data, writes the information to be transmitted to the corresponding register and memory, sets the data length according to the amount of data to be transmitted, and then enables the start transmission to transmit to the receiving chip through the ucie port. The method of receiving a large amount of information is shown in the figure. Figure 3As shown. The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit indicates that no data has been received, then continue to check the data valid bit, if the data valid bit indicates that data has been received, then check whether the transmission mode is to receive a small amount of information or a large amount of data, if a large amount of data is received, then check whether the data has been transmitted to the memory of the receiving chip, if the transmission has been completed, extract the length of the transmitted data in the corresponding register, then take the data of the corresponding length in the memory, and finally clear the data valid bit to prepare for the next data reception. Specifically, take the first chip0 transmitting a large amount of information to the second chip1, and the second chip1 receiving a large amount of information as an example. The first controller 11 of the first chip0 initializes the clock and ucie port, sets the sending mode to send batch data and information, writes the data and information to be transmitted to the first register 13 and the first memory 12, sets the data length according to the amount of data to be transmitted, and then enables the start of transmission to be transmitted to the second chip1 through the ucie port. The second controller 21 of the second chip chip1 initializes the clock and ucie port, checks whether the data valid bit has been received, and if the data valid bit indicates that no data has been received, continues to check the data valid bit, and if the data valid bit indicates that data has been received, checks whether the receiving mode is to receive a small amount of information or a large amount of data, and if a large amount of data is received, checks whether the data has been transmitted to the second memory 22 of the second chip chip1, and if the transmission has been completed, extracts the length of the transmitted data in the second register 23, and then obtains the data of the corresponding length in the second memory 22, and finally clears the data valid bit to prepare for the next data reception.

[0027] The above are only some embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, but not to limit them. For those skilled in the art, without departing from the creative concept of the present invention, the technical solutions recorded in the above embodiments are modified, or some or all of the technical features are replaced by equivalents, which all belong to the protection scope of the present invention.

Claims

1. A communication system based on SSD chiplet, characterized in that: Applied to communication between core particles, the core particles including controller, register and memory; The core particle is the subject of sending and receiving data; The controller is responsible for sending the data of the chiplet that sends information to the ucie port, and the controller is responsible for receiving the data sent by the chiplet at the opposite end from the ucie port.

2. The communication system based on SSD chiplet according to claim 1, characterized in that: When the core particle is the subject of sending data, it is a sending core particle, and when the core particle is the subject of receiving data, it is a receiving core particle.

3. A communication method of the communication system based on the SSD chiplet according to claim 2, characterized in that: Transmitting small amounts of information including, Send information: The sending chip initializes the clock and ucie port, sets the transmission mode to transmit information only, writes the information to be transmitted in the register of the sending chip, and then enables the start transmission to be transmitted to the receiving chip through the ucie port; Receive information: The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit has received data, checks the transmission mode, checks whether the information has been transmitted to the register of the receiving chip, and extracts the information from the register if the transmission is complete.

4. A communication method of the communication system based on the SSD chiplet according to claim 1, characterized in that: Transmitting large amounts of information including, Send information: The sending chip initializes the clock and ucie port, sets the transmission mode to batch data transmission, writes the information to be transmitted in the register and memory of the sending chip, and sets the data length according to the amount of data to be transmitted, and then enables the start transmission to be transmitted to the receiving chip through the ucie port; Receive information: The receiving chip initializes the clock and ucie port, checks whether the data valid bit has received data, if the data valid bit has received data, checks the transmission mode, if the transmission mode is batch data, checks whether the information has been transmitted to the memory of the receiving chip, if the transmission is completed, extracts the transmitted data length from the register of the receiving chip, and fetches the data of the corresponding length from the memory.

5. The SSD chiplet communication method according to claim 3 or 4, characterized in that: After extracting the data, the receiving core clears the data valid bit.

6. The SSD chiplet communication method according to claim 4, characterized in that: If the data valid bit indicates that no data has been received, the data valid bit continues to be checked until the data valid bit indicates that data has been received.

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