Method of operating phase change memory, corresponding apparatus and computer program product

Abstract

Embodiments of the present disclosure relate to a method of operating a phase change memory, a corresponding apparatus, and a computer program product. A phase change memory (PCM) device includes a set of cells into which binary logic levels are written by a write operation. Each unit is included in a respective one of the sets of units. The write operation includes performing a write verification operation on the cell to identify an actual logic level stored in the cell; checking whether the identified actual logic level is matched with a certain binary logic level or not; in response to the checking determining that the actual logic level does not match the binary logic level in the at least one cell, the actual logic level is corrected to match the binary logic level by setting a write operation, if the binary logic level is a high logic level, or resetting the write operation, and if the binary logic level is a low logic level, correcting the actual logic level to match the binary logic level. When the binary logic level is a low logic level.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000014754, filed on July 14, 2023, the contents of which are hereby incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Describes the field involving data storage technology.

[0004] One or more embodiments may be applied to computer storage technologies such as phase change memory (PCM), for example embedded phase change memory (ePCM) and / or non-volatile memory ePCM (ePCM NVM). Background Art

[0005] Phase change memory (PCM) is a type of computer storage technology, ie, memory technology, and is typically a type of non-volatile random access memory technology that may be embedded in an integrated circuit (IC) semiconductor device.

[0006] Typically, PCMs operate on a bit-by-bit basis in that heat generated by an electric current flowing through a heated material called a phase change material (such as, for example, chalcogenide glass) is used to melt and quench the phase change material, rendering it amorphous, or to maintain such a phase change material within its crystallization temperature range, thereby switching it to a crystalline state.

[0007] Thus, a PCM memory cell can use such a phase change material to store 1 bit of information because the two states of the phase change material (i.e., amorphous or crystalline) are characterized by different resistance values ​​that facilitate distinguishing one state from the other, i.e., each of the two states corresponds to a different value of a single bit.

[0008] Therefore, the phase change material can be stably in two states: an amorphous or disordered state, which is characterized by a high resistivity, i.e., by a high resistance of, for example, about 0.6 MΩ, which represents, for example, a low logic state (e.g., "0"), which is characterized by a low current flowing through the phase change material; or a crystalline or ordered state, which is characterized by a low resistivity, i.e., by a low resistance (e.g., a resistance lower than that of the amorphous state, e.g., about 18 kΩ), which represents, for example, a high logic state (e.g., "1"), which is characterized by a high current flowing through the phase change material.

[0009] A PCM memory cell can be switched between such two states by heating the phase change material differently, i.e., by applying a current to such phase change material for a given time for switching to the first state, and by applying currents of different values ​​to such phase change material for different times for switching to the second state.

[0010] For example, a “set” write operation for a particular cell, i.e., setting the cell to a high logic level, may be performed by applying an electric current to the phase change material of such particular cell for a given time, the electric current heating the corresponding phase change material to above the crystallization temperature associated with such corresponding phase change material, but below the melting temperature associated with the same phase change material.

[0011] For example, a “reset” write operation for a particular cell, i.e., setting the cell to a low logic level, can be performed by applying a current to the phase change material of such particular cell for a given time, e.g., shorter than the given time considered in the “set” write operation, the current heating the corresponding phase change material to above the melting temperature associated with such corresponding phase change material.

[0012] For example, a read operation of a particular cell may be performed by testing the resistance value of the phase change material of the particular cell (eg, via a current pulse) to detect the current phase of the phase change material, ie, amorphous or crystalline.

[0013] Note that “set” write operations and “reset” write operations will be collectively referred to as write operations in the following description, and thus, the write operation performed on a given cell may be a set write operation, i.e., setting such a given cell to a high logic level, or a reset write operation, i.e., setting such a given cell to a low logic level.

[0014] Note that after any write operation, a write verification operation is usually performed, i.e., a read operation is used to check the success of the corresponding write operation. If the write verification operation is deemed successful, i.e., if the read operation used to check the success of the corresponding write operation is deemed successful, that is, if the read operation detects that the cell associated with such corresponding write operation contains the correct value that should be written in such cell, then the corresponding write operation will end with the value contained in the cell being correct, and therefore, the write operation is successful. On the other hand, if the write verification operation is deemed unsuccessful, i.e., if the read operation detects that the cell associated with such corresponding write operation contains a value different from the correct value that should be written in such cell, then the write operation will be applied again, i.e., the current is applied to the cell again to repeat the write operation.

[0015] Single-ended PCM is a type of PCM in which a single cell corresponds to a single bit (i.e., 1 cell / bit). A read operation in single-ended PCM is performed by using a reference current, which is supplied, for example, by a reference current generator, and a sense amplifier receives a current from the PCM cell to be read at one terminal and receives a reference current supplied by the reference current generator at another terminal.

[0016] U.S. Patent Application Publication No. 2009 / 0161417A1, incorporated by reference, discloses a two-cell-per-bit (i.e., 2 cells / bit) PCM architecture, i.e., a PCM architecture in which two cells contain a single data bit, and one of the two cells (the complementary cell) is programmed to a complementary state of the other of the two cells. Thus, a bit is determined by reading a bit stored in one of the two cells and comparing it to a bit stored in the complementary cell, thereby performing a differential read operation.

[0017] The differential read operation takes into account both the value of such data stored in the cell in its direct form, i.e., a high logic level or a low logic level, respectively, and the value of such data stored in the complementary cell in its complementary form, i.e., a low logic level or a high logic level, respectively, and the result of the differential read operation is obtained by using a sense amplifier configured to receive at one terminal the current of the “direct” cell that has to be read, i.e., containing the data in direct form, and at the other terminal the current of the associated complementary cell, i.e., containing the data in complementary form.

[0018] Therefore, the sense amplifier is configured to compare the current received from the direct cell with the current received from the associated complementary cell. If the current received from the direct cell is higher than the current received from the associated complementary cell, the sense amplifier is configured to read a logic level equal to 1 ("1"), i.e., a high logic level. Otherwise, if the current received from the direct cell is lower than the current received from the associated complementary cell, the sense amplifier is configured to read a logic level equal to 0 ("0"), i.e., a low logic level.

[0019] Therefore, a read operation of a bit in a two-cell-per-bit PCM may be more reliable than a read operation of a bit in a single-ended PCM because the read window in the two-cell-per-bit PCM is twice as wide as the read window used in the single-ended PCM.

[0020] The read window in a two-cell PCM per bit depends on the difference between the current flowing in the direct cell and the current flowing in the associated complementary cell, the difference corresponding to the difference between the current flowing in a cell set to a high logic level (i.e., the current flowing in the direct cell or the complementary cell) and the current flowing in a cell set to a low logic level (i.e., the current flowing in the complementary cell or the direct cell, respectively).

[0021] In contrast, the read window in single-ended PCM depends on the difference between the current flowing in the cell (i.e., the current flowing within a cell set to a high logic level or a low logic level) and a reference current, such that the reference current is between the current flowing within a cell set to a high logic level and the current flowing within a cell set to a low logic level.

[0022] Therefore, the two-cell-per-bit PCM architecture improves the reliability of the read operation because no reference current is required because the read operation is based on differential reading and because the read window of the two-cell-per-bit is doubled.

[0023] Furthermore, a two-cell-per-bit PCM architecture will typically provide higher robustness, reliability, and retention than a single-ended PCM architecture, since two-cell-per-bit PCM is characterized by: information redundancy, i.e., a single bit is stored in two cells instead of a single cell; and the possibility of implementing a differential read strategy, i.e., allowing the contents of a cell to be read without using a reference current.

[0024] Such a differential reading strategy also allows avoiding problems related to relaxation phenomena affecting the amorphous material of the PCM cell, which renders it impractical to choose a constant reference current over the entire operating life of a single-ended PCM cell.

[0025] Figure 1 A conventional structure of a PCM array 10 with two cells per bit is shown.

[0026] The PCM array 10, for example, a two-cell-per-bit PCM array or a single-ended PCM array, includes a collection of cells, for example, including Figure 1 The units coupled together are 100 i-1,j , 100 i,j , 100 i+1,j and 100 i+2,j , Unit 100 i-1,j , 100 i,j , 100 i+1,j and 100 i+2,j They are collectively referred to as reference numeral 100 .

[0027] Notice, Figure 1 The resistor in is not a physical component but is caused by parasitic connections.

[0028] Figure 1 The set of cells 100 shown is included in word line WL j , and each of such cells 100 is also coupled to a corresponding bit line, for example, Figure 1 The bit line BL i-1 BL i BL i+1 or BL i+2 , bit line BL i-1 BL i BL i+1 or BL i+2 They are collectively referred to as BL.

[0029] Both the current received from the direct cell and the current received from the associated complementary cell depend on the voltages applied across the direct cell and the complementary cell, respectively.

[0030] Such voltages applied on the direct cells and complementary cells cannot be precisely defined in advance, because such voltages: are parts of the higher voltages applied on the corresponding bit lines BL (i.e., the bit lines to which such direct cells and complementary cells are coupled); and depend on the number of cells read in parallel in the same tile (i.e., the number of cells along the bit lines BL and word lines WL). j The same part of a PCM memory placed at the same time) and the current flowing within each cell.

[0031] The number of cells in the same tile that are read simultaneously in parallel changes the value of the voltage applied to each of such cells, thereby changing the value of the current flowing within each of such cells.

[0032] Such changes in the values ​​of voltage and current are due to the following factors: a low value of the β parameter, for example about 0.45, i.e., indicating the relationship between the collector current (output current) and the base current (input current) of a bipolar transistor used as a selector for a cell in a PCM memory; and a word line IR drop, i.e., a voltage drop caused by a current flowing through a parasitic resistor.

[0033] A solution that reduces current variations within the cell is therefore desirable in order to facilitate write verify operations, ie operations that check the success of a write operation.

[0034] There is a need in the art to contribute to providing such a solution. Summary of the invention

[0035] One or more embodiments are directed to methods for performing a PCM write operation.

[0036] One or more embodiments relate to corresponding memory devices and corresponding computer program products, which can be loaded into at least one processing circuit (e.g., a computer) and include software code portions for performing the steps of the method when the product is run on at least one processing circuit. As used herein, reference to such a computer program product is understood to be equivalent to reference to a computer-readable medium containing instructions for controlling a processing system to coordinate the implementation of the method according to one or more embodiments.

[0037] The solution described herein includes a method for performing a PCM write operation, i.e., writing a word comprising one or more bits in a phase change memory (PCM) device, the PCM write operation including a write verify operation, the PCM device including multiple groups ("sets") of cells, the cells being configured to be written therein in response to a write operation, e.g., a set write operation or a reset write operation, a binary logic level being selected from a high logic level and a low logic level, wherein each cell is included in a corresponding group ("set") of cells in the multiple groups ("sets") of cells.

[0038] An embodiment of the method described herein includes at least the following steps: performing a write verification operation on cells in such multiple groups ("sets") of cells, the write verification operation being configured to provide a result indicating an actual logic level stored in the cells in such multiple groups ("sets"), wherein the write verification operation is performed on each cell using a set of parameters, the set of parameters being selected based on a corresponding group ("set") of cells that includes the cell; based on the result of such write verification operation, checking whether the actual logic level stored in the cells in such multiple groups ("sets") matches such a binary logic level; and in response to such checking determining that in at least one cell in such multiple groups ("sets") the actual logic level does not match such a binary logic level, correcting such actual logic level to match such a binary logic level by: performing a set write operation when the binary logic level is a high logic level, or performing a reset write operation when the binary logic level is a low logic level.

[0039] The solutions described herein help reduce current variations within a cell to facilitate a write verify operation, ie, an operation to check the success of a write operation, thereby enabling a write operation with increased performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings:

[0041] Figure 1 It is the conventional structure of PCM array;

[0042] Figure 2A and Figure 2B The subsequent reset current pulse and set current pulse are illustrated respectively;

[0043] Figure 3 is a flow chart of a method for performing a write operation including a write verify operation; and

[0044] Figure 4 and Figure 5 is a flow chart of a method for performing a write operation including a write verify operation according to an embodiment of the present description. DETAILED DESCRIPTION

[0045] Corresponding reference numerals in the different figures generally refer to corresponding parts unless otherwise indicated.

[0046] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0047] The edges of features drawn in the diagram do not necessarily indicate the end of the feature's extent.

[0048] In the following description, one or more specific details are illustrated to provide a deeper understanding of the described embodiments. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of such embodiments are not obscured.

[0049] Reference to "embodiment" or "one embodiment" in the framework of this description is intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" may appear in one or more points of this description and do not necessarily refer to the same embodiment.

[0050] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] The headings / reference numbers used herein are provided for convenience only, and therefore do not limit the scope of protection or the scope of the embodiments.

[0052] For simplicity and ease of explanation, throughout this description and unless the context dictates otherwise, the same reference numerals are used in the various figures to refer to the same parts or elements, and the corresponding description will not be repeated for each figure.

[0053] As mentioned previously, the solution disclosed herein aims to reduce the current variation within the cells of a two-cell-per-bit PCM to facilitate a write-verify operation, ie, an operation to check the success of a write operation.

[0054] Note that in a two-cell-per-bit PCM, the effect of the word line IR drop, i.e., the effect of the voltage drop caused by the current flowing through the parasitic resistor, during a read operation is approximately constant, given that if the number of sense amplifiers in a given tile is equal to the number N, the number of cells storing a high logic level (i.e., corresponding to a high current flowing within such cells) that are read in parallel and the number of cells storing a low logic level (i.e., corresponding to a low current flowing within such cells) that are read in parallel is equal to such number N (i.e., each sense amplifier corresponds to a cell storing a high logic level, e.g., a direct or complementary cell, and a cell storing a low logic level, e.g., a complementary cell or a direct cell, respectively).

[0055] However, such effect of word line IR drop varies between different write verification operations because such effect depends on the state of the cell during the execution of the write verification operation, for example, resulting in reduced accuracy of the cycle of write verification operations, where each of such write verification operations is affected by a different contribution of such word line IR drop.

[0056] A write operation in a two-cell-per-bit PCM may include at least two phases, which may be performed in any order and repeated any number of times: a verification phase, in which the current flowing in each cell participating in the write operation is compared with one or more reference currents to determine whether each of such cells must receive a write current pulse; and a set and reset pulse phase, in which each cell participating in the write operation and being in a state different from the desired state receives one or more set or reset pulses.

[0057] The verification phase can include one or more of the following sub-phases:

[0058] - a direct cell setting verification subphase, in which each current flowing in the direct cells to be set to a high logic level is compared with a direct setting verification reference current (e.g., having a value of about 8 μA (micro)) to check whether each direct cell to be set to a high logic level is correctly set to such a logic level, i.e., to check whether the current flowing in each direct cell to be set to a high logic level is higher than such direct setting verification reference current, e.g., Icell>8 μA, where Icell is the current flowing in each of such direct cells;

[0059] - a complementary cell setting verification subphase, in which each current flowing in the complementary cell to be set to a high logic level is compared with a complementary setting verification reference current, for example, the value of the complementary setting verification reference current is equal to the direct setting verification reference current (i.e., about 8 μA), to check whether each complementary cell to be set to a high logic level is correctly set to such a logic level, i.e., to check whether the current flowing in each complementary cell to be set to a high logic level is higher than such complementary setting verification reference current, for example, Icell>8 μA;

[0060] a direct cell reset verification subphase, in which each current flowing in the direct cell to be set to a low logic level is compared with a direct reset verification reference current (e.g., having a value of about 4 μA) to check whether each direct cell to be set to a low logic level is correctly set to such a logic level, i.e., to check whether the current flowing in each direct cell to be set to a low logic level is lower than such direct reset verification reference current, e.g., Icell<4 μA; and

[0061] - A complementary cell reset verification sub-phase, in which each current flowing in a complementary cell to be set to a low logic level is compared with a complementary reset verification reference current, the value of the complementary reset verification reference current being, for example, equal to the direct reset verification reference current (i.e., approximately 4 μA), to check whether each complementary cell to be set to a low logic level is correctly set to such a logic level, i.e., to check whether the current flowing in each complementary cell to be set to a low logic level is lower than such complementary reset verification reference current, for example, Icell<4 μA.

[0062] In summary, each such verification sub-phase is performed using a set of parameters (e.g., selected according to the verification sub-phase currently being executed), the set of parameters including: a reference current for comparison with the current flowing through the cell undergoing the write verification operation; and the direction of the inequality applied in such comparison.

[0063] Thus, the verification phase may include: a first write verification operation, for example, by checking whether such a current flowing through the cell undergoing the first write verification operation is higher than such a first reference current, performing a write verification operation in a direct cell setting verification subphase and a complementary cell setting verification subphase performed on a first cell (for example, a direct cell and a complementary cell among such multiple cells that will be set to a high logic level using a first reference current (for example, a direct setting verification reference current or a complementary setting verification reference current)) in a first direction of the inequality, wherein in response to the current flowing through the cell undergoing the first write verification operation being higher than the first reference current, an actual logic level stored in a first cell among such multiple cells is maintained to match such a binary logic level (i.e., a high logic level).

[0064] In addition to or alternatively to the first write verification operation, the verification phase may include: a second write verification operation, for example, by checking whether the current flowing through the cell undergoing the second write verification operation is lower than such a second reference current, in a second direction of the inequality, a direct cell reset verification subphase and a complementary cell reset verification subphase performed on a second cell (for example, a direct cell and a complementary cell that will be set to a low logic level using a second reference current (for example, a direct reset verification reference current or a complementary reset verification reference current) among such multiple cells), wherein in response to the current flowing through the cell undergoing the second write verification operation being lower than the second reference current, the actual logic level stored in a second cell among such multiple cells is maintained to match such a binary logic level (i.e., a low logic level).

[0065] In various embodiments, such first reference current is higher than such second reference current.

[0066] The set and reset pulse phases may include one or more of the following sub-phases:

[0067] -Direct unit setting pulse sub-phase, where a triangular shaped setting pulse, e.g. Figure 2B PS1, PS2 or PS3 in is applied to each direct cell that is to be set to a high logic level and has not passed the corresponding direct cell set verification sub-phase;

[0068] -Complementary unit setup pulse sub-phase, where a triangular shaped setup pulse, e.g. Figure 2B PS1, PS2 or PS3 in is applied to each complementary cell that is to be set to a high logic level and has not passed the corresponding complementary cell set verification sub-phase;

[0069] -Direct cell reset pulse subphase, where a rectangular shaped reset pulse, e.g. Figure 2APR1, PR2 or PR3 of , is applied to each direct cell that is to be set to a low logic level and has not passed the corresponding direct cell reset verification sub-phase; and

[0070] -Complementary cell reset pulse subphase, where a rectangular shaped reset pulse, e.g. Figure 2A PR1, PR2 or PR3 is applied to each complementary cell that is to be set to a low logic level and has not passed the corresponding complementary cell reset verification subphase.

[0071] Figure 2A and Figure 2B The subsequent current pulses of resetting PR1 , PR2 and PR3 (collectively referred to as reference numeral PR) and setting PS1 , PS2 and PS3 (collectively referred to as reference numeral PS) are illustrated respectively.

[0072] Figure 2A The diagram illustrates a sequence of reset current pulses PR used for a reset write operation, the sequence of reset current pulses PR comprising at least:

[0073] - a first reset pulse PR1, for example, the first reset pulse PR1 has a rectangular shape, a value of about 240 μA, and lasts for about 0.1 μs, and is used in the first reset pulse sub-phase if the previous first reset verification sub-phase fails,

[0074] a second reset pulse PR2, for example, having a rectangular shape, a value of about 270 μA and a duration of about 0.1 μs, which is used in the second reset pulse subphase if the previous second reset verification subphase failed, i.e., if the first reset pulse subphase is deemed to have failed; and

[0075] - A third reset pulse PR3, for example, having a rectangular shape, a value of about 300 μA and a duration of about 0.1 μs, is used in the third reset pulse subphase if the previous third reset verification subphase fails, i.e., if the second reset pulse subphase is deemed to have failed.

[0076] Figure 2B The diagram illustrates a sequence of setting current pulses PS used for setting a write operation, the sequence of setting current pulses PS comprising at least:

[0077] - A first setting pulse PS1, e.g. Figure 2BAs shown, the first setting pulse PS1 includes a first rectangular shape, for example, a maximum value of about 160 μA and a duration of about 0.2 μs, and includes a second triangular shape, for example, the second triangular shape decreases from the maximum value and has a slope of about 0.045 μA / ns and a duration of about 3.5 μs. If the previous first setting verification sub-stage fails, the first setting pulse PS1 is used in the first setting pulse sub-stage;

[0078] - A second setting pulse PS2, e.g. Figure 2B As shown, the second setting pulse PS2 includes a first rectangular shape, for example, a maximum value of about 230 μA and a duration of about 0.2 μs, and includes a second triangular shape, for example, the second triangular shape decreases from the maximum value and has a slope of about 0.045 μA / ns and a duration of about 5 μs, if the previous second setting verification sub-stage fails, that is, if the first setting pulse sub-stage is deemed to have failed, then the second setting pulse PS2 is used for the second setting pulse sub-stage; and

[0079] - The third setting pulse PS3, for example, Figure 2B As shown, the third setting pulse PS3 includes a first rectangular shape, for example, a maximum value of about 260 μA and a duration of about 0.2 μs, and includes a second triangular shape, for example, the second triangular shape decreases from the maximum value and has a slope of about 0.045 μA / ns and lasts for about 5.7 μs. If the previous third setting verification substage fails, that is, if the second setting pulse substage is deemed to have failed, the third setting pulse PS3 is used for the third setting pulse substage.

[0080] Therefore, a write operation (e.g., a set write operation or a reset write operation) performed after a previously failed write operation (e.g., a failed set write operation or a failed reset write operation, respectively) is performed using a current pulse of increased value (e.g., a set PS current pulse or a reset PR current pulse, respectively) to reduce the probability of additional failed write operations.

[0081] Notice, Figure 2A and Figure 2B The reset / set current pulses illustrated in the figure are shown only as examples, and therefore: a smaller number of current pulses may be considered, for example, a single current pulse or pairs of current pulses, or a larger number of current pulses may be used, for example, additional current pulses, for example, if the previous four reset / set verification sub-stages fail, that is, if the third reset / set pulse sub-stage is deemed to have failed, then a fourth reset / set pulse sub-stage is performed; for each reset / set current pulse, different current (μA) and time (μs) values ​​may be considered; and / or for each reset / set current pulse, different shapes may be considered.

[0082] During the verification phase of a write operation, the sense amplifier compares the current flowing within the cell to a fixed reference current (i.e., a direct set verification reference current, a complementary set verification reference current, a direct reset verification reference current, or a complementary reset verification reference current), the value of the reference current depending on the currently executed sub-phase of such verification phase.

[0083] During any sub-phase of the verification phase, the side of the sense amplifier receiving the fixed reference current is coupled to the main bit line MBL and the local bit line BL, which is placed in a PCM sector symmetrical with respect to the addressed sector, the PCM sector including the cell currently considered for the verification phase of the write operation. In this way, the load capacitance is balanced.

[0084] Furthermore, during a verify phase of a write operation: both the direct cell and the corresponding complementary cell are pre-charged prior to a sense phase; and only one of the direct cell and the corresponding complementary cell is coupled to a terminal of a sense amplifier.

[0085] Note that the write operations as described below and performed in the PCM device are performed under the control of the control unit CU, which may be programmed to implement the methods 20, 30 described herein.

[0086] Figure 3 is a flow chart of a method 20 for performing a write operation including a write verify operation.

[0087] In order to perform such a method 20, the cells of the PCM memory can be divided into multiple groups ("sets"), the multiple groups including at least four different groups: a first group, the first group includes direct cells that will be set to a high logic level by means of a set write operation; a second group, the second group includes complementary cells that will be set to a high logic level by means of a set write operation; a third group, the third group includes direct cells that will be set to a low logic level by means of a reset write operation; and a fourth group, the fourth group includes complementary cells that will be set to a low logic level by means of a reset write operation.

[0088] In such a method 20, each of the groups is managed sequentially relative to the other groups, for example, writing operations and write verification operations are performed on the first group first, and then writing operations and write verification operations are performed on the second, third and fourth groups in sequence.

[0089] In summary, multiple sets (groups) of cells include: direct cells, each direct cell is configured to have a direct bit value written therein, the direct bit value being equal to one of such a high logic level and a low logic level; and complementary cells, each cell in the set of complementary cells being coupled to a corresponding cell in the set of direct cells and being configured to have a complementary bit value written therein, the complementary bit value being equal to the other of such a high logic level and a low logic level.

[0090] Such direct cells and complementary cells are arranged in: a first set (first group), the first set includes direct cells configured to write direct bit values ​​equal to such a high logic level therein; a second set (second group), the second set includes complementary cells configured to write complementary bit values ​​equal to the high logic level therein; a third set (third group), the third set includes direct cells configured to write direct bit values ​​equal to such a low logic level therein; and a fourth set (fourth group), the fourth set includes complementary cells configured to write complementary bit values ​​equal to the low logic level therein.

[0091] Thus, such a verification phase includes: performing such a first write verification operation on such a first set of direct cells and such a second set of complementary cells; and performing such a second write verification operation on such a third set of direct cells and such a fourth set of complementary cells.

[0092] Such a set and reset pulse phase, i.e., correcting the actual logic level of at least one cell to match the binary logic level of such at least one cell (i.e., setting the logic level of such at least one cell using a corresponding write operation), includes: a set write operation 3161 performed on the cells included in such a first set and such a second set; and a reset write operation 3162 performed on the cells included in such a third set and such a fourth set.

[0093] The method 20 starts with step 200 which is configured, for example, to mark each group as not yet considered, and then such method 20 proceeds to a first setting step 202 .

[0094] Note that such marking can be done in any possible way, for example, by associating a binary flag with the group, such flag indicating the status of the group, i.e., considered / not considered; or by associating each group with a number, for example, associating the first group with the number one ("1"), the second group with the number two ("2"), and so on; and by storing a group counter value in a variable, the group counter value indicating which group is the first group that has not yet been considered, i.e., the currently selected group, for example, if such a group counter value is equal to 2, the first group has been considered, the second, third and fourth groups are still to be considered, and the second group is considered to be the currently selected group.

[0095] Such a first setting step 202 is configured to select a group from among the plurality of groups described above, for example, to select a first group from among the plurality of groups.

[0096] For example, if each group is associated with a number, the group associated with the smaller number, eg, the first group associated with the number 1, may be selected.

[0097] Alternatively, if each group is associated with a corresponding flag, a random group among the plurality of groups may be selected, or the first group may always be selected first.

[0098] The first checking step 204 is configured to check whether each group of the plurality of groups has been considered.

[0099] For example, if each group is associated with a number, for example, the first group, the second group, the third group and the fourth group are associated with the numbers 1, 2, 3 and 4 respectively, the first checking step 204 can be configured to check whether the variable containing the group counter value is greater than 4, and if such a condition is met, the first checking step 204 is configured to determine that each of the multiple groups has been considered.

[0100] Alternatively, if each group is associated with a corresponding flag, the first checking step 204 may be configured to check whether the value of each flag corresponds to a value indicating that the corresponding group has been considered, and if such a condition is met, the first checking step 204 is configured to determine that each of the plurality of groups has been considered.

[0101] If each of the plurality of groups has been considered, the method 20 proceeds to an end step 228 , which is configured to end the corresponding method 20 .

[0102] Otherwise, if there are still groups to be considered, for example, if the currently selected group is still to be considered, method 20 proceeds to a second setting step 206, and such a second setting step 206 is configured as: if the operation to be performed is a setting write operation, then the first setting pulse PS1 is selected as the current pulse (i.e., the currently selected current pulse) for performing the subsequent setting pulse stage; and if the operation to be performed is a reset write operation, then the first reset pulse PR1 is selected as the current pulse (i.e., the currently selected current pulse) for performing the reset pulse stage.

[0103] Note that the operation to be performed depends on the sub-phase of the pulse phase to be performed, ie, on the currently selected group of the plurality of groups.

[0104] In fact, if the currently selected group is the first group, the second group, the third group or the fourth group, the corresponding selected sub-phases of the pulse phase to be executed are the direct unit setting pulse sub-phase, the complementary unit setting pulse sub-phase, the direct unit reset pulse sub-phase or the complementary unit reset pulse sub-phase.

[0105] Such a second setting step 206 is also configured to mark each of the reset / set current pulses PR and PS as still unused.

[0106] Note that the content previously described for marking groups is valid even for pulse marking operations, and therefore, such pulse marking can be done in any possible way, for example, by associating a binary flag with the pulse, such flag indicating the state of the pulse, i.e., considered / not considered; or by associating each pulse with a number, for example, associating the first set pulse PS1 and the first reset pulse PR1 with the number 1 ("1"), associating the second set pulse PS2 and the second reset pulse PR2 with the number 2 ("2"), and so on; and by storing a pulse counter value in a variable, the pulse counter value indicating which is the first pulse that has not yet been considered, i.e., the currently selected current pulse, for example, if such a pulse counter value is equal to 3, and if a set write operation is being performed, the first set pulse PS1 and the second set pulse PS2 have been considered, while the third set pulse PS3 remains to be considered and is regarded as the currently selected pulse.

[0107] After selecting the current pulse to be used in the corresponding reset or set pulse phase, the method 20 proceeds to a verification setup step 208, such a verification setup step 208 being configured to prepare the PCM for performing a write verification operation, for example by selecting a correct fixed reference current, the value of which depends on the sub-phase of the verification phase to be performed, i.e., on the currently selected group of the plurality of groups.

[0108] In fact, if the currently selected group is the first group, the second group, the third group or the fourth group, the corresponding selected sub-stages of the verification stage to be executed are the direct unit setting verification sub-stage, the complementary unit setting verification sub-stage, the direct unit reset verification sub-stage or the complementary unit reset verification sub-stage.

[0109] Then, the verification step 210 is configured to perform the operation of the sub-phase, ie, the operation selected according to the currently selected group, ie, the operation to be performed on each unit included in the currently selected group.

[0110] Such execution operation includes, for each cell included in the currently selected group, comparing the current flowing in the considered cell with the fixed reference current selected in the verification setting step 208 and checking whether such current flowing in the considered cell is higher or lower than such fixed reference current.

[0111] The verification step 210 is also configured to provide a result for each cell included in the selected group to a second checking step 212, such result indicating the result of the verification sub-stage performed, for example, a value indicating a successful or failed operation, i.e., indicating whether the currently considered cell included in such currently selected group is correctly set to the expected logic level.

[0112] The condition for determining the success or failure of the operation in order to set the value of the corresponding result depends on the currently selected group. Therefore, if the currently selected group is the first group or the second group, the success condition is determined if the result of the checking operation determines that such current flowing in the cell under consideration is higher than such fixed reference current, otherwise, if the currently selected group is the third group or the fourth group, the success condition is determined if the result of the checking operation determines that such current flowing in the cell under consideration is lower than such fixed reference current.

[0113] The second checking step 212 is configured to receive such results of performing the verification sub-phase on each unit included in the currently selected group from the verification step 210, and to check whether any of such results indicates that a unit among such units included in the currently selected group is not correctly set to the expected value, that is, whether at least one result indicates an unsuccessful operation.

[0114] If each cell included in the selected group is correctly set to the expected value, method 20 proceeds to a first incrementing step 214, such an incrementing step 214 being configured to mark the currently selected group as used and to select a different group among the multiple groups, for example, by selecting the next group in the sequence of groups, giving priority to those groups that have not yet been considered.

[0115] For example, if each group is associated with a number, the first incrementing step 214 is configured to increment the group counter value to change the label of the currently selected group to used and select the group corresponding to the incremented value of the group counter value as the new currently selected group.

[0116] Alternatively, if each group is associated with a corresponding flag, the first incrementing step 214 is configured to change the flag value of the currently selected group to indicate that such group has been considered, and to select a different group among the multiple groups that has not yet been considered as the new currently selected group, for example randomly or in a predetermined order.

[0117] After such a first incrementing step 214 , the method 20 returns from the first incrementing step 214 to the first checking step 204 .

[0118] If one or more cells included in the selected group are not correctly set to the expected value, the method 20 proceeds to a third checking step 216 .

[0119] The third checking step 216 is configured to check whether the currently selected current pulse for performing the set or reset pulse phase, i.e. the current pulse selected in the second setting step 206 or in the second incrementing step 226, is included in the set of available current pulses (e.g. Figure 2A and Figure 2B ) and are marked as still unused, ie such a third check step 216 checks whether there are any remaining current pulses available for use.

[0120] For example, if each current pulse is associated with a number, the third check step 216 may be configured to check whether the variable containing the pulse counter value is greater than 3 ( Figure 2A and Figure 2B The third check step 216 may be configured to determine that each current pulse has been considered, if such a condition is met.

[0121] Alternatively, if each pulse is associated with a corresponding flag, the third checking step 216 may be configured to check whether the value of each flag corresponds to a value indicating that the corresponding pulse has been considered, and if such a condition is met, the third checking step 216 is configured to determine that each pulse has been considered.

[0122] If the currently selected current pulse has been used, that is, if every current pulse has been used, the method 20 proceeds to a third setting step 218, which is configured to indicate that the write operation has failed, for example by setting the value of a failure variable to a high logic level and, optionally, sending such a failure variable to an internal and / or external control unit (for example, to any type of refinement unit, such as a processor, a microprocessor, a microcontroller, a logic unit, etc., even distributed on a control unit CU, such as a PCM).

[0123] After a write operation failure occurs through such a third setup step 218 , the method 20 proceeds to an end step 228 , which is configured to end the method 20 .

[0124] Otherwise, if at least the currently selected current pulse is still used, the method 20 proceeds to a first switching step 220 configured to modify the configuration and / or configuration parameters of the PCM to switch from a write-verify operation to a write operation.

[0125] The pulse step 222 is then configured to generate a current pulse having the characteristics of a currently selected current pulse, for example, the current pulse selected in the second setting step 206 or the current pulse selected in the second incrementing step 226, and to apply such a generated current pulse to each cell included in the currently selected group that is not correctly set to the desired value.

[0126] The second switching step 224 is configured to modify the configuration and / or configuration parameters of the PCM to switch from a write operation to a write verify operation, and then the method 20 proceeds to the second incrementing step 226 .

[0127] The second incrementing step 226 is configured to mark the currently selected current pulse as used, and if such a next current pulse is marked as not yet used, select the next current pulse in the sequence of current pulses, for example, setting the current pulse PS ( Figure 2B ) sequence or reset current pulse PR( Figure 2A ) sequence.

[0128] For example, if each current pulse is associated with a number, the second incrementing step 226 is configured to increment the pulse counter value to change the label of the currently selected current pulse already in use and select the current pulse corresponding to the incremented value of the pulse counter value as the new currently selected current pulse.

[0129] Alternatively, if each pulse is associated with a corresponding flag, the second incrementing step 226 is configured to change the flag value of the currently selected current pulse to indicate that such current pulse has been considered, and to select a different current pulse that has not yet been considered as the new currently selected current pulse, e.g. in a predetermined order.

[0130] For example, if each pulse is associated with a corresponding flag, an example of a predetermined sequence for selecting the next current pulse to be considered as the new currently selected current pulse may be:

[0131] - if the operation to be performed is a set write operation, the order of the current pulses selected as the currently selected current pulses is (from the first to the last): the first set pulse PS1, the second set pulse PS2 and the third set pulse PS3;

[0132] - if the operation to be performed is a reset write operation, the order of the current pulses selected as the currently selected current pulses is (from the first to the last): the first reset pulse PR1, the second reset pulse PR2, and the third reset pulse PR3; and

[0133] If each current pulse within such a sequence of current pulses is marked as used, any selection is possible (even if the next current pulse is not selected), since the method 20 ends in failure as soon as the third checking step 216 is reached again before executing the further pulse step 222 .

[0134] After such second incrementing step 226 , the method 20 is configured to return to the verification setup step 208 .

[0135] Figure 3 The method 20 in helps to perform a write operation, the write operation includes a write verification operation, but:

[0136] - each write-verify operation may be affected by a different wordline IR drop, such wordline IR drop during each such write-verify operation depending on the pattern of cells considered in the corresponding tile, i.e., such wordline IR drop during each such write-verify operation may depend on the sequence of logic levels of cells considered in the corresponding tile; and

[0137] - Method 20 is relatively slow and not optimized for fast write-verify operations, resulting in less reactive PCM devices and degrading the performance of systems containing such PCM devices.

[0138] A word line IR drop during a write verify operation may be caused by an asymmetry between the number of cells set to a high logic level and the number of cells set to a low logic level in a corresponding tile, such asymmetry being caused by cells in such a tile not being set to the correct desired logic level, for example, cells being set to a low logic level instead of a high logic level, thereby increasing the number of cells in such a tile that are currently set to one of the logic levels, for example, increasing the number of cells in such a tile that are set to a low logic level.

[0139] Thus, during a write verify operation, the number of cells storing a high logic level in a given tile may be different from a number N, and thus, the number of cells storing a low logic level in the same given tile may be different from a number N, where such number N is the number of sense amplifiers in such given tile.

[0140] Note that during the first verification operation and / or the last verification operation performed on a given tile, such asymmetry may not exist because the cells of such tile should be at the correct logic levels (i.e., obtained due to a successful write operation and therefore balanced), i.e., the number of cells storing high logic levels in such tile should be equal to the number of cells storing low logic levels in such tile, and both should be equal to the number N indicating the number of sense amplifiers in such tile.

[0141] As previously described, method 20 is relatively slow and is not optimized for fast write verification operations because: the direct and complementary cell pulse phases are managed separately; and for each of the multiple groups, a first switching step 220 is required whenever method 20 switches from a write verification operation to a write operation, and a second switching step 224 is required whenever method 20 switches from a write operation to a write verification operation.

[0142] The first switching step 220 and the second switching step 224 involve both time consumption and additional consumption (ie additional current consumption), possibly due to the presence of charging and discharging elements for performing such steps.

[0143] Figure 4 and Figure 5 is a flow chart of a method 30 , 30 ′ for performing a write operation including a write verify operation according to the solution disclosed herein.

[0144] In order to further improve the performance of such a method, instead of injecting the current of only the verified cells into the word line WL j and therefore not only coupling the cell to be verified to the word line WL j, but both the direct cell and the corresponding complementary cell are coupled to the selected word line, for example, word line WL j , so, as in a differential read operation, they both contribute to the word line IR falling. In this way, both the current of the direct cell and the current of the corresponding complementary cell are injected into the word line WL j In the word line WL j The IR drop remains stable.

[0145] Figure 4 and Figure 5 Such an illustrated method 30 , 30 ′ may be used to reduce the effects of the problems illustrated for the method 20 described above.

[0146] The methods 30, 30' are based on performing a set of write verify operations comprising, for example, a subset of write verify operations related to the first group, a subset related to the second group, a subset related to the third group and a subset related to the fourth group without pulse phases in between.

[0147] Such subsets of write verification operations are considered in sequence, for example, write verification operations of a subset related to the first group, write verification operations of a subset related to the second group, write verification operations of a subset related to the third group, and write verification operations of a subset related to the fourth group are performed in sequence.

[0148] Note that other sequences may also be considered, for example, sequences determined by randomly ordering the subsets.

[0149] In this way, a first set of write verification operations (i.e., including write verification operations performed before any pulse phase) can be performed without any asymmetry between the number of cells in the corresponding block that are set to a high logic level and the number of cells in the same block that are set to a low logic level, because such write verification operations are performed before any pulse phase, i.e., when the cells of such blocks should be at the correct logic level as they are obtained by a successful write operation.

[0150] Therefore, if the number of sense amplifiers for such a block is equal to the number N, the number of cells storing high logic levels in the same block is equal to the number N and even the number of cells storing low logic levels in the same block is equal to the number N, that is, equal to the number of cells storing high logic levels.

[0151] Furthermore, methods 30, 30' are based on performing a set of write operations, for example, a first set of write operations comprising a subset of write operations relating to a first group and a subset of write operations relating to a second group, and a second set of write operations comprising a subset of write operations relating to a third group and a subset relating to a fourth group, wherein such first set of write operations and such second set of write operations are performed without a verification phase in between.

[0152] These sets and subsets of write operations are considered in sequence, for example, the write operations of the first set are performed in sequence, i.e., the write operations of the subset related to the first group and the write operations of the subset related to the second group are performed in sequence; and the write operations of the second set, i.e., the write operations of the subset related to the third group and the write operations of the subset related to the fourth group are performed in sequence.

[0153] Also in this case, note that other sequences may also be considered, for example, sequences determined by random ordering of sets and subsets.

[0154] Therefore, since the second set of write verification operations is performed after the first set of write operations and the second set of write operations, and considering that only about 3% of the cells within the tile require a second set pulse and less than about 1% of the cells in the tile require a second reset pulse, if the number of sense amplifiers for a given tile is equal to the number N, the number of cells storing high logic levels in the same tile is approximately the number N, and even the number of cells storing low logic levels in the same tile is also approximately the number N.

[0155] Thus, the effect of the asymmetry can be considered almost negligible even for the second set of write verify operations, and given that an even smaller percentage of cells require a third pulse or additional pulses, the asymmetry effect can be considered almost negligible even for the sets of write verify operations considered after the second group.

[0156] In general, the wordline IR drop caused by such asymmetry may be considered constant during each write-verify operation performed by the method 30 , 30 ′.

[0157] Such a conclusion is typically valid when such a method 30, 30' is used due to the first set of write operations, and typically each set of write operations includes performing a write operation on each cell of each of a plurality of groups, so that each cell of the corresponding block whose logic level will be modified during the current write operation has received at least one current pulse, i.e., only a very small number of such cells are still at an erroneous logic level (refer to the percentage above), keeping the cells set to one logic level and the cells set to another logic level balanced.

[0158] Note that similar conclusions may not apply to method 20 because, by performing a write operation on each cell of a single group, i.e., during the pulse step 222, before the next write verification operation, i.e., before the next verification step 210, a portion of the cells in the corresponding block whose logic levels are to be modified during the current write operation are still set according to the previous write operation, i.e., have not yet received the current pulse, while another portion of the cells in the same block whose logic levels are to be modified during the current write operation are set according to such a current write operation, i.e., have received the current pulse and may be waiting for the second pulse, resulting in an imbalance between the cells that are set to a logic level and the cells that are set to another logic level.

[0159] The method 30 , 30 ′ is also based on merging the direct cell set pulse sub-phase with the complementary cell set pulse sub-phase.

[0160] Such merging can be accomplished in a two-cell-per-bit PCM because each sense amplifier in the tile is already coupled to only one of its two terminals that will be set to a high logic level, thus allowing the set pulse sub-phases for both the direct cell and the complementary cell to occur simultaneously.

[0161] Thus, direct cells coupled to some of the sense amplifiers are pulsed with corresponding set pulses along with complementary cells coupled to some other of the sense amplifiers.

[0162] Such a merging of the direct cell set pulse sub-phase and the complementary cell set pulse sub-phase is possible because the write verify operation of the verify phase has been performed for each of the plurality of groups prior to any of such pulse phases.

[0163] Similarly, the methods 30 , 30 ′ are also based on merging the direct cell reset pulse sub-phase with the complementary cell reset pulse sub-phase.

[0164] Even in this case, such merging can be accomplished in a two-cell-per-bit PCM because each sense amplifier in the tile is already coupled to only one of its two terminals that will be set to a low logic level, thus allowing the reset pulse sub-phases for both the direct cell and the complementary cell to occur simultaneously.

[0165] Thus, direct cells coupled to some of the sense amplifiers are pulsed with corresponding reset pulses along with complementary cells coupled to other ones of the sense amplifiers.

[0166] Even in this case, note that such merging of direct cell reset pulse subphases and complementary cell reset pulse subphases is possible because the write verify operation of the verify phase has been performed for each of the plurality of groups prior to any of such pulse phases.

[0167] Due to one or more of the changes described above, namely, one or more of the following: performing a set of write verification operations without an intermediate pulse phase; merging the direct cell setting pulse subphase and the complementary cell setting pulse subphase; and merging the direct cell reset pulse subphase and the complementary cell reset pulse subphase; wherein the number of executions of the first switching step 220 and the second switching step 224 can be reduced accordingly.

[0168] For example, in Figure 4 or Figure 5 In the embodiment shown, the number of times the first switching step 220 and the second switching step 224 need to be performed is equal to the number of available current pulses, for example, equal to Figure 2A or Figure 2B The number of current pulses in the set of current pulses illustrated in .

[0169] For example, if the current pulses used in the embodiments of the methods 30, 30' are as follows Figure 2A and Figure 2B As shown, for each write operation, the first switching step 220 and the second switching step 224 are only required three times at most.

[0170] Reducing the number of times such a first switching step 220 and such a second switching step 224 need to be performed can further reduce: the time required for performing a write operation, because the time required for such switching operations is reduced; and the consumption of the corresponding PCM device and / or related devices.

[0171] Furthermore, the time required to perform write operations may be further reduced by parallelizing (ie, merging) set write operations for direct cells and complementary cells, and / or reset write operations for direct cells and complementary cells.

[0172] Thus, the method 30, 30', e.g. Figure 4 or Figure 5 The method shown can alleviate the previously described Figure 3 The impact of the problem with method 20 is shown.

[0173] Figure 4 The method 30 shown includes at least the following steps:

[0174] a set of verification steps 306 configured to perform a write verification operation on each cell of each of the plurality of groups, i.e., depending on the group considered of the plurality of groups, to perform a given sub-phase of the verification phase on each cell included in the group considered;

[0175] - Checking steps 308-310, configured to check whether further write operations (i.e., further pulse phases) are needed, for example by determining whether any cell of any of the plurality of groups is not correctly set to the expected value, i.e., whether one or more of the write verification operations have failed, and by checking whether there are still any current pulses available for use, for example by checking whether the current pulse selected for performing the set or reset pulse phase is included in the set of available current pulses (e.g., Figure 2A and Figure 2B The current pulses shown in the figure are in the set) and are marked as still unused;

[0176] - a set pulse step 3161 configured to perform a set write operation, i.e. generate a set current pulse and apply the set current pulse thus generated to each cell which is not correctly set to a high logic level, regardless of their group; and

[0177] - A reset pulse step 3162, configured to perform a reset write operation, ie, generate a reset current pulse and apply the reset current pulse thus generated to each cell that is not correctly set to a low logic level, regardless of their group.

[0178] Such a set pulse step 3161 and such a reset pulse step 3162 are performed only if such checking steps 308-310 determine that one or more cells of any of the plurality of groups are not correctly set to the desired logic level.

[0179] In various embodiments, if there is at least one cell that is not correctly set to a high logic level, but every cell that should be set to a low logic level is correctly set, method 30 can be configured to perform a set pulse step 3161 instead of a reset pulse step 3162.

[0180] In various embodiments, if there is at least one cell that is not correctly set to a low logic level, but every cell that should be set to a high logic level is correctly set, method 30 can be configured to perform a reset pulse step 3162 instead of performing a set pulse step 3161.

[0181] In summary, the method 30 may be used to perform a write operation in a phase change memory (PCM) device, the PCM device including a plurality of sets (groups) of cells, e.g., the described first, second, third, and fourth groups, the plurality of sets (groups) of cells being configured to write therein a binary logic level selected from a high logic level and a low logic level in response to the write operation, wherein each cell is included in a corresponding set of cells in the plurality of sets of cells;

[0182] The method 30 includes:

[0183] performing a write verify operation 306 on cells of the plurality of sets of cells, the write verify operation configured to provide a result indicative of an actual logic level stored in the cells in the plurality of sets, wherein the write verify operation is performed on each cell using a set of parameters (e.g., a given reference current and a direction of the inequality) selected based on a corresponding set of cells that includes the cell;

[0184] checking 308-310 whether actual logic levels stored in cells in such plurality of sets match such binary logic levels based on results from such write verify operations;

[0185] In response to such checking 308-310 determining that in at least one cell in such plurality of sets, the actual logic level does not match such binary logic level, correcting such actual logic level to match such binary logic level by:

[0186] In case the binary logic level is a high logic level, a write operation 3161 is set; and

[0187] When the binary logic level is a low logic level, the write operation 3162 is reset.

[0188] Therefore, the method 30 may further include: in response to a failed set write operation 3161 and / or a failed reset write operation 3162, using a set PS current pulse or a reset PR current pulse of increasing value (eg, Figure 2A and Figure 2B As described), repeat such a set write operation 3161 and / or such a reset write operation 3162.

[0189] In various embodiments, Figure 4 The illustrated method 30 may include additional steps, for example, Figure 5 The steps of the method 30' shown, a subset of such steps (e.g., by excluding the second setting step 312), or even in addition to Figure 5 Additional steps beyond those shown.

[0190] Therefore, Figure 5 The following description of the steps of the method 30' is reported herein only as an example, i.e., to show Figure 4 Examples of possible ways of adding steps to such method 30 are shown.

[0191] Note that method 30 may also include only Figure 4 The steps described above (i.e., 306, 308-310, 3161, 3162) as shown, or, in various embodiments, for example, as Figure 5 As shown, such a method 30 may even include additional steps as previously described.

[0192] The method 30 ′ starts at step 300 and proceeds to a first setup step 302 .

[0193] Such a first setting step 302 is configured to select the first setting pulse PS1 as the setting current pulse for performing a subsequent setting pulse phase, and to select the first reset pulse PR1 as the reset current pulse for performing a reset pulse phase.

[0194] Furthermore, such a first setting step 302 is also configured to mark each of the reset / set current pulses PR and PS as still unused.

[0195] Such pulse labeling can be done in any possible way, for example, by associating a binary flag with the pulses, such flag indicating the state of the pulse, i.e., considered / not considered; or by associating each pulse with a number, for example, associating the first set pulse PS1 and the first reset pulse PR1 with the number 1 ("1"), the second set pulse PS2 and the second reset pulse PR2 with the number 2 ("2"), and so on; and by storing a pulse counter value in a variable, the pulse counter value indicating which is the first pulse that has not yet been considered, i.e., the currently selected current pulse, for example, if such a pulse counter value is equal to 3 and if a set write operation is being performed, the first set pulse PS1 and the second set pulse PS2 have been considered, while the third set pulse PS3 will still be considered and is regarded as the currently selected pulse.

[0196] The verify setup step 304 is configured to prepare the PCM for performing a plurality of write verify operations, for example by selecting a fixed reference current for each sub-phase of the verify phase to be performed.

[0197] After the verify setup step 304, a set of verify steps 306 are performed, such set of verify steps 306 being configured to perform a set of write verify operations for each of the plurality of groups.

[0198] Each write verification operation in such a set of write verification operations comprises: for each cell included in the group associated with the currently considered set of write verification operations, comparing the current flowing in the considered cell with the fixed reference current selected in the verification setup step 304, and checking whether such current flowing in the considered cell is higher or lower than such fixed reference current.

[0199] For example, the set of verification steps 306 may include the following stages:

[0200] a first verification phase 3061 configured to implement a direct cell set verification operation to perform a write verification operation on each cell included in the first group (i.e., the group including the direct cells to be set to a high logic level by the set write operation), for example by comparing the current flowing in each such cell with a direct set verification reference current as previously described;

[0201] a second verification phase 3062 configured to implement a complementary cell set verification operation to perform a write verification operation on each cell included in the second group (i.e., the group including the complementary cells to be set to a high logic level by the set write operation), for example by comparing the current flowing in each such cell with a complementary set verification reference current as previously described;

[0202] a third verification phase 3063 configured to implement a direct cell reset verification operation to perform a write verification operation on each cell included in the third group (i.e., the group including the direct cells to be set to a low logic level by the reset write operation), for example, by comparing the current flowing in each such cell with a direct reset verification reference current as previously described; and

[0203] - A fourth verification phase 3064, which is configured to implement a complementary cell reset verification operation to perform a write verification operation on each cell included in the fourth group (i.e., the group including complementary cells that will be set to a low logic level by the reset write operation), for example by comparing the current flowing in each such cell with the complementary reset verification reference current as described above.

[0204] In addition, each of such stages 306 is also configured to provide a result for each cell included in the corresponding group associated with the stage under consideration to the checking steps 308-310, such a result indicating the result of the verification sub-stage performed, for example, a value indicating a successful or failed operation, that is, indicating whether the currently considered cell included in such a corresponding group is correctly set to the expected logic level.

[0205] The condition for determining the success or failure of the operation to set the value of the corresponding result depends on the corresponding group under consideration, therefore, if the corresponding group under consideration is the first group or the second group, then if the result of the checking operation determines that such current flowing in the cell under consideration is higher than such a fixed reference current, then the condition for success is determined, otherwise, if the corresponding group under consideration is the third group or the fourth group, then if the result of the checking operation determines that such current flowing in the cell under consideration is lower than such a fixed reference current, then the condition for success is determined.

[0206] Such a method 30 ′ then proceeds to checking steps 308 - 310 , which are configured to check whether a further write operation, ie a further pulse phase, is required.

[0207] For example, such checking steps 308-310 may include the following stages:

[0208] a first checking phase 308 configured to receive such results of performing a write verification operation on each cell included in any group from each verification phase 306, and to check whether any of such results indicates whether any of such cells included in any of the plurality of groups is not correctly set to an expected value, i.e. whether at least one result indicates an unsuccessful operation, i.e. whether one or more write verification operations have failed; and

[0209] a second checking phase 310, which is configured to detect, for example, whether the currently selected reset / set current pulse for performing a set or reset pulse phase (e.g. selected in the first setting step 302 or in the incrementing step 322) is included in the set of available reset / set current pulses (e.g. Figure 2A and Figure 2B ) and is marked as still unused, it is checked whether there are any reset / set current pulses available for use.

[0210] If the first checking stage 308 detects that each cell included in any group is correctly set to the expected value, the method 30 ′ proceeds to an end step 324 configured to end the method 30 ′.

[0211] Otherwise, if one or more cells included in any group are not correctly set to the expected value, the method 30 ′ proceeds to a second checking phase 310 .

[0212] As previously described, the second check stage 310 is configured to check whether there are any reset / set current pulses available. For example, if each of the current pulses is associated with a number, the second check stage 310 can be configured to check whether the variable containing the pulse counter value is greater than 3 ( Figure 2A and Figure 2B and, if such a condition is met, the second checking stage 310 is configured to determine that each of the current pulses has been considered.

[0213] Alternatively, if each pulse is associated with a corresponding flag, the second checking stage 310 can be configured to check whether the value of each flag corresponds to a value indicating that the corresponding pulse has been considered, and, if such condition is met, the second checking stage 310 is configured to determine that each pulse has been considered.

[0214] If the second checking phase 310 detects that each of the reset / set current pulses has been used, the method 30' proceeds to a second setting step 312, which is configured to indicate the failure of the corresponding write operation, for example by setting the value of a failure variable to a high logic level and optionally sending such a failure variable to an internal and / or external control unit (for example, to any type of refinement unit, such as a processor, a microprocessor, a microcontroller, a logic unit, etc., even distributed on a control unit CU such as a PCM), and then the method 30' proceeds to an end step 324, which is configured to end the method 30'.

[0215] Otherwise, if at least the selected reset / set current pulse (e.g., selected in the first setting step 302 or the incrementing step 322) is still to be used, for example, because it is marked as still to be used, the method 30' proceeds to a first switching step 314, such a first switching step 314 being configured to modify the configuration and / or configuration parameters of the PCM to switch from a write verification operation to a set write operation.

[0216] Then, a set pulse step 3161 is performed, such a set pulse step 3161 being configured to generate a set current pulse having the characteristics of a currently selected set current pulse, for example, the set current pulse selected in the first setting step 302 or the set current pulse selected in the incrementing step 322, and applying the set current pulse thus generated to each cell that is not correctly set to a high logic level, regardless of their group, that is, each cell that should be set to a high logic level but is instead currently set to a low logic level.

[0217] The second switching step 318 is configured to modify the configuration and / or configuration parameters of the PCM to switch from a set write operation to a reset write operation.

[0218] A reset pulse step 3162 is then performed, such that a reset pulse step 3162 is configured to generate a reset current pulse having the characteristics of a currently selected reset current pulse, for example, the reset current pulse selected in the first setting step 302 or the reset current pulse selected in the incrementing step 322, and regardless of their group, the reset current pulse thus generated is applied to each cell that is not correctly set to a low logic level, that is, each cell that should be set to a low logic level but is instead currently set to a high logic level.

[0219] The third switching step 320 is configured to modify the configuration and / or configuration parameters of the PCM to switch from the reset write operation to the write verify operation, and then the method 30 ′ proceeds to the incrementing step 322 .

[0220] The increment step 322 is configured to mark the currently selected set current pulse and the currently selected reset current pulse as used, and if such next set and reset current pulses are marked as not yet used, then in the sequence of set current pulses (eg, Figure 2B The next setting current pulse is selected in the sequence of setting current pulses PS of Figure 2A The next reset current pulse is selected from the sequence of reset current pulses PR).

[0221] For example, if each of the current pulses is associated with a number, the increment step 322 is configured to increment the pulse counter value to change the flag of the currently selected reset / set current pulse to used and select the reset / set current pulse corresponding to the incremented value of the pulse counter value as the new currently selected reset / set current pulse.

[0222] Alternatively, if each pulse is associated with a corresponding flag, the increment step 322 is configured to change the flag value of the currently selected reset / set current pulse to indicate that such a current pulse has been considered, and to select, for example in a predetermined order, a different reset / set current pulse that has not yet been considered as the new currently selected reset / set current pulse.

[0223] For example, if each pulse is associated with a corresponding flag, an example of a predetermined sequence for selecting the next reset / set current pulse to be considered as the new currently selected reset / set current pulse may be:

[0224] - the order in which the setting current pulses are selected as the currently selected setting current pulses for performing the next setting pulse phase is (from the first to the last): the first setting pulse PS1, the second setting pulse PS2 and the third setting pulse PS3;

[0225] - the order in which the reset current pulses are selected as the currently selected reset current pulses for performing the next reset pulse phase is (from first to last): the first reset pulse PR1 , the second reset pulse PR2 and the third reset pulse PR3 ; and

[0226] - If each reset / set current pulse in such a sequence of reset / set current pulses is marked as used, any selection can be made (even if the next reset / set current pulse is not selected), because the method 30' ends in failure as soon as the second checking phase 310 is reached again before the further pulse steps 3161 and 3162 are performed.

[0227] In various embodiments, in response to a failed set write operation 3161 and / or a failed reset write operation 3162, a next reset / set current pulse to be considered as the new currently selected reset / set current pulse is selected, and additional set write operations 3161 and / or additional reset write operations 3162 are performed using set PS or reset PR current pulses of increased values, respectively.

[0228] After such incrementing step 322 , the method 30 ′ is configured to return to the verification setup step 304 .

[0229] The solutions described herein facilitate implementing a method for performing a PCM write operation, the PCM write operation including a write verify operation, i.e., writing a word including one or more bits in a phase change memory (PCM) device, the PCM device including multiple groups (“sets”) of cells, the cells being configured to write therein a binary logic level selected from a high logic level and a low logic level in response to a write operation (e.g., a set write operation or a reset write operation), wherein each cell is included in a corresponding group (“set”) of cells in the multiple groups (“sets”) of cells.

[0230] Thus, embodiments of the methods described herein include performing (at least) the following steps:

[0231] - performing a write-verify operation on cells in a plurality of groups ("sets") of such cells, the write-verify operation being configured to provide a result indicative of an actual logic level stored in the cells in such plurality of groups ("sets"), wherein the write-verify operation is performed on each cell using a set of parameters, the set of parameters being selected based on a corresponding group ("set") of cells that includes the cell;

[0232] - based on the results of such write-verify operations, checking whether the actual logic levels stored in the cells in such multiple groups ("sets") match such binary logic levels; and

[0233] In response to such checking determining that in at least one cell in such plurality of groups (“sets”) the actual logic level does not match the binary logic level, correcting such actual logic level to match the binary logic level by:

[0234] Set the write operation, in the case of a binary logic level high logic level, or

[0235] Reset write operation, where the binary logic level is a low logic level.

[0236] Therefore, the solution described herein helps to reduce current variations within a cell to facilitate a write verification operation, ie, an operation for checking the success of a write operation, thereby enabling a write operation with higher performance.

[0237] Furthermore, the solution described herein can improve the accuracy of write verification operations because in each operation, the subline WL j The IR drop can be considered to be approximately constant.

[0238] Then, the reduction in the number of switching operations (e.g., such a first switching step 220 and such a second switching step 224) can further reduce the time required to perform a write operation because the time required for such switching operations is reduced, and the consumption of the PCM and / or related devices can also be reduced.

[0239] The time taken to perform a write operation can be further reduced by parallelizing the set write operations for the direct cell and the complementary cell and the reset write operations for the direct cell and the complementary cell.

[0240] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what is described purely by way of example, without departing from the scope of the embodiments.

[0241] The claims are an integral part of the technical teaching provided for the exemplary embodiments.

[0242] The scope of protection is determined by the appended claims.

Claims

1. A method of performing a write operation in a phase change memory (PCM) device, the PCM device comprising a plurality of sets of cells, the cells being configured to write therein a binary logic level in response to a write operation, the binary logic level being selected from a high logic level and a low logic level, wherein each cell is included in a corresponding set of cells in the plurality of sets of cells, the method comprising: performing a write verify operation on the cells in the plurality of sets of cells, the write verify operation being configured to provide a result indicative of an actual logic level stored in the cells in the plurality of sets of cells, wherein the write verify operation is performed on each cell using a set of parameters selected according to a corresponding set of cells that includes the cell; checking whether the actual logic levels stored in the cells in the plurality of sets match the binary logic levels based on the results from the write verify operation; In response to the examining determining that the actual logic level does not match the binary logic level in at least one cell in the plurality of sets, correcting the actual logic level to match the binary logic level by performing one of: Set the write operation, in the case where the binary logic level is a high logic level, and Reset write operation, where the binary logic level is a low logic level.

2. The method of claim 1, wherein the PCM device is a two-cell-per-bit phase change memory PCM device.

3. The method of claim 1 , wherein the plurality of sets of the units comprises: a set of direct cells, wherein each direct cell is configured to have a direct bit value written therein, the direct bit value being equal to one of the high logic level and the low logic level; as well as A set of complementary cells, wherein each complementary cell is coupled to a corresponding direct cell in the set of direct cells, and wherein each complementary cell is configured to have a complementary bit value written therein, the complementary bit value being equal to the other of the high logic level and the low logic level.

4. The method according to claim 3, wherein the direct unit and the complementary unit are arranged in: In the first set, the first set includes: a direct cell configured to write therein a direct bit value equal to the high logic level; In the second set, the second set includes: complementary cells configured to write complementary bit values ​​equal to a high logic level therein; In a third set, the third set includes: a direct cell configured to write a direct bit value equal to the low logic level therein; and In the fourth set, the fourth set includes: complementary cells configured to write complementary bit values ​​equal to a low logic level therein.

5. The method of claim 4 , wherein correcting the actual logic level to match the binary logic level comprises: performing the set write operation on direct cells included in the first set and the second set; as well as A reset write operation is performed on complementary cells included in the third set and the fourth set.

6. The method according to claim 4, The write verification operation includes: a first write verification operation performed on a first cell of the plurality of sets of cells using a first reference current by: checking whether the current flowing through the cell subjected to the first write verification operation is higher than the first reference current, and determining that the actual logic level stored in the first cell of the plurality of sets of cells does not match the binary logic level in response to the current flowing through the cell subjected to the first write verification operation being lower than the first reference current, the first reference current having a first direction of an inequality; and / or a second write verification operation performed on a second cell of the plurality of sets of cells using a second reference current by: checking whether the current flowing through the cell subjected to the second write verification operation is lower than the second reference current, and determining that the actual logic level stored in the second cell of the plurality of sets of cells does not match the binary logic level in response to the current flowing through the cell subjected to the second write verification operation being higher than the second reference current, the second reference current having a second direction of the inequality; And the method also includes: performing the first write-verify operation on the first set of the direct cells and the second set of the complementary cells; as well as The second write-verify operation is performed on the third set of the direct cells and the fourth set of the complementary cells. The method according to claim 6 , wherein the first reference current is higher than the second reference current.

8. The method according to claim 1, wherein the set of parameters comprises: a reference current for comparison with a current flowing through the cell subjected to a write verification operation; as well as The direction of the inequality that is applied in the comparison.

9. The method according to claim 1, wherein the write verification operation comprises: a first write verification operation performed on a first cell of the plurality of sets of cells using a first reference current by: checking whether the current flowing through the cell subjected to the first write verification operation is higher than the first reference current, and determining that the actual logic level stored in the first cell of the plurality of sets of cells does not match the binary logic level in response to the current flowing through the cell subjected to the first write verification operation being lower than the first reference current, the first reference current having a first direction of an inequality; and / or A second write verification operation is performed on a second cell in the multiple sets of cells using a second reference current by: checking whether the current flowing through the cell undergoing the second write verification operation is lower than the second reference current, and determining that the actual logic level stored in the second cell in the multiple sets of cells does not match the binary logic level in response to the current flowing through the cell undergoing the second write verification operation being higher than the second reference current, the second reference current having a second direction of the inequality.

10. The method of claim 9, wherein the first reference current is higher than the second reference current.

11. The method according to claim 1, comprising: In response to a failed set write operation and / or a failed reset write operation, the set write operation and / or the reset write operation are repeated using a set current pulse or a reset current pulse of an increased value, respectively.

12. A phase change memory (PCM) device comprising a plurality of sets of cells, wherein the cells are configured to be set to a given logic level in response to a write operation, the PCM device being configured to implement the method according to claim 1.

13. A computer program product capable of being loaded into a control unit of a phase change memory (PCM) device, the PCM device comprising a plurality of sets of cells, the cells being configured to be set to a given logic level in response to a write operation, the computer program product comprising a portion of software code, the software code being configured to cause the PCM device to implement the method according to claim 1 in response to the computer program product being run in the control unit of the PCM device.

14. A method of performing a write operation in a phase change memory (PCM) device, wherein each bit of data is stored in a pair of memory cells, the pair of memory cells comprising a direct memory cell and a complementary memory cell, the direct memory cell being configured to store a direct bit value, the direct bit value being equal to one of a set state and a reset state, the complementary memory cell being configured to store a complementary bit value, the complementary bit value being equal to the other of the set state and the reset state, the method comprising: In response to writing the bits of the data to the pairs of the memory cells: A write verification operation is performed on the memory cells in pairs by: comparing an output current from only the direct memory cell in the pair of the memory cells with a first reference current to detect whether the direct bit value is erroneously in the set state; comparing output currents from only the complementary memory cells in the pair of memory cells with the first reference current to detect whether the complementary bit value is erroneously in the set state; comparing an output current from only the direct memory cell in the pair of memory cells with a second reference current to detect whether the direct bit value is erroneously in the reset state; as well as comparing the output current from only the complementary memory cell in the pair of memory cells with the second reference current to detect whether the complementary bit value is erroneously in the reset state; as well as Correction is selectively performed on pairs of the memory cells by: applying a reset write operation to the direct memory cell to program the direct bit value to the reset state when the direct bit value in the direct memory cell is detected as being erroneously in the set state; applying a set write operation to the direct memory cell to program the direct bit value to the set state when the direct bit value in the direct memory cell is detected as erroneously in the reset state; applying a reset write operation to the complementary memory cell to program the complementary bit value to the reset state when the complementary bit value in the complementary memory cell is detected as erroneously in the set state; as well as When the complementary bit value in the complementary memory cell is detected as being erroneously in the reset state, a set write operation is applied to the complementary memory cell to program the complementary bit value to the set state. The method according to claim 14 , wherein the first reference current is higher than the second reference current.

16. The method of claim 14, wherein applying a reset write operation comprises: A reset current pulse is applied to the direct memory cell or the complementary memory cell to be programmed to the reset state, and wherein applying a set write operation comprises applying a set current pulse to the direct memory cell or the complementary memory cell to be programmed to the set state.

17. The method according to claim 16, further comprising: In response to a failed reset write operation, the reset write operation is repeated with an increased value of the reset current pulse.

18. The method according to claim 16, further comprising: In response to a failed set write operation, the set write operation is repeated using an increased value of the set current pulse.

19. A phase change memory (PCM) device, configured to implement the method according to claim 14.

20. A computer program product capable of being loaded into a control unit of a phase change memory (PCM) device, the computer program product comprising a portion of software code, the software code being configured to cause the PCM device to implement the method according to claim 14 in response to the computer program product being run in the control unit of the PCM device.

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