MRAM (Magnetic Random Access Memory) storage unit based on differential form, preparation method of MRAM storage unit, MRAM storage unit array, MRAM memory and chip

Abstract

The invention relates to the technical field of storage, in particular to an MRAM (Magnetic Random Access Memory) storage unit based on a differential form, a preparation method of the MRAM storage unit, an MRAM storage unit array, an MRAM memory and a chip. The present disclosure innovatively introduces a dual magnetic tunnel junction including a first magnetic tunnel junction and a second magnetic tunnel junction into an MRAM memory cell. The first and second magnetic tunnel junctions are mirrored on both sides of the first metal layer, their free layers are in electrical contact with the first metal layer, and their fixed layers are in electrical contact with the second and third metal layers, respectively. When a write operation is performed on the MRAM memory cell, data is written by applying write currents of different directions penetrating through the double magnetic tunnel junctions, and when a read operation is performed on the MRAM memory cell, data is read by determining a magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction. Therefore, external magnetic field interference is effectively resisted.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a differential-based MRAM storage cell and a preparation method thereof, an MRAM storage cell array, an MRAM memory, and a chip. Background Art

[0002] With the rapid development of electronic information technology, the demand for high-speed, high-density, non-volatile memory is growing. Magnetoresistive random access memory (MRAM), a new type of memory that combines the high-speed read and write capabilities of static random access memory (SRAM) and the high density and non-volatile characteristics of dynamic random access memory (DRAM), has received extensive attention and research. The basic principle of MRAM is similar to that of a hard disk drive, both of which rely on the magnetization state of magnetic materials to store data. It has significant advantages in terms of integration, read and write speed, and power consumption.

[0003] The basic storage unit of the MRAM in the prior art is mainly composed of a magnetic tunnel junction (MTJ). The MTJ has a unique structure, and its core part is composed of two layers of ferromagnetic materials (the "free" ferromagnetic layer and the "pinned" ferromagnetic layer) with an extremely thin insulating shielding layer (such as magnesium oxide or aluminum oxide) in the middle. This structure gives the MTJ a bistable tunnel magnetoresistance (TMR) effect, that is, when the spin magnetic states of the "free" ferromagnetic layer and the "pinned" ferromagnetic layer are in "parallel" or "anti-parallel", the MTJ will show two stable states of low resistance and high resistance respectively, and these two states can be used to represent the logical data "0" and "1" respectively.

[0004] However, although MRAM has a near-infinite number of writes and excellent non-volatility in theory, it still faces some challenges in practical applications. In particular, since MRAM data storage relies on the magnetization state inside the MTJ, this magnetization state is easily disturbed by strong external magnetic fields. When there is a strong external interfering magnetic field, the "free" ferromagnetic layer in the MTJ may be affected, causing its magnetization direction to change, which in turn causes an erroneous flip of the stored data, seriously affecting the read and write accuracy and data reliability of MRAM.

[0005] Therefore, developing a new type of MRAM that can effectively resist interference from external magnetic fields has become an important issue that needs to be urgently addressed in the current field of storage technology. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a differential-based MRAM memory cell and a preparation method thereof, an MRAM memory cell array, an MRAM memory, and a chip.

[0007] In a first aspect, an MRAM storage unit based on a differential form is provided in an embodiment of the present disclosure, and the MRAM storage unit includes: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer and a free layer arranged in sequence;

[0008] The first magnetic tunnel junction and the second magnetic tunnel junction are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction and the free layer of the second magnetic tunnel junction are respectively in electrical contact with the first metal layer; the fixed layer of the first magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction is in electrical contact with the third metal layer;

[0009] The gate of the MOS tube is connected to the word line, the source of the MOS tube is connected to the source line, and the drain of the MOS tube is connected to the third metal layer;

[0010] When the MRAM storage unit is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage unit through the write current, wherein the direction of the write current corresponds to the write data;

[0011] When the MRAM storage unit is in a read state, the first metal layer is connected to a first input terminal of a data reading circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data reading circuit, so that the data reading circuit reads data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, and the data of the MRAM storage unit is output through an output terminal of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0012] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction;

[0013] When the direction of the write current is the first direction, the write current is the first write current;

[0014] When the direction of the write current is the second direction, the write current is the second write current;

[0015] The direction of the write current corresponds to the write data, including:

[0016] The first write current corresponds to the first write data; the second write current corresponds to the second write data;

[0017] The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

[0018] According to an embodiment of the present disclosure, forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube according to the write data includes:

[0019] When the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube;

[0020] When the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

[0021] According to an embodiment of the present disclosure, forming a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube includes:

[0022] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor;

[0023] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises:

[0024] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is formed that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer;

[0025] Wherein, turning on the MOS tube includes: when the MOS tube is an NMOS tube, applying a forward bias voltage between the gate and the source of the MOS tube; when the MOS tube is a PMOS tube, applying a negative bias voltage between the gate and the source of the MOS tube, so that the MOS tube is turned on.

[0026] According to an embodiment of the present disclosure, writing the write data into the MRAM storage unit by the write current includes:

[0027] When the write current is the first write current, then:

[0028] The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, thereby writing the first write data;

[0029] When the write current is the second write current, then:

[0030] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, thereby writing the second write data.

[0031] According to an embodiment of the present disclosure, reading data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0032] determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction;

[0033] The data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0034] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0035] When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit;

[0036] When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit;

[0037] The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit comprises:

[0038] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data;

[0039] When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

[0040] In a second aspect, an MRAM storage unit based on a differential form is provided in an embodiment of the present disclosure, and the MRAM storage unit includes: a MOS tube, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer; wherein the three dual magnetic tunnel junctions are respectively: a first dual magnetic tunnel junction, a second dual magnetic tunnel junction and a third dual magnetic tunnel junction, and the dual magnetic tunnel junctions include: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer and a free layer arranged in sequence;

[0041] The first magnetic tunnel junction of the first double magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction of the first double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are electrically in contact with the first metal layer respectively; the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction is electrically in contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction of the first double magnetic tunnel junction is electrically in contact with the third metal layer;

[0042] The first magnetic tunnel junction of the second double magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction are mirror-imaged on both sides of the fourth metal layer, and the free layer of the first magnetic tunnel junction of the second double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are electrically in contact with the fourth metal layer respectively; the fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction is electrically in contact with the third metal layer, and the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction is electrically in contact with the fifth metal layer;

[0043] The first magnetic tunnel junction of the third double magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction are mirror-arranged on both sides of the sixth metal layer, and the free layer of the first magnetic tunnel junction of the third double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are respectively in electrical contact with the sixth metal layer; the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the fifth metal layer, and the fixed layer of the second magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the seventh metal layer;

[0044] The gate of the MOS tube is connected to the word line, the source of the MOS tube is connected to the source line, and the drain of the MOS tube is connected to the seventh metal layer;

[0045] When the MRAM storage unit is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the first dual magnetic tunnel junction, the second dual magnetic tunnel junction and the third dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube according to write data, so that the data write circuit writes the write data into the MRAM storage unit through the write current, wherein the direction of the write current corresponds to the write data;

[0046] When the MRAM storage unit is in a read state, the first metal layer, the fourth metal layer and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, so that the data reading circuit reads data of the MRAM storage unit according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, and the data of the MRAM storage unit is output through an output terminal of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0047] According to an embodiment of the present disclosure, the data reading circuit includes: a first data reading circuit, a second data reading circuit, a third data reading circuit and a logic integration circuit, wherein the output ends of the first data reading circuit, the second data reading circuit and the third data reading circuit are respectively connected to the logic integration circuit;

[0048] The first metal layer, the fourth metal layer and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, including:

[0049] The first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

[0050] According to an embodiment of the present disclosure, the data reading circuit reads data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of each double magnetic tunnel junction, including:

[0051] The first data reading circuit determines first read data according to a magnetic resistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1;

[0052] The second data reading circuit determines second read data according to a magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2;

[0053] The third data reading circuit determines the third read data according to the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3;

[0054] The logic integration circuit determines the data of the MRAM storage unit according to the first read data, the second read data and the third read data, and the data of the MRAM storage unit is output through the output terminal of the logic integration circuit;

[0055] The data D of the MRAM storage unit is expressed by the following formula:

[0056] D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

[0057] In a third aspect, an embodiment of the present disclosure provides an MRAM memory cell array based on a differential form, comprising: N MRAM memory cells according to any one of the first aspect or the second aspect arranged in an array, and N MOS tubes corresponding to the N MRAM memory cells one by one, wherein N is an integer greater than 1;

[0058] The second metal layer of each MRAM storage unit is connected to the source of the MOS tube corresponding to the MRAM storage unit, and the drains of the N MOS tubes are connected to the first source line;

[0059] The sources of the MOS tubes of each MRAM storage unit are connected to each other and then connected to the second source line; the gates of the MOS tubes corresponding to the MRAM storage units are connected to the gates of the MOS tubes of the MRAM storage units and then connected to the word lines corresponding to the MRAM storage units;

[0060] The first metal layer of each MRAM storage cell is connected to the first input terminal of the data reading circuit;

[0061] The first source line and the second source line are respectively connected to the second input terminal of the data reading circuit;

[0062] An output terminal of the data reading circuit is connected to a bit line.

[0063] In a fourth aspect, an MRAM memory based on a differential form is provided in an embodiment of the present disclosure, comprising: an MRAM memory cell array cluster, a data writing circuit, and a data reading circuit; the MRAM memory cell array cluster comprises one or more MRAM memory cell arrays according to claim 11;

[0064] The input end of the data writing circuit is connected to the external IO port for receiving the writing data;

[0065] The output end of the data writing circuit is connected to the word line of the MRAM memory cell in the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data;

[0066] The data writing circuit is configured to form a writing current that penetrates the dual magnetic tunnel junctions of the MRAM storage cells in the MRAM storage cell array between the second metal layer of the MRAM storage cells in the MRAM storage cell array and the drain of the MOS tube of the MRAM storage cells in the MRAM storage cell array according to the writing data, and write the writing data into the MRAM storage cells in the MRAM storage cell array through the writing current, wherein the direction of the writing current corresponds to the writing data;

[0067] The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0068] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction;

[0069] When the direction of the write current is the first direction, the write current is the first write current;

[0070] When the direction of the write current is the second direction, the write current is the second write current;

[0071] The direction of the write current corresponds to the write data, including:

[0072] The first write current corresponds to the first write data; the second write current corresponds to the second write data;

[0073] The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

[0074] According to an embodiment of the present disclosure, the step of forming a write current that runs through a dual magnetic tunnel junction of an MRAM storage cell in the MRAM storage cell array between a second metal layer of an MRAM storage cell in the MRAM storage cell array and a drain of a MOS tube of an MRAM storage cell in the MRAM storage cell array according to the write data comprises:

[0075] When the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube;

[0076] When the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

[0077] According to an embodiment of the present disclosure, forming a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube includes:

[0078] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor;

[0079] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises:

[0080] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is formed that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer;

[0081] Wherein, turning on the MOS tube includes: when the MOS tube is an NMOS tube, applying a forward bias voltage between the gate and the source of the MOS tube; when the MOS tube is a PMOS tube, applying a negative bias voltage between the gate and the source of the MOS tube, so that the MOS tube is turned on.

[0082] According to an embodiment of the present disclosure, writing the write data into the MRAM storage unit by the write current includes:

[0083] When the write current is the first write current, then:

[0084] The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, thereby writing the first write data;

[0085] When the write current is the second write current, then:

[0086] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

[0087] According to an embodiment of the present disclosure, the method of reading data of the MRAM memory cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array includes:

[0088] determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction;

[0089] The data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0090] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0091] When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit;

[0092] When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit;

[0093] The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit comprises:

[0094] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data;

[0095] When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

[0096] In a fifth aspect, an embodiment of the present disclosure provides a method for preparing a differential MRAM storage unit, wherein the MRAM storage unit includes: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes:

[0097] Forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit;

[0098] forming the third metal layer on the MOS tube;

[0099] forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction in sequence on the third metal layer;

[0100] forming the first metal layer on the free layer of the second magnetic tunnel junction;

[0101] forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction in sequence on the first metal layer;

[0102] The second metal layer is formed on the fixed layer of the first magnetic tunnel junction.

[0103] In a sixth aspect, an embodiment of the present disclosure provides a method for preparing a differential MRAM storage cell, wherein the MRAM storage cell comprises: a MOS tube, a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, a third dual magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the dual magnetic tunnel junction comprises: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method comprises:

[0104] Forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit;

[0105] forming the seventh metal layer on the MOS tube;

[0106] forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the seventh metal layer;

[0107] forming the sixth metal layer on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction;

[0108] forming a free layer, a non-magnetic tunnel layer and a fixed layer of a first magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the sixth metal layer;

[0109] forming the fifth metal layer on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction;

[0110] forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fifth metal layer;

[0111] forming a fourth metal layer on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction;

[0112] sequentially forming a free layer, a non-magnetic tunnel layer and a fixed layer of a first magnetic tunnel junction of the second double magnetic tunnel junction on the fourth metal layer;

[0113] forming a third metal layer on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction;

[0114] forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the third metal layer;

[0115] forming a second metal layer on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction;

[0116] sequentially forming a free layer, a non-magnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction on the second metal layer;

[0117] A first metal layer is formed on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction.

[0118] In a seventh aspect, an embodiment of the present disclosure provides an MRAM memory cell based on a differential form, and the MRAM memory cell is prepared according to the preparation method described in any one of the fifth aspect and the sixth aspect.

[0119] In an eighth aspect, a chip is provided in an embodiment of the present disclosure, comprising the MRAM storage unit described in any one of the first aspect and the second aspect.

[0120] In a ninth aspect, a chip is provided in an embodiment of the present disclosure, comprising the MRAM storage unit described in any one of the seventh aspects.

[0121] In a tenth aspect, a chip is provided in an embodiment of the present disclosure, comprising the MRAM memory described in any one of the third aspects.

[0122] According to the technical solution provided by the embodiment of the present disclosure, a dual magnetic tunnel junction including a first magnetic tunnel junction and a second magnetic tunnel junction is innovatively introduced into the MRAM storage unit. The first and second magnetic tunnel junctions are mirror-set on both sides of the first metal layer, and their free layers are in electrical contact with the first metal layer, and the fixed layers are in electrical contact with the second and third metal layers, respectively. When the MRAM storage unit is written, data is written by applying a write current in different directions that runs through the dual magnetic tunnel junctions, and when the MRAM storage unit is read, data is read by judging the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction. Since the two MTJs are mirror-set, this symmetrical design makes the two MTJs relatively independent in physical position, but at the same time have similar electromagnetic properties. When there is strong magnetic field interference in the outside world, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. At the same time, under the condition of common-mode magnetic field interference, the magnetic resistance of the two MTJs changes synchronously with the external magnetic field interference, but the difference in magnetic resistance is not easy to change. By identifying the difference in magnetic resistance, the stored data can be effectively read, thereby ensuring the correct reading of the data, thereby effectively resisting external magnetic field interference.

[0123] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0125] Figure 1 A schematic diagram showing the structure of a differential MRAM storage unit according to an embodiment of the present disclosure is shown;

[0126] Figure 2 A schematic diagram showing a connection between a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure is shown;

[0127] Figure 3 A schematic diagram showing a connection between a differential MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure is shown;

[0128] Figure 4A schematic diagram showing a connection between a differential MRAM storage unit and a data reading circuit in a specific example of the present disclosure is shown;

[0129] Figure 5 A schematic structural diagram of another differential MRAM storage unit according to an embodiment of the present disclosure is shown;

[0130] Figure 6 A schematic diagram showing a connection between another differential-based MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure;

[0131] Figure 7 A schematic diagram showing a connection between another differential-based MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure;

[0132] Figure 8 A schematic diagram showing a connection between another differential-based MRAM storage unit and a data reading circuit in a specific example of the present disclosure is shown;

[0133] Fig. 9 A schematic diagram showing the structure of a differential-based MRAM storage cell array in a specific example of the present disclosure is shown;

[0134] Fig.10 A schematic diagram of the structure of a differential MRAM memory according to an embodiment of the present disclosure is shown;

[0135] Fig.11 A flowchart showing a method for preparing a differential MRAM memory cell according to an embodiment of the present disclosure is shown;

[0136] Fig.12 A flow chart showing another method for preparing a differential-based MRAM memory cell according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0137] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0138] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0139] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0140] As described above, when the MRAM memory in the prior art performs storage based on the traditional MTJ, the magnetization state inside the MTJ is easily disturbed by the strong external magnetic field, which affects the "free" ferromagnetic layer therein, causing its magnetization direction to change, thereby affecting the read and write accuracy and data reliability of the MRAM.

[0141] To overcome this problem, researchers are constantly exploring ways to improve MRAM's ability to resist interference from external magnetic fields. Currently, there are several ways:

[0142] 1. By integrating a magnetic shielding layer around or inside the MRAM chip, the impact of the external magnetic field on the MTJ storage unit is reduced. These shielding layers are usually made of high magnetic permeability materials, such as Permalloy. Although they can guide or disperse the external magnetic field, thereby protecting the magnetization state of the MTJ from interference, the high cost of these materials increases the production cost of MRAM. At the same time, the design of the magnetic shielding layer requires precise calculations to ensure that it can effectively guide or disperse the external magnetic field, which increases the complexity of the design. In addition, the introduction of the magnetic shielding layer will increase the size of the MRAM chip, affecting its use in highly integrated applications.

[0143] 2. Magnetic noise suppression technology is used to suppress magnetic noise, including using more accurate reading circuits, optimizing reading algorithms, and introducing error detection and correction mechanisms. Although the reading stability and accuracy of MRAM can be improved to a certain extent, optimizing reading algorithms and introducing error detection and correction mechanisms may increase the computational complexity and power consumption of the system.

[0144] 3. By introducing a multi-layer magnetic material structure into the MTJ, a more complex magnetization state is formed to improve the stability of the MTJ to the external magnetic field. The multi-layer structure can increase the magnetic anisotropy of the MTJ, making its magnetization state more difficult to be flipped by the external magnetic field. However, the design of the multi-layer magnetic material structure requires precise control of the thickness, composition and magnetic properties of each layer, and the multi-layer structure may introduce additional magnetic effects and interactions, which need to be carefully optimized to ensure that the overall performance of the MTJ is not affected, increasing the complexity and difficulty of the design.

[0145] It can be seen that the above-mentioned methods for improving the anti-interference capability of MRAM to external magnetic fields often increase the implementation cost and complexity, which limits the wide application of MRAM.

[0146] How can MRAM be effectively protected from external magnetic field interference while being simple to implement, so that it can be widely used? After repeated demonstrations and careful thinking, the inventors of the present disclosure proposed an MRAM storage cell based on differential form. Specifically, traditional MRAM storage cells usually adopt a single magnetic tunnel junction (MTJ) structure, while the present disclosure innovatively introduces a dual magnetic tunnel junction including a first magnetic tunnel junction and a second magnetic tunnel junction in the MRAM storage cell. The first and second magnetic tunnel junctions are mirrored on both sides of the first metal layer, and their free layers are both electrically in contact with the first metal layer, while the fixed layers are electrically in contact with the second and third metal layers, respectively. When a write operation is performed on the MRAM storage cell, data is written by applying write currents in different directions that pass through the dual magnetic tunnel junctions, and when a read operation is performed on the MRAM storage cell, data is read by judging the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction.

[0147] First, since the two MTJs are mirror images, this symmetrical design makes the two MTJs relatively independent in physical position, but at the same time have similar electromagnetic properties. When there is strong magnetic field interference from the outside, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. At the same time, under common-mode magnetic field interference conditions, the magnetic resistance of the two MTJs changes synchronously with the external magnetic field interference, but the difference in magnetic resistance is not easy to change. By identifying the difference in magnetic resistance, the stored data can be effectively read, thereby ensuring the correct reading of the data.

[0148] Secondly, through this mirror layout and contact method, the current path is optimized, ensuring that the current can maintain similar path length and resistance characteristics when flowing through the two MTJs, thereby reducing uneven current distribution and energy loss. At the same time, the mirror layout also helps to ensure the thermal and electrical symmetry of the two tunnel junctions, further improving the stability and reliability of the storage unit. In addition, compared with the method of setting two MTJs in parallel, this mirror layout and contact method, on the one hand, makes the two MTJs relatively independent in physical position, reduces the direct electromagnetic coupling and thermal coupling between them, thereby reducing mutual interference; on the other hand, it helps to achieve higher integration and storage density. By optimizing the unit structure and layout, more storage units can be integrated in the same area, thereby increasing the overall storage capacity.

[0149] Figure 1 FIG. 1 is a schematic diagram showing a structure of a differential MRAM storage unit according to an embodiment of the present disclosure. Figure 1As shown, the MRAM storage unit 100 includes: a MOS tube 130, a dual magnetic tunnel junction, a first metal layer, a second metal layer and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction 110 and a second magnetic tunnel junction 120; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 respectively include a fixed layer, a non-magnetic tunnel layer and a free layer arranged in sequence; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 are mirror-arranged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction 110 and the free layer of the second magnetic tunnel junction 120 are respectively electrically in contact with the first metal layer; the fixed layer of the first magnetic tunnel junction 110 is electrically in contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction 120 is electrically in contact with the third metal layer; the gate of the MOS tube 130 is connected to the word line, the source of the MOS tube 130 is connected to the source line, and the drain of the MOS tube 130 is connected to the third metal layer.

[0150] The "fixed layer" in the magnetic tunnel junction (for example, the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120) involved in the embodiments of the present disclosure is also called the "pinned ferromagnetic layer" or "reference layer". The magnetization direction of this layer is fixed and will not change easily with the external magnetic field or current; the "free layer" in the magnetic tunnel junction is also called the "free ferromagnetic layer". The magnetization direction of this layer can be changed according to the external magnetic field or current, so as to be parallel or anti-parallel to the magnetization direction of the fixed layer, which will put the magnetic tunnel junction in a low resistance state or a high resistance state, and the two resistance states can represent binary data "0" and "1" respectively; the "non-magnetic tunneling layer" in the magnetic tunnel junction is also called the "tunnel layer", "non-magnetic isolation layer" or "insulating barrier layer". This layer is usually made of insulating materials such as MgO, and is only a few atomic layers thick, allowing electrons to tunnel from one ferromagnetic layer to another ferromagnetic layer through the quantum tunneling effect.

[0151] In addition, the MRAM storage cell of the embodiment of the present disclosure is an improvement on the existing STT-MRAM storage cell. Among them, STT-MRAM is a new type of MRAM that realizes information writing through spin current. For the existing STT-MRAM storage cell, the writing principle is as follows:

[0152] The forward bit line current writes the information "1". When a high-density bit line current (containing an equal amount of electron flow with opposite spins) flows from the free layer to the fixed layer, the electrons exchange-couple with the magnetic moment in the fixed layer, allowing electrons with spins parallel to the magnetic moment of the fixed layer to pass through, while electrons with spins antiparallel to the magnetic moment of the fixed layer are reflected. The fixed layer acts as a "filter", reducing the number of electrons by half, forming a spin current. Since the fixed layer is thicker and has stronger magnetism, the spin moment of the reflected electrons is not enough to reverse the magnetic moment in the fixed layer. The spin electrons passing through the fixed layer cross the extremely thin non-magnetic isolation layer and reach the free layer, and exchange-couple with the magnetic moment of the free layer, causing the magnetic moment of the free layer to rotate in the opposite direction of the magnetic moment of the fixed layer. Finally, the magnetic moments of the two ferromagnetic layers are antiparallel, the resistance of the MTJ is large, and the STT-MRAM completes writing the information "1".

[0153] The reverse bit line current writes the information "0". If the current of the bit line is reversed, when the electrons with opposite spins flow through the free layer, the direction of the magnetic moment of the free layer remains unchanged, and the current magnitude remains unchanged. When passing through the extremely thin non-magnetic isolation layer to reach the fixed layer, the original spin state is still maintained. At this time, if the spin direction of the electron is consistent with the direction of the magnetic moment of the fixed layer, it will pass through the MTJ; if the spin direction is opposite to the direction of the magnetic moment of the fixed layer, it will be reflected. When the reflected spin electrons pass through the non-magnetic isolation layer again to reach the free layer, they transfer the spin moment to the magnetic moment of the free layer, increasing its precession angle until it reverses. At this time, the magnetic moments in the free layer and the fixed layer are arranged in parallel, the resistance of the MTJ is small, and the writing of the information "0" is achieved.

[0154] STT-MRAM polarizes the current through the fixed layer to form a spin current. The spin electrons in the spin current transfer the spin torque to the magnetic moment of the free layer, causing it to rotate according to the direction of the spin current, thereby writing information "0" or "1".

[0155] Based on the writing principle of the STT-MRAM storage unit as described above, it can be known that when the STT-MRAM storage unit is written, the direction of the write current (from the fixed layer to the free layer, or from the free layer to the fixed layer) is different, and the magnetic resistance of the MTJ is also different, that is: the magnetic resistance of the MTJ is related to the direction of the write current. The inventor of the present disclosure uses this correlation to combine two MTJs and set them in a mirror image. In this way, when there is a write current running through the MTJ combination, no matter what the direction of the write current is, the direction of the write current flowing through the two MTJs is bound to be different, resulting in the magnetic resistance of the two MTJs is bound to be different. When the write direction is changed, the magnetic resistance of the two MTJs will also change accordingly. Therefore, data is written based on the correspondence between the direction of the write current and the difference in magnetic resistance of the two MTJs.

[0156] Figure 2FIG. 1 is a schematic diagram showing a connection between a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure. Figure 2 As shown, when the MRAM storage unit 100 is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube 130 according to the write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage unit 100 through the write current, wherein the direction of the write current corresponds to the write data.

[0157] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction.

[0158] When the direction of the write current is the first direction, the write current is the first write current; when the direction of the write current is the second direction, the write current is the second write current.

[0159] According to an embodiment of the present disclosure, the direction of the write current corresponds to the write data, including:

[0160] The first write current corresponds to first write data; the second write current corresponds to second write data; wherein the first write data is 0 and the second write data is 1; or, the first write data is 1 and the second write data is 0.

[0161] According to an embodiment of the present disclosure, forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube according to the write data includes:

[0162] When the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube;

[0163] When the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

[0164] For example, the direction in which the write current flows from the second metal layer to the drain of the MOS tube can be preset as the first direction, and the direction in which the write current flows from the drain of the MOS tube to the second metal layer can be preset as the second direction. When writing to the MRAM storage unit, the first write current corresponding to the first direction corresponds to the write data "1", and the second write current corresponding to the second direction corresponds to the write data "0". In practical applications, the corresponding relationship can be set as needed.

[0165] When performing a write operation on the MRAM storage unit of the embodiment of the present disclosure according to a preset correspondence between a write current and write data, the data is written by controlling the direction of the write current flowing through the dual magnetic tunnel junction through a data write circuit connected to the MRAM storage unit.

[0166] In the present disclosure, in a differential MRAM storage cell, when a write operation is performed on the MRAM storage cell, the role of a MOS tube (metal oxide semiconductor field effect transistor) can be defined as: on the one hand, it acts as a switch during the write operation to control the on and off of the write current. When the voltage on the word line turns on the MOS tube, the data write circuit can provide a write current to the double magnetic tunnel junction through the MOS tube, thereby changing the magnetization state of the free layer according to the direction of the current to achieve data writing; on the other hand, it is used to control the flow direction of the write current, specifically: allowing or preventing the current in a specific direction from passing through its conduction state, so that different data can be written correspondingly through write currents in different directions.

[0167] Among them, the MOS tube can be a PMOS (P-type MOS tube) or an NMOS (N-type MOS tube). The following specifically describes the implementation process of performing a write operation on the MRAM storage unit of the embodiment of the present disclosure when the MOS tube is a PMOS tube and an NMOS tube.

[0168] When the MOS tube in the MRAM storage unit is an NMOS tube:

[0169] When a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube, a high level is input to the word line, and a forward bias voltage is applied between the gate and source of the MOS tube (this means that the write line voltage needs to be higher than the source line voltage by a certain value, and the specific value depends on the threshold voltage of the MOS tube), so that the MOS tube is turned on. At the same time, a first voltage is applied to the second metal layer, a second voltage is applied to the source line, and the first voltage is greater than the second voltage, thereby forming a first write current flowing from the second metal layer to the drain of the MOS tube and penetrating the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS tube.

[0170] When a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube, a high level is input to the word line, and a forward bias voltage is applied between the gate and source of the MOS tube (this means that the write line voltage needs to be higher than the source line voltage by a certain value, and the specific value depends on the threshold voltage of the MOS tube), so that the MOS tube is turned on. At the same time, a first voltage is applied to the source line (the first voltage should be less than the word line voltage), a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, so that a second write current is formed that flows from the drain of the MOS tube to the second metal layer and penetrating the dual magnetic tunnel junction, and the second write current flows out from the second metal layer.

[0171] When the MOS tube in the MRAM storage unit is a PMOS tube:

[0172] When a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube, a high level is input to the word line, and a negative bias voltage is applied between the gate and source of the MOS tube (this means that the write line voltage needs to be lower than the source line voltage by a certain value, and the specific value depends on the threshold voltage of the MOS tube), so that the MOS tube is turned on. At the same time, a first voltage is applied to the second metal layer, a second voltage is applied to the source line, and the first voltage is greater than the second voltage, thereby forming a first write current flowing from the second metal layer to the drain of the MOS tube and penetrating the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS tube.

[0173] When a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube, a high level is input to the word line, and a negative bias voltage is applied between the gate and the source of the MOS tube (this means that the write line voltage needs to be lower than the source line voltage by a certain value, and the specific value depends on the threshold voltage of the MOS tube), so that the MOS tube is turned on. At the same time, a first voltage is applied to the source line, a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, so that a second write current is formed that flows from the drain of the MOS tube to the second metal layer and penetrating the dual magnetic tunnel junction, and the second write current flows out from the second metal layer.

[0174] When a write current is generated and passes through the dual magnetic tunnel junction, a magnetic field is generated that is sufficient to change the magnetization direction of the free layer in the magnetic tunnel junction.

[0175] According to an embodiment of the present disclosure, writing the write data into the MRAM storage unit by the write current includes:

[0176] When the write current is the first write current, then:

[0177] The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization direction of the free layer of the first magnetic tunnel junction is opposite to that of the fixed layer of the first magnetic tunnel junction, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization direction of the free layer of the second magnetic tunnel junction is the same as that of the fixed layer of the second magnetic tunnel junction, and the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, thereby writing the first write data. In a specific embodiment, the first write data is 1.

[0178] When the write current is the second write current, then:

[0179] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization direction of the free layer of the first magnetic tunnel junction is the same as that of the fixed layer of the first magnetic tunnel junction, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization direction of the free layer of the second magnetic tunnel junction is opposite to that of the fixed layer of the second magnetic tunnel junction, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, thereby writing the second write data. In a specific embodiment, the second write data is 0.

[0180] Once the magnetization directions of the free layers corresponding to the first magnetic tunnel junction and the second magnetic tunnel junction in the dual magnetic tunnel junction are correctly set and the write current is turned off, the data of the MRAM storage cell is stably stored until the next write operation.

[0181] Figure 3 FIG. 2 shows a schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure. Figure 3 As shown, when the MRAM storage cell 100 is in a reading state, the first metal layer is connected to a first input terminal of a data reading circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data reading circuit. This connection mode allows the data reading circuit to simultaneously access the resistance characteristics of two magnetic tunnel junctions (the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120), so that the data reading circuit reads the data of the MRAM storage cell 100 according to the difference in magnetic resistance between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120, and the data of the MRAM storage cell 100 is output through the output terminal of the data reading circuit.

[0182] When performing a read operation on the MRAM storage unit, it is first necessary to start the data reading circuit to prepare it to receive and process the signal from the MRAM storage unit. According to the specific design of the MRAM, a small read current may be required to stabilize the state of the magnetic tunnel junction or increase the signal strength. After that, the data reading circuit measures the difference in magnetic resistance by comparing the current or voltage flowing through the two magnetic tunnel junctions. Since the magnetization direction of the free layer determines the resistance value of the magnetic tunnel junction, the difference in magnetic resistance can reflect the stored data.

[0183] Among them, the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetic resistance difference and a negative magnetic resistance difference. The positive magnetic resistance difference is formed because the magnetic resistance of the first magnetic tunnel junction is greater than the magnetic resistance of the second magnetic tunnel junction, and the negative magnetic resistance difference is formed because the magnetic resistance of the first magnetic tunnel junction is less than the magnetic resistance of the second magnetic tunnel junction.

[0184] In the present disclosure, in a differential MRAM storage cell, when a read operation is performed on the MRAM storage cell, the MOS tube performs isolation and protection functions, and is used to remain disconnected during the read operation, thereby isolating the data writing circuit and the data reading circuit, avoiding unnecessary interference. This isolation mechanism helps to ensure the accuracy and stability of the read data.

[0185] Figure 4 FIG. 1 shows a schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit in a specific example of the present disclosure. Figure 4 As shown, in the specific example, the data reading circuit is implemented by a differential comparator, and the data of the MRAM storage unit 100 is read by comparing the voltages of the negative electrode and the positive electrode of the differential comparator. The second metal layer and the third metal layer are respectively connected to the positive electrode of the differential comparator through a resistor R with the same resistance value.

[0186] According to an embodiment of the present disclosure, reading data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0187] A voltage difference between a first input terminal and a second input terminal of the data reading circuit is determined according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction.

[0188] Specifically, when the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit. When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit.

[0189] The data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0190] Specifically, when the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data. When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

[0191] exist Figure 4 In the differential comparator, the negative voltage V - It can be expressed as follows:

[0192]

[0193] The positive voltage of the differential comparator V + It can be expressed as follows:

[0194]

[0195] Wherein, V1 is the voltage of the first magnetic tunnel junction when the MRAM storage cell is read, V2 is the voltage of the second magnetic tunnel junction when the MRAM storage cell is read, R1 is the magnetic resistance of the first magnetic tunnel junction when the MRAM storage cell is read, R2 is the resistance of the first magnetic tunnel junction when the MRAM storage cell is read, and R is Figure 4 The resistance value of the resistor R.

[0196] According to the above two formulas, when R1 is larger than R2, that is, when the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the negative voltage V - Less than the positive voltage V of the differential comparator + , the differential comparator outputs a high level, and the read data is 1, that is, the first written data is 1. If R1 is smaller than R2, that is, when the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the negative voltage V -Greater than the positive voltage V of the differential comparator + , the differential comparator outputs a low level, and the read data is 0, that is, the second written data is 0.

[0197] Figure 5 A schematic diagram of the structure of another MRAM storage unit based on a differential form according to an embodiment of the present disclosure is shown. The MRAM storage unit 500 includes: a MOS tube, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer; wherein the three dual magnetic tunnel junctions are: a first dual magnetic tunnel junction 510, a second dual magnetic tunnel junction 520 and a third dual magnetic tunnel junction 530, and the dual magnetic tunnel junctions include: a first magnetic tunnel junction 110 and a second magnetic tunnel junction 120; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 respectively include a fixed layer, a non-magnetic tunnel layer and a free layer arranged in sequence.

[0198] The first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 and the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 are mirror-arranged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 and the free layer of the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 are respectively electrically contacted with the first metal layer; the fixed layer of the first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 is electrically contacted with the second metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 is electrically contacted with the third metal layer.

[0199] The first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 and the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 are mirror-arranged on both sides of the fourth metal layer, and the free layer of the first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 and the free layer of the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 are respectively electrically contacted with the fourth metal layer; the fixed layer of the first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 is electrically contacted with the third metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 is electrically contacted with the fifth metal layer.

[0200] The first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 and the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 are mirror-arranged on both sides of the sixth metal layer, and the free layer of the first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 and the free layer of the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 are respectively electrically contacted with the sixth metal layer; the fixed layer of the first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 is electrically contacted with the fifth metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 is electrically contacted with the seventh metal layer.

[0201] The gate of the MOS transistor 130 is connected to the word line, the source of the MOS transistor 130 is connected to the source line, and the drain of the MOS transistor 130 is connected to the seventh metal layer.

[0202] Figure 6 FIG. 2 shows another schematic diagram of connecting a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure. Figure 6 As shown, when the MRAM storage unit 500 is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the first dual magnetic tunnel junction 510, the second dual magnetic tunnel junction 520 and the third dual magnetic tunnel junction 530 is formed between the second metal layer and the drain of the MOS tube 130 according to the write data, so that the data write circuit writes the write data into the MRAM storage unit 500 through the write current, wherein the direction of the write current corresponds to the write data.

[0203] In specific Figure 6 When performing a write operation on the MRAM storage cell 500 shown in FIG. Figure 1 The writing process of the MRAM storage unit shown in FIG. Figure 6 In the MRAM storage unit 500 shown, one writing process can sequentially write write data into the first double magnetic tunnel junction 510 , the second double magnetic tunnel junction 520 , and the third double magnetic tunnel junction 530 .

[0204] Figure 7 FIG. 2 shows another schematic diagram of connecting a differential MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure. Figure 7As shown, when the MRAM storage unit 500 is in a reading state, the first metal layer, the fourth metal layer and the sixth metal layer are respectively connected to the first input terminal of the data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are respectively connected to the second input terminal of the data reading circuit, so that the data reading circuit reads the data of the MRAM storage unit 500 according to the magnetoresistance difference between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 of each double magnetic tunnel junction, and the data of the MRAM storage unit 500 is output through the output terminal of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction 110 is greater than the magnetoresistance of the second magnetic tunnel junction 120, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction 110 is less than the magnetoresistance of the second magnetic tunnel junction 120.

[0205] Figure 8 FIG. 2 shows another schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit in a specific example of the present disclosure. Figure 8 As shown, in the specific example, the data reading circuit includes: a first data reading circuit, a second data reading circuit, a third data reading circuit and a logic integration circuit, and the output ends of the first data reading circuit, the second data reading circuit and the third data reading circuit are respectively connected to the logic integration circuit. The first data reading circuit, the second data reading circuit and the third data reading circuit are respectively implemented by differential comparators, and the logic integration circuit can construct the required logic operation through standard CMOS logic gates (such as AND gates and OR gates).

[0206] like Figure 8 As shown, the first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

[0207] According to an embodiment of the present disclosure, the data reading circuit reads data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of each double magnetic tunnel junction, including:

[0208] The first data reading circuit determines the first read data according to the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1; ​​the second data reading circuit determines the second read data according to the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2; the third data reading circuit determines the third read data according to the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3.

[0209] The logic integration circuit determines data of the MRAM storage unit according to the first read data, the second read data and the third read data, and the data of the MRAM storage unit is output through an output terminal of the logic integration circuit.

[0210] The data D of the MRAM storage unit is expressed by the following formula:

[0211] D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

[0212] The logical operator ∧ represents logical AND, and ∨ represents logical OR.

[0213] The logical meaning of the above formula is: when any two of D1, D2 and D3 are 1, D is 1; when any two of them are 0, D is 0.

[0214] In specific Figure 6 When performing a read operation on the MRAM storage cell shown in FIG. Figure 1 The reading process of the MRAM storage unit shown in FIG. Figure 6 The MRAM storage unit shown first reads the write data stored in the first double magnetic tunnel junction, the second double magnetic tunnel junction and the third double magnetic tunnel junction respectively through the first data reading circuit, the second data reading circuit and the third data reading circuit, and then performs a logic integration operation on the respectively read write data, and uses the final result after the operation as the write data of the MRAM storage unit.

[0215] Figure 6 Another MRAM storage cell based on a differential form according to the embodiment of the present disclosure is shown. Figure 1 The MRAM storage cell based on the differential form of the embodiment of the present disclosure shown has the following beneficial effects:

[0216] 1. Improve the reliability and fault tolerance of data storage. Figure 6The MRAM memory cell shown contains three dual magnetic tunnel junctions (i.e., six magnetic tunnel junctions). This multiple structure makes data storage more reliable. Even if one or two of the dual magnetic tunnel junctions fail or are misread, the data in the other structures can still remain accurate, thereby improving overall fault tolerance and reliability.

[0217] 2. Enhanced resistance to external interference. The design of multiple dual magnetic tunnel junctions reduces the sensitivity of MRAM storage cells to external electromagnetic interference. Even if there is a certain degree of interference, the correct write data can be determined according to the majority principle based on the voting principle, reducing the impact of interference on data reading accuracy.

[0218] on the contrary, Figure 1 The embodiment of the present disclosure shown is a differential MRAM storage unit, compared with Figure 6 Another MRAM storage unit based on differential form in the embodiment of the present disclosure is simpler to implement, and has relatively lower cost and power consumption. In specific implementation, trade-offs can be made according to specific application scenarios and requirements. For example, in application scenarios with high requirements for fault tolerance and reliability, such as aerospace, military equipment and other fields, it can be applied Figure 6 The MRAM storage cell shown can be used in resource-constrained environments. Figure 1 The MRAM memory cell shown.

[0219] The present disclosure also provides an MRAM memory cell array based on a differential form. The MRAM memory cell array includes: N MRAM memory cells described in any one of the above described items arranged in an array, and N MOS tubes corresponding to the N MRAM memory cells one by one, wherein N is an integer greater than 1. The second metal layer of each MRAM memory cell is connected to the source of the MOS tube corresponding to the MRAM memory cell, and the drains of the N MOS are connected and then connected to the first source line; the sources of the MOS tubes of each MRAM memory cell are connected to each other and then connected to the second source line; the gate of the MOS tube corresponding to the MRAM memory cell is connected to the gate of the MOS tube of the MRAM memory cell and then connected to the word line of the corresponding MRAM memory cell; the first metal layer of each MRAM memory cell is connected to the first input end of the data reading circuit; the first source line and the second source line are respectively connected to the second input end of the data reading circuit, and the output end of the data reading circuit is connected to the bit line.

[0220] Fig. 9 FIG. 1 is a schematic diagram showing a structure of a differential MRAM storage cell array in a specific example of the present disclosure. In the specific example, the MRAM storage cell array includes two Figure 1Taking the MRAM storage cell shown in the figure and the data reading circuit being implemented by a differential comparator as an example, the structure of the MRAM storage cell array is described.

[0221] like Fig. 9 As shown, the MRAM storage cell array includes: 2 arranged in an array as shown in Figure 1 The MRAM storage units shown are respectively a first MRAM storage unit and a second MRAM storage unit, and two MOS transistors corresponding to the two MRAM storage units are respectively a first MOS transistor and a second MOS transistor, wherein the first MOS transistor corresponds to the first MRAM storage unit, and the second MOS transistor corresponds to the second MRAM storage unit.

[0222] The second metal layer of the first MRAM storage unit is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the drain of the second MOS transistor and then connected to the first source line; the sources of the MOS transistors 130 in the first MRAM storage unit and the second MRAM storage unit are connected to each other and then connected to the second source line; the gates of the first MOS transistor and the second MOS transistor are respectively connected to the gates of the MOS transistors 130 of the first MRAM storage unit and the second MRAM storage unit and then connected to their respective word lines, that is: the gate of the first MOS transistor is connected to the gate of the MOS transistor 130 of the first MRAM storage unit and then connected to the first word line, and the gate of the second MOS transistor is connected to the gate of the MOS transistor 130 of the second MRAM storage unit and then connected to the second word line. The first metal layers of the first MRAM storage unit and the second MRAM storage unit are connected to the first input end of the data reading circuit; the first source line and the second source line are respectively connected to the second input end of the data reading circuit.

[0223] In the right Fig. 9 When the MRAM memory cell array shown is performing a write operation, if the first MRAM memory cell corresponding to the first word line needs to be written, the first word line is controlled to be high level and the second word line is controlled to be low level to achieve gating of the first MRAM memory cell, and the MOS transistor 130 and the first MOS transistor in the first MRAM memory cell are in a conducting state. The MOS transistor 130 and the second MOS transistor in the second MRAM memory cell are not conducting and are in an off state.

[0224] In a specific implementation, if data 1 needs to be written, the first source line voltage is controlled to be greater than the second source line voltage, so that current flows from top to bottom. Then, the magnetic resistance of the first magnetic tunnel junction of the first MRAM storage unit is large, and the magnetic resistance of the second magnetic tunnel junction of the first MRAM storage unit is small. The difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive difference in magnetic resistance, thereby writing data 1.

[0225] If data 0 needs to be written, the first source line voltage is controlled to be less than the second source line voltage, so that current flows from bottom to top. Then, the magnetic resistance of the first magnetic tunnel junction of the first MRAM storage unit is small, and the magnetic resistance of the second magnetic tunnel junction of the first MRAM storage unit is large. The difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative difference in magnetic resistance, so that data 0 is written.

[0226] In the right Fig. 9 When the MRAM memory cell array shown is performing a read operation, it is confirmed that no write operation is in progress and all necessary control signals (such as word lines and source lines) have been set to the level of the read mode. At this time, the differential comparator compares the voltages of the positive and negative poles. If the negative voltage is lower than the positive voltage, it is a positive difference in magnetic resistance, and the differential comparator outputs a high level, and the data of the MRAM memory cell read is 1; if the negative voltage is higher than the positive voltage, it is a negative difference in magnetic resistance, and the differential comparator outputs a low level, and the data of the MRAM memory cell read is 0. The differential comparator outputs the read data to the bit line through the output terminal for subsequent processing or display. The bit line is usually designed as 1 group, 8 groups, 16 groups, 32 groups or 64 groups.

[0227] Fig.10 FIG. 2 shows a schematic diagram of a structure of a differential MRAM memory according to an embodiment of the present disclosure. Fig.10 As shown, the MRAM memory includes: an MRAM storage cell array cluster, a data writing circuit and a data reading circuit; the MRAM storage cell array cluster includes one or more MRAM storage cell arrays as described above. For the sake of clarity, Fig.10 An address decoder is also shown in FIG. 4 , which is not included in the MRAM memory.

[0228] The input end of the data writing circuit is connected to the external IO port for receiving writing data.

[0229] The output end of the data writing circuit is connected to the word line corresponding to the MRAM memory cell in the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data.

[0230] The data writing circuit is configured to form a writing current that penetrates the dual magnetic tunnel junctions of the MRAM memory cells in the MRAM memory cell array between the second metal layer of the MRAM memory cells in the MRAM memory cell array and the drain of the MOS tube of the MRAM memory cells in the MRAM memory cell array according to the writing data, and write the writing data into the MRAM memory cells in the MRAM memory cell array through the writing current, wherein the direction of the writing current corresponds to the writing data.

[0231] The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0232] During the writing process to the MRAM memory, the address decoder controls the word lines of the MRAM memory cells in the MRAM memory cell array, thereby controlling the gating of the corresponding MRAM memory cells.

[0233] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction; when the direction of the write current is the first direction, the write current is the first write current; when the direction of the write current is the second direction, the write current is the second write current; the direction of the write current corresponds to the write data, including: the first write current corresponds to the first write data; the second write current corresponds to the second write data; wherein the first write data is 0 and the second write data is 1; or, the first write data is 1 and the second write data is 0.

[0234] According to an embodiment of the present disclosure, the write current penetrating the dual magnetic tunnel junction of the MRAM storage cell in the MRAM storage cell array is formed between the second metal layer of the MRAM storage cell in the MRAM storage cell array and the drain of the MOS tube of the MRAM storage cell in the MRAM storage cell array according to the write data, including: when the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube; when the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

[0235] According to an embodiment of the present disclosure, forming a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube includes:

[0236] When a high level is input to the word line to turn on the MOS tube, and at the same time a first voltage is applied to the second metal layer, a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS tube and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS tube.

[0237] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises:

[0238] When a high level is input to the word line to turn on the MOS tube, and at the same time a first voltage is applied to the source line, a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is formed that flows from the drain of the MOS tube to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer; wherein, turning on the MOS tube includes: when the MOS tube is an NMOS tube, applying a forward bias voltage between the gate and the source of the MOS tube, and when the MOS tube is a PMOS tube, applying a negative bias voltage between the gate and the source of the MOS tube, so that the MOS tube is turned on.

[0239] According to an embodiment of the present disclosure, writing the write data into the MRAM storage unit by the write current includes:

[0240] When the write current is the first write current, then:

[0241] The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, thereby writing the first write data.

[0242] When the write current is the second write current, then:

[0243] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

[0244] According to an embodiment of the present disclosure, the method of reading data of the MRAM memory cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array includes:

[0245] The voltage difference between the first input terminal and the second input terminal of the data reading circuit is determined according to the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction; and the data of the MRAM storage unit is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0246] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0247] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; when the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; reading data of the MRAM storage unit according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit comprises:

[0248] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data; when the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

[0249] Fig.11 A flowchart of a method for preparing a differential MRAM storage cell according to an embodiment of the present disclosure is shown. The MRAM storage cell comprises: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer and a third metal layer; wherein the dual magnetic tunnel junction comprises: a first magnetic tunnel junction and a second magnetic tunnel junction, such as Fig.11 As shown, the preparation method includes the following steps S1110 to S1160:

[0250] In step S1110 , the MOS transistor is formed, and the MOS transistor is located at the bottom of the MRAM storage unit.

[0251] When the MOS tube is specifically formed, the following steps are followed:

[0252] 1. Substrate preparation: First, select a suitable semiconductor substrate (such as silicon wafer) and perform cleaning and pretreatment, such as chemical mechanical polishing (CMP) to remove surface impurities and oxide layers. When selecting a substrate, if the MOS tube to be formed is a PMOS tube, select a P-type silicon wafer as the substrate; if the MOS tube to be formed is an NMOS tube, select an N-type silicon wafer as the substrate.

[0253] 2. Isolation region formation: An isolation region is formed on the substrate through shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technology to define the active area of ​​the MOS tube.

[0254] 3. Gate oxide layer growth: A layer of high-quality silicon dioxide (SiO2) is grown on the active area as the gate oxide layer.

[0255] 4. Gate formation: The gate pattern is defined using photolithography and etching techniques, and then the gate structure is formed by metal deposition (such as polysilicon or polysilicon / metal stack) and back etching.

[0256] 5. Source and drain region doping: Ion implantation technology is used to form source and drain regions in the active areas on both sides of the gate, and annealing is performed to activate the doped atoms.

[0257] When forming source and drain regions in the active regions on both sides of the gate by ion implantation technology, if the formed MOS tube is a PMOS tube, the source and drain need to be N-type doped to form N-type regions, and the electrons in these regions will be repelled into the channel, leaving holes as conductive carriers, and then, N-type impurities (such as phosphorus P or arsenic As) are injected into the active regions on both sides of the gate by ion implantation technology to form source and drain regions; if the formed MOS tube is an NMOS tube, the source and drain need to be P-type doped to form P-type regions, and the holes in these regions will be repelled into the channel, leaving electrons as conductive carriers, and then, P-type impurities (such as boron B or indium In) are injected into the active regions on both sides of the gate by ion implantation technology to form source and drain regions.

[0258] 6. Passivation layer deposition: Deposit a layer of silicon nitride (Si3N4) or silicon dioxide as a passivation layer to protect the MOS tube from the impact of subsequent processes.

[0259] In step S1120, the third metal layer is formed on the MOS transistor.

[0260] When the third metal layer is specifically formed, the following steps are followed:

[0261] 1. Opening: Open a contact hole on the passivation layer through photolithography and etching technology to connect to the drain of the MOS tube.

[0262] 2. Metal deposition: Use physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating to deposit a third metal layer (such as copper, aluminum or copper alloy) on the contact hole and the top of the exposed MOS tube to form a conductive path.

[0263] 3. Planarization: Use chemical mechanical polishing (CMP) and other technologies to remove excess metal and flatten the surface.

[0264] In step S1130 , a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction are sequentially formed on the third metal layer.

[0265] Specifically, a layer of magnetic material (such as cobalt iron boron CoFeB) is deposited on the third metal layer through sputtering or evaporation technology as a fixed layer of the second magnetic tunnel junction, and then a layer of non-magnetic insulating material (such as magnesium oxide MgO) is deposited on the fixed layer as a non-magnetic tunneling layer, and its thickness is controlled to achieve a quantum tunneling effect. Finally, a layer of magnetic material is deposited on the non-magnetic tunneling layer as a free layer, and its magnetization direction can change with the external magnetic field.

[0266] In step S1140 , the first metal layer is formed on the free layer of the second magnetic tunnel junction.

[0267] In step S1150 , a free layer, a non-magnetic tunneling layer, and a fixed layer of the first magnetic tunnel junction are sequentially formed on the first metal layer.

[0268] In step S1160 , the second metal layer is formed on the fixed layer of the first magnetic tunnel junction.

[0269] It should be noted that during the entire preparation process, conditions such as temperature, pressure and atmosphere are strictly controlled to avoid material contamination and performance degradation.

[0270] Fig.12 A flowchart of another method for preparing a differential MRAM storage cell according to an embodiment of the present disclosure is shown. The MRAM storage cell includes: a MOS tube, a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, a third dual magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction. Fig.12 As shown, the preparation method includes the following steps S1210 to S1270:

[0271] In step S1210, the MOS transistor is formed, and the MOS transistor is located at the bottom of the MRAM storage unit; and the seventh metal layer is formed on the MOS transistor.

[0272] In step S1220, a fixed layer, a nonmagnetic tunneling layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are sequentially formed on the seventh metal layer; and the sixth metal layer is formed on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction.

[0273] In step S1230, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction are sequentially formed on the sixth metal layer; and the fifth metal layer is formed on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction.

[0274] In step S1240, a fixed layer, a nonmagnetic tunneling layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are sequentially formed on the fifth metal layer; and a fourth metal layer is formed on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction.

[0275] In step S1250, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction are sequentially formed on the fourth metal layer; and a third metal layer is formed on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction.

[0276] In step S1260, a fixed layer, a nonmagnetic tunneling layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are sequentially formed on the third metal layer; and a second metal layer is formed on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction.

[0277] In step S1270, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction are sequentially formed on the second metal layer; and a first metal layer is formed on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction.

[0278] The present disclosure also provides a differential-based MRAM storage unit, wherein the MRAM storage unit is prepared according to any one of the preparation methods described in the present disclosure.

[0279] The present disclosure also provides a chip, comprising the MRAM storage unit described in any one of the embodiments of the present disclosure.

[0280] The present disclosure also provides a chip, comprising the MRAM memory described in any one of the embodiments of the present disclosure.

[0281] According to the technical solution provided in the embodiment of the present disclosure, according to the technical solution provided in the embodiment of the present disclosure, a dual magnetic tunnel junction including a first magnetic tunnel junction and a second magnetic tunnel junction is innovatively introduced into the MRAM storage unit. The first and second magnetic tunnel junctions are mirror-set on both sides of the first metal layer, their free layers are in electrical contact with the first metal layer, and the fixed layers are in electrical contact with the second and third metal layers respectively. When the MRAM storage unit is written, data is written by applying write currents in different directions that pass through the dual magnetic tunnel junctions, and when the MRAM storage unit is read, data is read by judging the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction. Since the two MTJs are mirror-set, this symmetrical design makes the two MTJs relatively independent in physical position, but at the same time have similar electromagnetic characteristics. When there is strong magnetic field interference in the outside world, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. At the same time, under common-mode magnetic field interference conditions, the two MTJ magnetic resistances change synchronously with the external magnetic field interference, but the magnetic resistance difference is not easy to change. By identifying the magnetic resistance difference, the stored data can be effectively read, thereby ensuring the correct reading of the data, thereby effectively resisting external magnetic field interference.

[0282] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A differential MRAM storage cell, characterized in that: The MRAM storage unit comprises: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer and a third metal layer; wherein the dual magnetic tunnel junction comprises: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively comprise a fixed layer, a non-magnetic tunnel layer and a free layer which are arranged in sequence; The first magnetic tunnel junction and the second magnetic tunnel junction are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction and the free layer of the second magnetic tunnel junction are respectively in electrical contact with the first metal layer; the fixed layer of the first magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction is in electrical contact with the third metal layer; The gate of the MOS tube is connected to the word line, the source of the MOS tube is connected to the source line, and the drain of the MOS tube is connected to the third metal layer; When the MRAM storage unit is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage unit through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM storage unit is in a read state, the first metal layer is connected to a first input terminal of a data reading circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data reading circuit, so that the data reading circuit reads data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, and the data of the MRAM storage unit is output through an output terminal of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

2. The MRAM storage cell according to claim 1, characterized in that: The direction of the write current includes a first direction and a second direction; When the direction of the write current is the first direction, the write current is the first write current; When the direction of the write current is the second direction, the write current is the second write current; The direction of the write current corresponds to the write data, including: The first write current corresponds to the first write data; the second write current corresponds to the second write data; The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

3. The MRAM storage cell according to claim 2, characterized in that: The step of forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube according to the write data comprises: When the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube; When the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

4. The MRAM storage cell according to claim 3, characterized in that: The forming of a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor; The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is formed that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer; Wherein, turning on the MOS tube includes: when the MOS tube is an NMOS tube, applying a forward bias voltage between the gate and the source of the MOS tube; when the MOS tube is a PMOS tube, applying a negative bias voltage between the gate and the source of the MOS tube, so that the MOS tube is turned on.

5. The MRAM storage cell according to claim 4, characterized in that: Writing the write data into the MRAM storage unit by the write current includes: When the write current is the first write current, then: The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, thereby writing the first write data; When the write current is the second write current, then: The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, thereby writing the second write data.

6. The MRAM storage cell according to claim 2, characterized in that: The method of reading data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes: determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction; The data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

7. The MRAM memory cell according to claim 6, wherein: The step of determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction comprises: When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit comprises: When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data; When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

8. A differential MRAM storage cell, characterized in that: The MRAM storage unit comprises: a MOS tube, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer; wherein the three dual magnetic tunnel junctions are respectively: a first dual magnetic tunnel junction, a second dual magnetic tunnel junction and a third dual magnetic tunnel junction, and the dual magnetic tunnel junctions include: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer and a free layer which are arranged in sequence; The first magnetic tunnel junction of the first double magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction of the first double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are electrically in contact with the first metal layer respectively; the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction is electrically in contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction of the first double magnetic tunnel junction is electrically in contact with the third metal layer; The first magnetic tunnel junction of the second double magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction are mirror-imaged on both sides of the fourth metal layer, and the free layer of the first magnetic tunnel junction of the second double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are electrically in contact with the fourth metal layer respectively; the fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction is electrically in contact with the third metal layer, and the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction is electrically in contact with the fifth metal layer; The first magnetic tunnel junction of the third double magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction are mirror-arranged on both sides of the sixth metal layer, and the free layer of the first magnetic tunnel junction of the third double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are respectively in electrical contact with the sixth metal layer; the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the fifth metal layer, and the fixed layer of the second magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the seventh metal layer; The gate of the MOS tube is connected to the word line, the source of the MOS tube is connected to the source line, and the drain of the MOS tube is connected to the seventh metal layer; When the MRAM storage unit is in a write state, the second metal layer, the word line and the source line are respectively connected to a data write circuit, and a write current penetrating the first dual magnetic tunnel junction, the second dual magnetic tunnel junction and the third dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube according to write data, so that the data write circuit writes the write data into the MRAM storage unit through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM storage unit is in a read state, the first metal layer, the fourth metal layer and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, so that the data reading circuit reads data of the MRAM storage unit according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, and the data of the MRAM storage unit is output through an output terminal of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

9. The MRAM storage cell according to claim 8, characterized in that: The data reading circuit comprises: a first data reading circuit, a second data reading circuit, a third data reading circuit and a logic integration circuit, wherein the output ends of the first data reading circuit, the second data reading circuit and the third data reading circuit are respectively connected to the logic integration circuit; The first metal layer, the fourth metal layer and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, including: The first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

10. The MRAM storage cell according to claim 9, characterized in that: The data reading circuit reads data of the MRAM storage unit according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of each double magnetic tunnel junction, including: The first data reading circuit determines first read data according to a magnetic resistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1; The second data reading circuit determines second read data according to a magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2; The third data reading circuit determines the third read data according to the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3; The logic integration circuit determines the data of the MRAM storage unit according to the first read data, the second read data and the third read data, and the data of the MRAM storage unit is output through the output terminal of the logic integration circuit; The data D of the MRAM storage unit is expressed by the following formula: D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

11. A differential MRAM storage cell array, characterized in that: include: N MRAM storage units according to any one of claims 1 to 10 arranged in an array, and N MOS transistors corresponding one-to-one to the N MRAM storage units, wherein N is an integer greater than 1; The second metal layer of each MRAM storage unit is connected to the source of the MOS tube corresponding to the MRAM storage unit, and the drains of the N MOS tubes are connected to the first source line; The sources of the MOS tubes of each MRAM storage unit are connected to each other and then connected to the second source line; the gates of the MOS tubes corresponding to the MRAM storage units are connected to the gates of the MOS tubes of the MRAM storage units and then connected to the word lines corresponding to the MRAM storage units; The first metal layer of each MRAM storage cell is connected to the first input terminal of the data reading circuit; The first source line and the second source line are respectively connected to the second input terminal of the data reading circuit; An output terminal of the data reading circuit is connected to a bit line.

12. A differential MRAM memory, characterized in that: include: MRAM memory cell array cluster, data writing circuit and data reading circuit; The MRAM memory cell array cluster comprises one or more MRAM memory cell arrays according to claim 11; The input end of the data writing circuit is connected to the external IO port for receiving the writing data; The output end of the data writing circuit is connected to the word line of the MRAM memory cell in the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data; The data writing circuit is configured to form a writing current that penetrates the dual magnetic tunnel junctions of the MRAM storage cells in the MRAM storage cell array between the second metal layer of the MRAM storage cells in the MRAM storage cell array and the drain of the MOS tube of the MRAM storage cells in the MRAM storage cell array according to the writing data, and write the writing data into the MRAM storage cells in the MRAM storage cell array through the writing current, wherein the direction of the writing current corresponds to the writing data; The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

13. The MRAM memory according to claim 12, characterized in that: The direction of the write current includes a first direction and a second direction; When the direction of the write current is the first direction, the write current is the first write current; When the direction of the write current is the second direction, the write current is the second write current; The direction of the write current corresponds to the write data, including: The first write current corresponds to the first write data; the second write current corresponds to the second write data; The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

14. The MRAM memory according to claim 13, characterized in that: The step of forming a write current penetrating a dual magnetic tunnel junction of an MRAM storage cell in the MRAM storage cell array between a second metal layer of the MRAM storage cell in the MRAM storage cell array and a drain of a MOS tube of the MRAM storage cell in the MRAM storage cell array according to the write data comprises: When the write data is the first write data, a first write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube; When the write data is the second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS tube.

15. The MRAM memory according to claim 14, characterized in that: The forming of a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor; The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS tube comprises: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is formed that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer; Wherein, turning on the MOS tube includes: when the MOS tube is an NMOS tube, applying a forward bias voltage between the gate and the source of the MOS tube; when the MOS tube is a PMOS tube, applying a negative bias voltage between the gate and the source of the MOS tube, so that the MOS tube is turned on.

16. The MRAM memory according to claim 15, characterized in that: Writing the write data into the MRAM storage unit by the write current includes: When the write current is the first write current, then: The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low resistance state, thereby writing the first write data; When the write current is the second write current, then: The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

17. The MRAM memory according to claim 13, characterized in that: The method of reading data of the MRAM memory cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array comprises: determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction; The data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

18. The MRAM memory according to claim 17, characterized in that: The step of determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction comprises: When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; When the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit comprises: When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the first write data; When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data of the MRAM storage unit read is the second write data.

19. A method for preparing a differential MRAM storage cell, characterized in that: The MRAM storage unit includes: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes: Forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit; Forming the third metal layer on the MOS tube; forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction in sequence on the third metal layer; forming the first metal layer on the free layer of the second magnetic tunnel junction; forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction in sequence on the first metal layer; The second metal layer is formed on the fixed layer of the first magnetic tunnel junction.

20. A method for preparing a differential MRAM storage cell, characterized in that: The MRAM storage unit includes: a MOS tube, a first double magnetic tunnel junction, a second double magnetic tunnel junction, a third double magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer; wherein the double magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes: Forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit; forming the seventh metal layer on the MOS tube; forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the seventh metal layer; forming the sixth metal layer on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction; forming a free layer, a non-magnetic tunnel layer and a fixed layer of a first magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the sixth metal layer; forming the fifth metal layer on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction; forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fifth metal layer; forming a fourth metal layer on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction; forming a free layer, a non-magnetic tunnel layer and a fixed layer of a first magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fourth metal layer; forming a third metal layer on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction; forming a fixed layer, a non-magnetic tunnel layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the third metal layer; forming a second metal layer on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction; sequentially forming a free layer, a non-magnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction on the second metal layer; A first metal layer is formed on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction.

21. A differential MRAM storage cell, characterized in that: The MRAM storage unit is manufactured according to the manufacturing method described in any one of claims 19 to 20.

22. A chip, characterized in that: The invention comprises the MRAM memory cell according to any one of claims 1 to 10.

23. A chip, characterized in that: Comprising the MRAM memory cell of claim 21.

24. A chip, characterized in that: The MRAM memory comprises the MRAM memory according to any one of claims 12 to 18.

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